2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
26 static void ar71xx_gpio_irq_dispatch(void)
28 void __iomem *base = ar71xx_gpio_base;
31 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
32 __raw_readl(base + GPIO_REG_INT_ENABLE);
35 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
40 static void ar71xx_gpio_irq_unmask(struct irq_data *d)
42 unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
43 void __iomem *base = ar71xx_gpio_base;
46 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
47 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
50 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
53 static void ar71xx_gpio_irq_mask(struct irq_data *d)
55 unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
56 void __iomem *base = ar71xx_gpio_base;
59 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
60 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
63 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
66 static struct irq_chip ar71xx_gpio_irq_chip = {
67 .name = "AR71XX GPIO",
68 .irq_unmask = ar71xx_gpio_irq_unmask,
69 .irq_mask = ar71xx_gpio_irq_mask,
70 .irq_mask_ack = ar71xx_gpio_irq_mask,
73 static struct irqaction ar71xx_gpio_irqaction = {
75 .name = "cascade [AR71XX GPIO]",
78 #define GPIO_INT_ALL 0xffff
80 static void __init ar71xx_gpio_irq_init(void)
82 void __iomem *base = ar71xx_gpio_base;
85 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
86 __raw_writel(0, base + GPIO_REG_INT_PENDING);
88 /* setup type of all GPIO interrupts to level sensitive */
89 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
91 /* setup polarity of all GPIO interrupts to active high */
92 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
94 for (i = AR71XX_GPIO_IRQ_BASE;
95 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
96 irq_set_chip_and_handler(i, &ar71xx_gpio_irq_chip,
99 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
102 static void ar71xx_misc_irq_dispatch(void)
106 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
107 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
109 if (pending & MISC_INT_UART)
110 do_IRQ(AR71XX_MISC_IRQ_UART);
112 else if (pending & MISC_INT_DMA)
113 do_IRQ(AR71XX_MISC_IRQ_DMA);
115 else if (pending & MISC_INT_PERFC)
116 do_IRQ(AR71XX_MISC_IRQ_PERFC);
118 else if (pending & MISC_INT_TIMER)
119 do_IRQ(AR71XX_MISC_IRQ_TIMER);
121 else if (pending & MISC_INT_OHCI)
122 do_IRQ(AR71XX_MISC_IRQ_OHCI);
124 else if (pending & MISC_INT_ERROR)
125 do_IRQ(AR71XX_MISC_IRQ_ERROR);
127 else if (pending & MISC_INT_GPIO)
128 ar71xx_gpio_irq_dispatch();
130 else if (pending & MISC_INT_WDOG)
131 do_IRQ(AR71XX_MISC_IRQ_WDOG);
133 else if (pending & MISC_INT_TIMER2)
134 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
136 else if (pending & MISC_INT_TIMER3)
137 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
139 else if (pending & MISC_INT_TIMER4)
140 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
142 else if (pending & MISC_INT_DDR_PERF)
143 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
145 else if (pending & MISC_INT_ENET_LINK)
146 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
149 spurious_interrupt();
152 static void ar71xx_misc_irq_unmask(struct irq_data *d)
154 unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
155 void __iomem *base = ar71xx_reset_base;
158 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
159 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
162 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
165 static void ar71xx_misc_irq_mask(struct irq_data *d)
167 unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
168 void __iomem *base = ar71xx_reset_base;
171 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
172 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
175 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
178 static void ar724x_misc_irq_ack(struct irq_data *d)
180 unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
181 void __iomem *base = ar71xx_reset_base;
184 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
185 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
188 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
191 static struct irq_chip ar71xx_misc_irq_chip = {
192 .name = "AR71XX MISC",
193 .irq_unmask = ar71xx_misc_irq_unmask,
194 .irq_mask = ar71xx_misc_irq_mask,
197 static struct irqaction ar71xx_misc_irqaction = {
198 .handler = no_action,
199 .name = "cascade [AR71XX MISC]",
202 static void __init ar71xx_misc_irq_init(void)
204 void __iomem *base = ar71xx_reset_base;
207 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
208 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
210 switch (ar71xx_soc) {
211 case AR71XX_SOC_AR7240:
212 case AR71XX_SOC_AR7241:
213 case AR71XX_SOC_AR7242:
214 case AR71XX_SOC_AR9330:
215 case AR71XX_SOC_AR9331:
216 case AR71XX_SOC_AR9341:
217 case AR71XX_SOC_AR9342:
218 case AR71XX_SOC_AR9344:
219 ar71xx_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
222 ar71xx_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
226 for (i = AR71XX_MISC_IRQ_BASE;
227 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
228 irq_set_chip_and_handler(i, &ar71xx_misc_irq_chip,
231 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
234 static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
238 disable_irq_nosync(irq);
240 status = ar71xx_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
242 if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
243 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
244 generic_handle_irq(AR934X_IP2_IRQ_PCIE);
245 } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
246 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
247 generic_handle_irq(AR934X_IP2_IRQ_WMAC);
249 spurious_interrupt();
255 static void ar934x_ip2_irq_init(void)
259 for (i = AR934X_IP2_IRQ_BASE;
260 i < AR934X_IP2_IRQ_BASE + AR934X_IP2_IRQ_COUNT; i++)
261 irq_set_chip_and_handler(i, &dummy_irq_chip,
264 irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
269 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
270 * these devices typically allocate coherent DMA memory, however the
271 * DMA controller may still have some unsynchronized data in the FIFO.
272 * Issue a flush in the handlers to ensure that the driver sees
275 static void ar71xx_ip2_handler(void)
277 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI);
278 do_IRQ(AR71XX_CPU_IRQ_IP2);
281 static void ar724x_ip2_handler(void)
283 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
284 do_IRQ(AR71XX_CPU_IRQ_IP2);
287 static void ar913x_ip2_handler(void)
289 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
290 do_IRQ(AR71XX_CPU_IRQ_IP2);
293 static void ar933x_ip2_handler(void)
295 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
296 do_IRQ(AR71XX_CPU_IRQ_IP2);
299 static void ar934x_ip2_handler(void)
301 do_IRQ(AR71XX_CPU_IRQ_IP2);
304 static void ar71xx_ip3_handler(void)
306 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB);
307 do_IRQ(AR71XX_CPU_IRQ_USB);
310 static void ar724x_ip3_handler(void)
312 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
313 do_IRQ(AR71XX_CPU_IRQ_USB);
316 static void ar913x_ip3_handler(void)
318 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
319 do_IRQ(AR71XX_CPU_IRQ_USB);
322 static void ar933x_ip3_handler(void)
324 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
325 do_IRQ(AR71XX_CPU_IRQ_USB);
328 static void ar934x_ip3_handler(void)
330 do_IRQ(AR71XX_CPU_IRQ_USB);
333 static void (*ip2_handler)(void);
334 static void (*ip3_handler)(void);
336 asmlinkage void plat_irq_dispatch(void)
338 unsigned long pending;
340 pending = read_c0_status() & read_c0_cause() & ST0_IM;
342 if (pending & STATUSF_IP7)
343 do_IRQ(AR71XX_CPU_IRQ_TIMER);
345 else if (pending & STATUSF_IP2)
348 else if (pending & STATUSF_IP4)
349 do_IRQ(AR71XX_CPU_IRQ_GE0);
351 else if (pending & STATUSF_IP5)
352 do_IRQ(AR71XX_CPU_IRQ_GE1);
354 else if (pending & STATUSF_IP3)
357 else if (pending & STATUSF_IP6)
358 ar71xx_misc_irq_dispatch();
361 spurious_interrupt();
364 void __init arch_init_irq(void)
366 switch (ar71xx_soc) {
367 case AR71XX_SOC_AR7130:
368 case AR71XX_SOC_AR7141:
369 case AR71XX_SOC_AR7161:
370 ip2_handler = ar71xx_ip2_handler;
371 ip3_handler = ar71xx_ip3_handler;
374 case AR71XX_SOC_AR7240:
375 case AR71XX_SOC_AR7241:
376 case AR71XX_SOC_AR7242:
377 ip2_handler = ar724x_ip2_handler;
378 ip3_handler = ar724x_ip3_handler;
381 case AR71XX_SOC_AR9130:
382 case AR71XX_SOC_AR9132:
383 ip2_handler = ar913x_ip2_handler;
384 ip3_handler = ar913x_ip3_handler;
387 case AR71XX_SOC_AR9330:
388 case AR71XX_SOC_AR9331:
389 ip2_handler = ar933x_ip2_handler;
390 ip3_handler = ar933x_ip3_handler;
393 case AR71XX_SOC_AR9341:
394 case AR71XX_SOC_AR9342:
395 case AR71XX_SOC_AR9344:
396 ip2_handler = ar934x_ip2_handler;
397 ip3_handler = ar934x_ip3_handler;
406 ar71xx_misc_irq_init();
408 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
409 ar71xx_soc == AR71XX_SOC_AR9342 ||
410 ar71xx_soc == AR71XX_SOC_AR9344)
411 ar934x_ip2_irq_init();
413 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
415 ar71xx_gpio_irq_init();