2 * Atheros AR71xx SoC GPIO API support
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/spinlock.h>
18 #include <linux/ioport.h>
19 #include <linux/gpio.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
23 static DEFINE_SPINLOCK(ar71xx_gpio_lock);
25 void __ar71xx_gpio_set_value(unsigned gpio, int value)
29 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
32 ar71xx_gpio_wr(GPIO_REG_SET, (1 << gpio));
34 ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << gpio));
36 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
38 EXPORT_SYMBOL(__ar71xx_gpio_set_value);
40 int __ar71xx_gpio_get_value(unsigned gpio)
42 return (ar71xx_gpio_rr(GPIO_REG_IN) & (1 << gpio)) ? 1 : 0;
44 EXPORT_SYMBOL(__ar71xx_gpio_get_value);
46 static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
48 return __ar71xx_gpio_get_value(offset);
51 static void ar71xx_gpio_set_value(struct gpio_chip *chip,
52 unsigned offset, int value)
54 __ar71xx_gpio_set_value(offset, value);
57 static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
62 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
64 ar71xx_gpio_wr(GPIO_REG_OE,
65 ar71xx_gpio_rr(GPIO_REG_OE) & ~(1 << offset));
67 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
72 static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int value)
77 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
80 ar71xx_gpio_wr(GPIO_REG_SET, (1 << offset));
82 ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << offset));
84 ar71xx_gpio_wr(GPIO_REG_OE,
85 ar71xx_gpio_rr(GPIO_REG_OE) | (1 << offset));
87 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
92 static struct gpio_chip ar71xx_gpio_chip = {
94 .get = ar71xx_gpio_get_value,
95 .set = ar71xx_gpio_set_value,
96 .direction_input = ar71xx_gpio_direction_input,
97 .direction_output = ar71xx_gpio_direction_output,
99 .ngpio = AR71XX_GPIO_COUNT,
102 void ar71xx_gpio_function_enable(u32 mask)
106 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
108 ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) | mask);
110 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
113 void ar71xx_gpio_function_disable(u32 mask)
117 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
119 ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) & ~mask);
121 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
124 void __init ar71xx_gpio_init(void)
128 if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
129 "AR71xx GPIO controller"))
130 panic("cannot allocate AR71xx GPIO registers page");
132 err = gpiochip_add(&ar71xx_gpio_chip);
134 panic("cannot add AR71xx GPIO chip, error=%d", err);