2 * Atheros AR7XXX/AR9XXX SoC GPIO API support
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/spinlock.h>
18 #include <linux/ioport.h>
19 #include <linux/gpio.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
23 static DEFINE_SPINLOCK(ar71xx_gpio_lock);
25 unsigned long ar71xx_gpio_count;
26 EXPORT_SYMBOL(ar71xx_gpio_count);
28 void __ar71xx_gpio_set_value(unsigned gpio, int value)
30 void __iomem *base = ar71xx_gpio_base;
33 __raw_writel(1 << gpio, base + GPIO_REG_SET);
35 __raw_writel(1 << gpio, base + GPIO_REG_CLEAR);
37 EXPORT_SYMBOL(__ar71xx_gpio_set_value);
39 int __ar71xx_gpio_get_value(unsigned gpio)
41 return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1;
43 EXPORT_SYMBOL(__ar71xx_gpio_get_value);
45 static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
47 return __ar71xx_gpio_get_value(offset);
50 static void ar71xx_gpio_set_value(struct gpio_chip *chip,
51 unsigned offset, int value)
53 __ar71xx_gpio_set_value(offset, value);
56 static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
59 void __iomem *base = ar71xx_gpio_base;
62 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
64 __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
67 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
72 static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int value)
75 void __iomem *base = ar71xx_gpio_base;
78 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
81 __raw_writel(1 << offset, base + GPIO_REG_SET);
83 __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
85 __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
88 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
93 static int ar934x_gpio_direction_input(struct gpio_chip *chip,
96 void __iomem *base = ar71xx_gpio_base;
99 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
101 __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
104 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
109 static int ar934x_gpio_direction_output(struct gpio_chip *chip,
110 unsigned offset, int value)
112 void __iomem *base = ar71xx_gpio_base;
115 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
118 __raw_writel(1 << offset, base + GPIO_REG_SET);
120 __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
122 __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
125 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
130 static struct gpio_chip ar71xx_gpio_chip = {
132 .get = ar71xx_gpio_get_value,
133 .set = ar71xx_gpio_set_value,
134 .direction_input = ar71xx_gpio_direction_input,
135 .direction_output = ar71xx_gpio_direction_output,
137 .ngpio = AR71XX_GPIO_COUNT,
140 void ar71xx_gpio_function_enable(u32 mask)
142 void __iomem *base = ar71xx_gpio_base;
145 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
147 __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask,
148 base + GPIO_REG_FUNC);
150 (void) __raw_readl(base + GPIO_REG_FUNC);
152 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
155 void ar71xx_gpio_function_disable(u32 mask)
157 void __iomem *base = ar71xx_gpio_base;
160 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
162 __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask,
163 base + GPIO_REG_FUNC);
165 (void) __raw_readl(base + GPIO_REG_FUNC);
167 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
170 void ar71xx_gpio_function_setup(u32 set, u32 clear)
172 void __iomem *base = ar71xx_gpio_base;
175 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
177 __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set,
178 base + GPIO_REG_FUNC);
180 (void) __raw_readl(base + GPIO_REG_FUNC);
182 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
184 EXPORT_SYMBOL(ar71xx_gpio_function_setup);
186 void __init ar71xx_gpio_init(void)
190 if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
191 "AR71xx GPIO controller"))
192 panic("cannot allocate AR71xx GPIO registers page");
194 switch (ar71xx_soc) {
195 case AR71XX_SOC_AR7130:
196 case AR71XX_SOC_AR7141:
197 case AR71XX_SOC_AR7161:
198 ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
201 case AR71XX_SOC_AR7240:
202 case AR71XX_SOC_AR7241:
203 case AR71XX_SOC_AR7242:
204 ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
207 case AR71XX_SOC_AR9130:
208 case AR71XX_SOC_AR9132:
209 ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
212 case AR71XX_SOC_AR9330:
213 case AR71XX_SOC_AR9331:
214 ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT;
217 case AR71XX_SOC_AR9341:
218 case AR71XX_SOC_AR9342:
219 case AR71XX_SOC_AR9344:
220 ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT;
221 ar71xx_gpio_chip.direction_input = ar934x_gpio_direction_input;
222 ar71xx_gpio_chip.direction_output = ar934x_gpio_direction_output;
229 err = gpiochip_add(&ar71xx_gpio_chip);
231 panic("cannot add AR71xx GPIO chip, error=%d", err);