2 * Atheros AR71xx SoC GPIO API support
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/spinlock.h>
18 #include <linux/ioport.h>
19 #include <linux/gpio.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
23 static DEFINE_SPINLOCK(ar71xx_gpio_lock);
25 unsigned long ar71xx_gpio_count;
26 EXPORT_SYMBOL(ar71xx_gpio_count);
28 void __ar71xx_gpio_set_value(unsigned gpio, int value)
30 void __iomem *base = ar71xx_gpio_base;
33 __raw_writel(1 << gpio, base + GPIO_REG_SET);
35 __raw_writel(1 << gpio, base + GPIO_REG_CLEAR);
37 EXPORT_SYMBOL(__ar71xx_gpio_set_value);
39 int __ar71xx_gpio_get_value(unsigned gpio)
41 return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1;
43 EXPORT_SYMBOL(__ar71xx_gpio_get_value);
45 static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
47 return __ar71xx_gpio_get_value(offset);
50 static void ar71xx_gpio_set_value(struct gpio_chip *chip,
51 unsigned offset, int value)
53 __ar71xx_gpio_set_value(offset, value);
56 static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
59 void __iomem *base = ar71xx_gpio_base;
62 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
64 __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
67 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
72 static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int value)
75 void __iomem *base = ar71xx_gpio_base;
78 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
81 __raw_writel(1 << offset, base + GPIO_REG_SET);
83 __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
85 __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
88 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
93 static struct gpio_chip ar71xx_gpio_chip = {
95 .get = ar71xx_gpio_get_value,
96 .set = ar71xx_gpio_set_value,
97 .direction_input = ar71xx_gpio_direction_input,
98 .direction_output = ar71xx_gpio_direction_output,
100 .ngpio = AR71XX_GPIO_COUNT,
103 void ar71xx_gpio_function_enable(u32 mask)
105 void __iomem *base = ar71xx_gpio_base;
108 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
110 __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask,
111 base + GPIO_REG_FUNC);
113 (void) __raw_readl(base + GPIO_REG_FUNC);
115 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
118 void ar71xx_gpio_function_disable(u32 mask)
120 void __iomem *base = ar71xx_gpio_base;
123 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
125 __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask,
126 base + GPIO_REG_FUNC);
128 (void) __raw_readl(base + GPIO_REG_FUNC);
130 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
133 void ar71xx_gpio_function_setup(u32 set, u32 clear)
135 void __iomem *base = ar71xx_gpio_base;
138 spin_lock_irqsave(&ar71xx_gpio_lock, flags);
140 __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set,
141 base + GPIO_REG_FUNC);
143 (void) __raw_readl(base + GPIO_REG_FUNC);
145 spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
147 EXPORT_SYMBOL(ar71xx_gpio_function_setup);
149 void __init ar71xx_gpio_init(void)
153 if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
154 "AR71xx GPIO controller"))
155 panic("cannot allocate AR71xx GPIO registers page");
157 switch (ar71xx_soc) {
158 case AR71XX_SOC_AR7130:
159 case AR71XX_SOC_AR7141:
160 case AR71XX_SOC_AR7161:
161 ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
164 case AR71XX_SOC_AR7240:
165 ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
168 case AR71XX_SOC_AR9130:
169 case AR71XX_SOC_AR9132:
170 ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
177 err = gpiochip_add(&ar71xx_gpio_chip);
179 panic("cannot add AR71xx GPIO chip, error=%d", err);