target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_8250.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22
  23 #include "devices.h"
  24
  25 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
  26
  27 static struct resource ar71xx_uart_resources[] = {
  28         {
  29                 .start  = AR71XX_UART_BASE,
  30                 .end    = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
  31                 .flags  = IORESOURCE_MEM,
  32         },
  33 };
  34
  35 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
  36 static struct plat_serial8250_port ar71xx_uart_data[] = {
  37         {
  38                 .mapbase        = AR71XX_UART_BASE,
  39                 .irq            = AR71XX_MISC_IRQ_UART,
  40                 .flags          = AR71XX_UART_FLAGS,
  41                 .iotype         = UPIO_MEM32,
  42                 .regshift       = 2,
  43         }, {
  44                 /* terminating entry */
  45         }
  46 };
  47
  48 static struct platform_device ar71xx_uart_device = {
  49         .name           = "serial8250",
  50         .id             = PLAT8250_DEV_PLATFORM,
  51         .resource       = ar71xx_uart_resources,
  52         .num_resources  = ARRAY_SIZE(ar71xx_uart_resources),
  53         .dev = {
  54                 .platform_data  = ar71xx_uart_data
  55         },
  56 };
  57
  58 void __init ar71xx_add_device_uart(void)
  59 {
  60         ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
  61         platform_device_register(&ar71xx_uart_device);
  62 }
  63
  64 static struct resource ar71xx_mdio_resources[] = {
  65         {
  66                 .name   = "mdio_base",
  67                 .flags  = IORESOURCE_MEM,
  68                 .start  = AR71XX_GE0_BASE,
  69                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
  70         }
  71 };
  72
  73 static struct ag71xx_mdio_platform_data ar71xx_mdio_data;
  74
  75 struct platform_device ar71xx_mdio_device = {
  76         .name           = "ag71xx-mdio",
  77         .id             = -1,
  78         .resource       = ar71xx_mdio_resources,
  79         .num_resources  = ARRAY_SIZE(ar71xx_mdio_resources),
  80         .dev = {
  81                 .platform_data = &ar71xx_mdio_data,
  82         },
  83 };
  84
  85 void __init ar71xx_add_device_mdio(u32 phy_mask)
  86 {
  87         switch (ar71xx_soc) {
  88         case AR71XX_SOC_AR7240:
  89                 ar71xx_mdio_data.is_ar7240 = 1;
  90                 break;
  91         case AR71XX_SOC_AR7241:
  92                 ar71xx_mdio_data.is_ar7240 = 1;
  93                 ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
  94                 ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
  95                 break;
  96         case AR71XX_SOC_AR7242:
  97                 ar71xx_mdio_data.is_ar7240 = 1;
  98                 break;
  99         default:
 100                 break;
 101         }
 102
 103         ar71xx_mdio_data.phy_mask = phy_mask;
 104
 105         platform_device_register(&ar71xx_mdio_device);
 106 }
 107
 108 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
 109 {
 110         void __iomem *base;
 111         u32 t;
 112
 113         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 114
 115         t = __raw_readl(base + cfg_reg);
 116         t &= ~(3 << shift);
 117         t |=  (2 << shift);
 118         __raw_writel(t, base + cfg_reg);
 119         udelay(100);
 120
 121         __raw_writel(pll_val, base + pll_reg);
 122
 123         t |= (3 << shift);
 124         __raw_writel(t, base + cfg_reg);
 125         udelay(100);
 126
 127         t &= ~(3 << shift);
 128         __raw_writel(t, base + cfg_reg);
 129         udelay(100);
 130
 131         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 132                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 133
 134         iounmap(base);
 135 }
 136
 137 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
 138 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
 139
 140 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
 141 {
 142         struct ar71xx_eth_pll_data *pll_data;
 143         u32 pll_val;
 144
 145         switch (mac) {
 146         case 0:
 147                 pll_data = &ar71xx_eth0_pll_data;
 148                 break;
 149         case 1:
 150                 pll_data = &ar71xx_eth1_pll_data;
 151                 break;
 152         default:
 153                 BUG();
 154         }
 155
 156         switch (speed) {
 157         case SPEED_10:
 158                 pll_val = pll_data->pll_10;
 159                 break;
 160         case SPEED_100:
 161                 pll_val = pll_data->pll_100;
 162                 break;
 163         case SPEED_1000:
 164                 pll_val = pll_data->pll_1000;
 165                 break;
 166         default:
 167                 BUG();
 168         }
 169
 170         return pll_val;
 171 }
 172
 173 static void ar71xx_set_pll_ge0(int speed)
 174 {
 175         u32 val = ar71xx_get_eth_pll(0, speed);
 176
 177         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 178                         val, AR71XX_ETH0_PLL_SHIFT);
 179 }
 180
 181 static void ar71xx_set_pll_ge1(int speed)
 182 {
 183         u32 val = ar71xx_get_eth_pll(1, speed);
 184
 185         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 186                          val, AR71XX_ETH1_PLL_SHIFT);
 187 }
 188
 189 static void ar724x_set_pll_ge0(int speed)
 190 {
 191         /* TODO */
 192 }
 193
 194 static void ar724x_set_pll_ge1(int speed)
 195 {
 196         /* TODO */
 197 }
 198
 199 static void ar91xx_set_pll_ge0(int speed)
 200 {
 201         u32 val = ar71xx_get_eth_pll(0, speed);
 202
 203         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
 204                          val, AR91XX_ETH0_PLL_SHIFT);
 205 }
 206
 207 static void ar91xx_set_pll_ge1(int speed)
 208 {
 209         u32 val = ar71xx_get_eth_pll(1, speed);
 210
 211         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
 212                          val, AR91XX_ETH1_PLL_SHIFT);
 213 }
 214
 215 static void ar71xx_ddr_flush_ge0(void)
 216 {
 217         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
 218 }
 219
 220 static void ar71xx_ddr_flush_ge1(void)
 221 {
 222         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
 223 }
 224
 225 static void ar724x_ddr_flush_ge0(void)
 226 {
 227         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 228 }
 229
 230 static void ar724x_ddr_flush_ge1(void)
 231 {
 232         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 233 }
 234
 235 static void ar91xx_ddr_flush_ge0(void)
 236 {
 237         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 238 }
 239
 240 static void ar91xx_ddr_flush_ge1(void)
 241 {
 242         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 243 }
 244
 245 static struct resource ar71xx_eth0_resources[] = {
 246         {
 247                 .name   = "mac_base",
 248                 .flags  = IORESOURCE_MEM,
 249                 .start  = AR71XX_GE0_BASE,
 250                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 251         }, {
 252                 .name   = "mii_ctrl",
 253                 .flags  = IORESOURCE_MEM,
 254                 .start  = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
 255                 .end    = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
 256         }, {
 257                 .name   = "mac_irq",
 258                 .flags  = IORESOURCE_IRQ,
 259                 .start  = AR71XX_CPU_IRQ_GE0,
 260                 .end    = AR71XX_CPU_IRQ_GE0,
 261         },
 262 };
 263
 264 struct ag71xx_platform_data ar71xx_eth0_data = {
 265         .reset_bit      = RESET_MODULE_GE0_MAC,
 266 };
 267
 268 struct platform_device ar71xx_eth0_device = {
 269         .name           = "ag71xx",
 270         .id             = 0,
 271         .resource       = ar71xx_eth0_resources,
 272         .num_resources  = ARRAY_SIZE(ar71xx_eth0_resources),
 273         .dev = {
 274                 .platform_data = &ar71xx_eth0_data,
 275         },
 276 };
 277
 278 static struct resource ar71xx_eth1_resources[] = {
 279         {
 280                 .name   = "mac_base",
 281                 .flags  = IORESOURCE_MEM,
 282                 .start  = AR71XX_GE1_BASE,
 283                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 284         }, {
 285                 .name   = "mii_ctrl",
 286                 .flags  = IORESOURCE_MEM,
 287                 .start  = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
 288                 .end    = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
 289         }, {
 290                 .name   = "mac_irq",
 291                 .flags  = IORESOURCE_IRQ,
 292                 .start  = AR71XX_CPU_IRQ_GE1,
 293                 .end    = AR71XX_CPU_IRQ_GE1,
 294         },
 295 };
 296
 297 struct ag71xx_platform_data ar71xx_eth1_data = {
 298         .reset_bit      = RESET_MODULE_GE1_MAC,
 299 };
 300
 301 struct platform_device ar71xx_eth1_device = {
 302         .name           = "ag71xx",
 303         .id             = 1,
 304         .resource       = ar71xx_eth1_resources,
 305         .num_resources  = ARRAY_SIZE(ar71xx_eth1_resources),
 306         .dev = {
 307                 .platform_data = &ar71xx_eth1_data,
 308         },
 309 };
 310
 311 #define AR71XX_PLL_VAL_1000     0x00110000
 312 #define AR71XX_PLL_VAL_100      0x00001099
 313 #define AR71XX_PLL_VAL_10       0x00991099
 314
 315 #define AR724X_PLL_VAL_1000     0x00110000
 316 #define AR724X_PLL_VAL_100      0x00001099
 317 #define AR724X_PLL_VAL_10       0x00991099
 318
 319 #define AR91XX_PLL_VAL_1000     0x1a000000
 320 #define AR91XX_PLL_VAL_100      0x13000a44
 321 #define AR91XX_PLL_VAL_10       0x00441099
 322
 323 static void __init ar71xx_init_eth_pll_data(unsigned int id)
 324 {
 325         struct ar71xx_eth_pll_data *pll_data;
 326         u32 pll_10, pll_100, pll_1000;
 327
 328         switch (id) {
 329         case 0:
 330                 pll_data = &ar71xx_eth0_pll_data;
 331                 break;
 332         case 1:
 333                 pll_data = &ar71xx_eth1_pll_data;
 334                 break;
 335         default:
 336                 BUG();
 337         }
 338
 339         switch (ar71xx_soc) {
 340         case AR71XX_SOC_AR7130:
 341         case AR71XX_SOC_AR7141:
 342         case AR71XX_SOC_AR7161:
 343                 pll_10 = AR71XX_PLL_VAL_10;
 344                 pll_100 = AR71XX_PLL_VAL_100;
 345                 pll_1000 = AR71XX_PLL_VAL_1000;
 346                 break;
 347
 348         case AR71XX_SOC_AR7240:
 349         case AR71XX_SOC_AR7241:
 350         case AR71XX_SOC_AR7242:
 351                 pll_10 = AR724X_PLL_VAL_10;
 352                 pll_100 = AR724X_PLL_VAL_100;
 353                 pll_1000 = AR724X_PLL_VAL_1000;
 354                 break;
 355
 356         case AR71XX_SOC_AR9130:
 357         case AR71XX_SOC_AR9132:
 358                 pll_10 = AR91XX_PLL_VAL_10;
 359                 pll_100 = AR91XX_PLL_VAL_100;
 360                 pll_1000 = AR91XX_PLL_VAL_1000;
 361                 break;
 362         default:
 363                 BUG();
 364         }
 365
 366         if (!pll_data->pll_10)
 367                 pll_data->pll_10 = pll_10;
 368
 369         if (!pll_data->pll_100)
 370                 pll_data->pll_100 = pll_100;
 371
 372         if (!pll_data->pll_1000)
 373                 pll_data->pll_1000 = pll_1000;
 374 }
 375
 376 static int ar71xx_eth_instance __initdata;
 377 void __init ar71xx_add_device_eth(unsigned int id)
 378 {
 379         struct platform_device *pdev;
 380         struct ag71xx_platform_data *pdata;
 381
 382         ar71xx_init_eth_pll_data(id);
 383
 384         switch (id) {
 385         case 0:
 386                 switch (ar71xx_eth0_data.phy_if_mode) {
 387                 case PHY_INTERFACE_MODE_MII:
 388                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
 389                         break;
 390                 case PHY_INTERFACE_MODE_GMII:
 391                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
 392                         break;
 393                 case PHY_INTERFACE_MODE_RGMII:
 394                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
 395                         break;
 396                 case PHY_INTERFACE_MODE_RMII:
 397                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
 398                         break;
 399                 default:
 400                         printk(KERN_ERR "ar71xx: invalid PHY interface mode "
 401                                         "for eth0\n");
 402                         return;
 403                 }
 404                 pdev = &ar71xx_eth0_device;
 405                 break;
 406         case 1:
 407                 switch (ar71xx_eth1_data.phy_if_mode) {
 408                 case PHY_INTERFACE_MODE_RMII:
 409                         ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
 410                         break;
 411                 case PHY_INTERFACE_MODE_RGMII:
 412                         ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
 413                         break;
 414                 default:
 415                         printk(KERN_ERR "ar71xx: invalid PHY interface mode "
 416                                         "for eth1\n");
 417                         return;
 418                 }
 419                 pdev = &ar71xx_eth1_device;
 420                 break;
 421         default:
 422                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 423                 return;
 424         }
 425
 426         pdata = pdev->dev.platform_data;
 427
 428         switch (ar71xx_soc) {
 429         case AR71XX_SOC_AR7130:
 430                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 431                                       : ar71xx_ddr_flush_ge0;
 432                 pdata->set_pll =  id ? ar71xx_set_pll_ge1
 433                                      : ar71xx_set_pll_ge0;
 434                 break;
 435
 436         case AR71XX_SOC_AR7141:
 437         case AR71XX_SOC_AR7161:
 438                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 439                                       : ar71xx_ddr_flush_ge0;
 440                 pdata->set_pll =  id ? ar71xx_set_pll_ge1
 441                                      : ar71xx_set_pll_ge0;
 442                 pdata->has_gbit = 1;
 443                 break;
 444
 445         case AR71XX_SOC_AR7241:
 446         case AR71XX_SOC_AR7242:
 447                 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
 448                 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
 449                 /* fall through */
 450         case AR71XX_SOC_AR7240:
 451                 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
 452                                       : ar724x_ddr_flush_ge0;
 453                 pdata->set_pll =  id ? ar724x_set_pll_ge1
 454                                      : ar724x_set_pll_ge0;
 455                 pdata->is_ar724x = 1;
 456
 457                 if (!pdata->fifo_cfg1)
 458                         pdata->fifo_cfg1 = 0x0010ffff;
 459                 if (!pdata->fifo_cfg2)
 460                         pdata->fifo_cfg2 = 0x015500aa;
 461                 if (!pdata->fifo_cfg3)
 462                         pdata->fifo_cfg3 = 0x01f00140;
 463                 break;
 464
 465         case AR71XX_SOC_AR9130:
 466                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 467                                       : ar91xx_ddr_flush_ge0;
 468                 pdata->set_pll =  id ? ar91xx_set_pll_ge1
 469                                      : ar91xx_set_pll_ge0;
 470                 pdata->is_ar91xx = 1;
 471                 break;
 472
 473         case AR71XX_SOC_AR9132:
 474                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 475                                       : ar91xx_ddr_flush_ge0;
 476                 pdata->set_pll =  id ? ar91xx_set_pll_ge1
 477                                       : ar91xx_set_pll_ge0;
 478                 pdata->is_ar91xx = 1;
 479                 pdata->has_gbit = 1;
 480                 break;
 481
 482         default:
 483                 BUG();
 484         }
 485
 486         switch (pdata->phy_if_mode) {
 487         case PHY_INTERFACE_MODE_GMII:
 488         case PHY_INTERFACE_MODE_RGMII:
 489                 if (!pdata->has_gbit) {
 490                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
 491                                         id);
 492                         return;
 493                 }
 494                 /* fallthrough */
 495         default:
 496                 break;
 497         }
 498
 499         if (!is_valid_ether_addr(pdata->mac_addr)) {
 500                 random_ether_addr(pdata->mac_addr);
 501                 printk(KERN_DEBUG
 502                         "ar71xx: using random MAC address for eth%d\n",
 503                         ar71xx_eth_instance);
 504         }
 505
 506         if (pdata->mii_bus_dev == NULL)
 507                 pdata->mii_bus_dev = &ar71xx_mdio_device.dev;
 508
 509         /* Reset the device */
 510         ar71xx_device_stop(pdata->reset_bit);
 511         mdelay(100);
 512
 513         ar71xx_device_start(pdata->reset_bit);
 514         mdelay(100);
 515
 516         platform_device_register(pdev);
 517         ar71xx_eth_instance++;
 518 }
 519
 520 static struct resource ar71xx_spi_resources[] = {
 521         [0] = {
 522                 .start  = AR71XX_SPI_BASE,
 523                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 524                 .flags  = IORESOURCE_MEM,
 525         },
 526 };
 527
 528 static struct platform_device ar71xx_spi_device = {
 529         .name           = "ar71xx-spi",
 530         .id             = -1,
 531         .resource       = ar71xx_spi_resources,
 532         .num_resources  = ARRAY_SIZE(ar71xx_spi_resources),
 533 };
 534
 535 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
 536                                 struct spi_board_info const *info,
 537                                 unsigned n)
 538 {
 539         spi_register_board_info(info, n);
 540         ar71xx_spi_device.dev.platform_data = pdata;
 541         platform_device_register(&ar71xx_spi_device);
 542 }
 543
 544 void __init ar71xx_add_device_wdt(void)
 545 {
 546         platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
 547 }
 548
 549 void __init ar71xx_set_mac_base(unsigned char *mac)
 550 {
 551         memcpy(ar71xx_mac_base, mac, ETH_ALEN);
 552 }
 553
 554 void __init ar71xx_parse_mac_addr(char *mac_str)
 555 {
 556         u8 tmp[ETH_ALEN];
 557         int t;
 558
 559         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 560                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 561
 562         if (t != ETH_ALEN)
 563                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
 564                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 565
 566         if (t == ETH_ALEN)
 567                 ar71xx_set_mac_base(tmp);
 568         else
 569                 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
 570                                 "\"%s\"\n", mac_str);
 571 }
 572
 573 static int __init ar71xx_ethaddr_setup(char *str)
 574 {
 575         ar71xx_parse_mac_addr(str);
 576         return 1;
 577 }
 578 __setup("ethaddr=", ar71xx_ethaddr_setup);
 579
 580 static int __init ar71xx_kmac_setup(char *str)
 581 {
 582         ar71xx_parse_mac_addr(str);
 583         return 1;
 584 }
 585 __setup("kmac=", ar71xx_kmac_setup);
 586
 587 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
 588                             unsigned offset)
 589 {
 590         u32 t;
 591
 592         if (!is_valid_ether_addr(src)) {
 593                 memset(dst, '\0', ETH_ALEN);
 594                 return;
 595         }
 596
 597         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
 598         t += offset;
 599
 600         dst[0] = src[0];
 601         dst[1] = src[1];
 602         dst[2] = src[2];
 603         dst[3] = (t >> 16) & 0xff;
 604         dst[4] = (t >> 8) & 0xff;
 605         dst[5] = t & 0xff;
 606 }