target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
  25
  26 #include "devices.h"
  27
  28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
  29
  30 static struct resource ar71xx_uart_resources[] = {
  31         {
  32                 .start  = AR71XX_UART_BASE,
  33                 .end    = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
  34                 .flags  = IORESOURCE_MEM,
  35         },
  36 };
  37
  38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
  39 static struct plat_serial8250_port ar71xx_uart_data[] = {
  40         {
  41                 .mapbase        = AR71XX_UART_BASE,
  42                 .irq            = AR71XX_MISC_IRQ_UART,
  43                 .flags          = AR71XX_UART_FLAGS,
  44                 .iotype         = UPIO_MEM32,
  45                 .regshift       = 2,
  46         }, {
  47                 /* terminating entry */
  48         }
  49 };
  50
  51 static struct platform_device ar71xx_uart_device = {
  52         .name           = "serial8250",
  53         .id             = PLAT8250_DEV_PLATFORM,
  54         .resource       = ar71xx_uart_resources,
  55         .num_resources  = ARRAY_SIZE(ar71xx_uart_resources),
  56         .dev = {
  57                 .platform_data  = ar71xx_uart_data
  58         },
  59 };
  60
  61 static struct resource ar933x_uart_resources[] = {
  62         {
  63                 .start  = AR933X_UART_BASE,
  64                 .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         {
  68                 .start  = AR71XX_MISC_IRQ_UART,
  69                 .end    = AR71XX_MISC_IRQ_UART,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 static struct ar933x_uart_platform_data ar933x_uart_data;
  75 static struct platform_device ar933x_uart_device = {
  76         .name           = "ar933x-uart",
  77         .id             = -1,
  78         .resource       = ar933x_uart_resources,
  79         .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
  80         .dev = {
  81                 .platform_data  = &ar933x_uart_data,
  82         },
  83 };
  84
  85 void __init ar71xx_add_device_uart(void)
  86 {
  87         struct platform_device *pdev;
  88
  89         switch (ar71xx_soc) {
  90         case AR71XX_SOC_AR7130:
  91         case AR71XX_SOC_AR7141:
  92         case AR71XX_SOC_AR7161:
  93         case AR71XX_SOC_AR7240:
  94         case AR71XX_SOC_AR7241:
  95         case AR71XX_SOC_AR7242:
  96         case AR71XX_SOC_AR9130:
  97         case AR71XX_SOC_AR9132:
  98                 pdev = &ar71xx_uart_device;
  99                 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
 100                 break;
 101
 102         case AR71XX_SOC_AR9330:
 103         case AR71XX_SOC_AR9331:
 104                 pdev = &ar933x_uart_device;
 105                 ar933x_uart_data.uartclk = ar71xx_ref_freq;
 106                 break;
 107
 108         case AR71XX_SOC_AR9341:
 109         case AR71XX_SOC_AR9342:
 110         case AR71XX_SOC_AR9344:
 111                 pdev = &ar71xx_uart_device;
 112                 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
 113                 break;
 114
 115         default:
 116                 BUG();
 117         }
 118
 119         platform_device_register(pdev);
 120 }
 121
 122 static struct resource ar71xx_mdio0_resources[] = {
 123         {
 124                 .name   = "mdio_base",
 125                 .flags  = IORESOURCE_MEM,
 126                 .start  = AR71XX_GE0_BASE,
 127                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 128         }
 129 };
 130
 131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
 132
 133 struct platform_device ar71xx_mdio0_device = {
 134         .name           = "ag71xx-mdio",
 135         .id             = 0,
 136         .resource       = ar71xx_mdio0_resources,
 137         .num_resources  = ARRAY_SIZE(ar71xx_mdio0_resources),
 138         .dev = {
 139                 .platform_data = &ar71xx_mdio0_data,
 140         },
 141 };
 142
 143 static struct resource ar71xx_mdio1_resources[] = {
 144         {
 145                 .name   = "mdio_base",
 146                 .flags  = IORESOURCE_MEM,
 147                 .start  = AR71XX_GE1_BASE,
 148                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 149         }
 150 };
 151
 152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
 153
 154 struct platform_device ar71xx_mdio1_device = {
 155         .name           = "ag71xx-mdio",
 156         .id             = 1,
 157         .resource       = ar71xx_mdio1_resources,
 158         .num_resources  = ARRAY_SIZE(ar71xx_mdio1_resources),
 159         .dev = {
 160                 .platform_data = &ar71xx_mdio1_data,
 161         },
 162 };
 163
 164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
 165 {
 166         void __iomem *base;
 167         u32 t;
 168
 169         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 170
 171         t = __raw_readl(base + cfg_reg);
 172         t &= ~(3 << shift);
 173         t |=  (2 << shift);
 174         __raw_writel(t, base + cfg_reg);
 175         udelay(100);
 176
 177         __raw_writel(pll_val, base + pll_reg);
 178
 179         t |= (3 << shift);
 180         __raw_writel(t, base + cfg_reg);
 181         udelay(100);
 182
 183         t &= ~(3 << shift);
 184         __raw_writel(t, base + cfg_reg);
 185         udelay(100);
 186
 187         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 188                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 189
 190         iounmap(base);
 191 }
 192
 193 static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
 194                                           unsigned int mii_if)
 195 {
 196         void __iomem *base;
 197         u32 t;
 198
 199         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 200
 201         t = __raw_readl(base + reg);
 202         t &= ~(MII_CTRL_IF_MASK);
 203         t |= (mii_if & MII_CTRL_IF_MASK);
 204         __raw_writel(t, base + reg);
 205
 206         iounmap(base);
 207 }
 208
 209 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 210 {
 211         struct platform_device *mdio_dev;
 212         struct ag71xx_mdio_platform_data *mdio_data;
 213         unsigned int max_id;
 214
 215         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 216             ar71xx_soc == AR71XX_SOC_AR9342 ||
 217             ar71xx_soc == AR71XX_SOC_AR9344)
 218                 max_id = 1;
 219         else
 220                 max_id = 0;
 221
 222         if (id > max_id) {
 223                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 224                 return;
 225         }
 226
 227         switch (ar71xx_soc) {
 228         case AR71XX_SOC_AR7241:
 229         case AR71XX_SOC_AR9330:
 230         case AR71XX_SOC_AR9331:
 231                 mdio_dev = &ar71xx_mdio1_device;
 232                 mdio_data = &ar71xx_mdio1_data;
 233                 break;
 234
 235         case AR71XX_SOC_AR9341:
 236         case AR71XX_SOC_AR9342:
 237         case AR71XX_SOC_AR9344:
 238                 if (id == 0) {
 239                         mdio_dev = &ar71xx_mdio0_device;
 240                         mdio_data = &ar71xx_mdio0_data;
 241                 } else {
 242                         mdio_dev = &ar71xx_mdio1_device;
 243                         mdio_data = &ar71xx_mdio1_data;
 244                 }
 245                 break;
 246
 247         case AR71XX_SOC_AR7242:
 248                 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 249                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 250                                AR71XX_ETH0_PLL_SHIFT);
 251                 /* fall through */
 252         default:
 253                 mdio_dev = &ar71xx_mdio0_device;
 254                 mdio_data = &ar71xx_mdio0_data;
 255                 break;
 256         }
 257
 258         mdio_data->phy_mask = phy_mask;
 259
 260         switch (ar71xx_soc) {
 261         case AR71XX_SOC_AR7240:
 262         case AR71XX_SOC_AR7241:
 263         case AR71XX_SOC_AR9330:
 264         case AR71XX_SOC_AR9331:
 265                 mdio_data->is_ar7240 = 1;
 266                 break;
 267
 268         case AR71XX_SOC_AR9341:
 269         case AR71XX_SOC_AR9342:
 270         case AR71XX_SOC_AR9344:
 271                 if (id == 1)
 272                         mdio_data->is_ar7240 = 1;
 273                 break;
 274
 275         default:
 276                 break;
 277         }
 278
 279         platform_device_register(mdio_dev);
 280 }
 281
 282 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
 283 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
 284
 285 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
 286 {
 287         struct ar71xx_eth_pll_data *pll_data;
 288         u32 pll_val;
 289
 290         switch (mac) {
 291         case 0:
 292                 pll_data = &ar71xx_eth0_pll_data;
 293                 break;
 294         case 1:
 295                 pll_data = &ar71xx_eth1_pll_data;
 296                 break;
 297         default:
 298                 BUG();
 299         }
 300
 301         switch (speed) {
 302         case SPEED_10:
 303                 pll_val = pll_data->pll_10;
 304                 break;
 305         case SPEED_100:
 306                 pll_val = pll_data->pll_100;
 307                 break;
 308         case SPEED_1000:
 309                 pll_val = pll_data->pll_1000;
 310                 break;
 311         default:
 312                 BUG();
 313         }
 314
 315         return pll_val;
 316 }
 317
 318 static void ar71xx_set_speed_ge0(int speed)
 319 {
 320         u32 val = ar71xx_get_eth_pll(0, speed);
 321
 322         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 323                         val, AR71XX_ETH0_PLL_SHIFT);
 324 }
 325
 326 static void ar71xx_set_speed_ge1(int speed)
 327 {
 328         u32 val = ar71xx_get_eth_pll(1, speed);
 329
 330         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 331                          val, AR71XX_ETH1_PLL_SHIFT);
 332 }
 333
 334 static void ar724x_set_speed_ge0(int speed)
 335 {
 336         /* TODO */
 337 }
 338
 339 static void ar724x_set_speed_ge1(int speed)
 340 {
 341         /* TODO */
 342 }
 343
 344 static void ar7242_set_speed_ge0(int speed)
 345 {
 346         u32 val = ar71xx_get_eth_pll(0, speed);
 347         void __iomem *base;
 348
 349         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 350         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 351         iounmap(base);
 352 }
 353
 354 static void ar91xx_set_speed_ge0(int speed)
 355 {
 356         u32 val = ar71xx_get_eth_pll(0, speed);
 357
 358         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
 359                          val, AR91XX_ETH0_PLL_SHIFT);
 360 }
 361
 362 static void ar91xx_set_speed_ge1(int speed)
 363 {
 364         u32 val = ar71xx_get_eth_pll(1, speed);
 365
 366         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
 367                          val, AR91XX_ETH1_PLL_SHIFT);
 368 }
 369
 370 static void ar933x_set_speed_ge0(int speed)
 371 {
 372         /* TODO */
 373 }
 374
 375 static void ar933x_set_speed_ge1(int speed)
 376 {
 377         /* TODO */
 378 }
 379
 380 static void ar934x_set_speed_ge0(int speed)
 381 {
 382         /* TODO */
 383 }
 384
 385 static void ar934x_set_speed_ge1(int speed)
 386 {
 387         /* TODO */
 388 }
 389
 390 static void ar71xx_ddr_flush_ge0(void)
 391 {
 392         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
 393 }
 394
 395 static void ar71xx_ddr_flush_ge1(void)
 396 {
 397         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
 398 }
 399
 400 static void ar724x_ddr_flush_ge0(void)
 401 {
 402         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 403 }
 404
 405 static void ar724x_ddr_flush_ge1(void)
 406 {
 407         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 408 }
 409
 410 static void ar91xx_ddr_flush_ge0(void)
 411 {
 412         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 413 }
 414
 415 static void ar91xx_ddr_flush_ge1(void)
 416 {
 417         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 418 }
 419
 420 static void ar933x_ddr_flush_ge0(void)
 421 {
 422         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
 423 }
 424
 425 static void ar933x_ddr_flush_ge1(void)
 426 {
 427         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
 428 }
 429
 430 static void ar934x_ddr_flush_ge0(void)
 431 {
 432         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
 433 }
 434
 435 static void ar934x_ddr_flush_ge1(void)
 436 {
 437         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
 438 }
 439
 440 static struct resource ar71xx_eth0_resources[] = {
 441         {
 442                 .name   = "mac_base",
 443                 .flags  = IORESOURCE_MEM,
 444                 .start  = AR71XX_GE0_BASE,
 445                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 446         }, {
 447                 .name   = "mii_ctrl",
 448                 .flags  = IORESOURCE_MEM,
 449                 .start  = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
 450                 .end    = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
 451         }, {
 452                 .name   = "mac_irq",
 453                 .flags  = IORESOURCE_IRQ,
 454                 .start  = AR71XX_CPU_IRQ_GE0,
 455                 .end    = AR71XX_CPU_IRQ_GE0,
 456         },
 457 };
 458
 459 struct ag71xx_platform_data ar71xx_eth0_data = {
 460         .reset_bit      = RESET_MODULE_GE0_MAC,
 461 };
 462
 463 struct platform_device ar71xx_eth0_device = {
 464         .name           = "ag71xx",
 465         .id             = 0,
 466         .resource       = ar71xx_eth0_resources,
 467         .num_resources  = ARRAY_SIZE(ar71xx_eth0_resources),
 468         .dev = {
 469                 .platform_data = &ar71xx_eth0_data,
 470         },
 471 };
 472
 473 static struct resource ar71xx_eth1_resources[] = {
 474         {
 475                 .name   = "mac_base",
 476                 .flags  = IORESOURCE_MEM,
 477                 .start  = AR71XX_GE1_BASE,
 478                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 479         }, {
 480                 .name   = "mii_ctrl",
 481                 .flags  = IORESOURCE_MEM,
 482                 .start  = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
 483                 .end    = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
 484         }, {
 485                 .name   = "mac_irq",
 486                 .flags  = IORESOURCE_IRQ,
 487                 .start  = AR71XX_CPU_IRQ_GE1,
 488                 .end    = AR71XX_CPU_IRQ_GE1,
 489         },
 490 };
 491
 492 struct ag71xx_platform_data ar71xx_eth1_data = {
 493         .reset_bit      = RESET_MODULE_GE1_MAC,
 494 };
 495
 496 struct platform_device ar71xx_eth1_device = {
 497         .name           = "ag71xx",
 498         .id             = 1,
 499         .resource       = ar71xx_eth1_resources,
 500         .num_resources  = ARRAY_SIZE(ar71xx_eth1_resources),
 501         .dev = {
 502                 .platform_data = &ar71xx_eth1_data,
 503         },
 504 };
 505
 506 #define AR71XX_PLL_VAL_1000     0x00110000
 507 #define AR71XX_PLL_VAL_100      0x00001099
 508 #define AR71XX_PLL_VAL_10       0x00991099
 509
 510 #define AR724X_PLL_VAL_1000     0x00110000
 511 #define AR724X_PLL_VAL_100      0x00001099
 512 #define AR724X_PLL_VAL_10       0x00991099
 513
 514 #define AR7242_PLL_VAL_1000     0x16000000
 515 #define AR7242_PLL_VAL_100      0x00000101
 516 #define AR7242_PLL_VAL_10       0x00001616
 517
 518 #define AR91XX_PLL_VAL_1000     0x1a000000
 519 #define AR91XX_PLL_VAL_100      0x13000a44
 520 #define AR91XX_PLL_VAL_10       0x00441099
 521
 522 #define AR933X_PLL_VAL_1000     0x00110000
 523 #define AR933X_PLL_VAL_100      0x00001099
 524 #define AR933X_PLL_VAL_10       0x00991099
 525
 526 #define AR934X_PLL_VAL_1000     0x00110000
 527 #define AR934X_PLL_VAL_100      0x00001099
 528 #define AR934X_PLL_VAL_10       0x00991099
 529
 530 static void __init ar71xx_init_eth_pll_data(unsigned int id)
 531 {
 532         struct ar71xx_eth_pll_data *pll_data;
 533         u32 pll_10, pll_100, pll_1000;
 534
 535         switch (id) {
 536         case 0:
 537                 pll_data = &ar71xx_eth0_pll_data;
 538                 break;
 539         case 1:
 540                 pll_data = &ar71xx_eth1_pll_data;
 541                 break;
 542         default:
 543                 BUG();
 544         }
 545
 546         switch (ar71xx_soc) {
 547         case AR71XX_SOC_AR7130:
 548         case AR71XX_SOC_AR7141:
 549         case AR71XX_SOC_AR7161:
 550                 pll_10 = AR71XX_PLL_VAL_10;
 551                 pll_100 = AR71XX_PLL_VAL_100;
 552                 pll_1000 = AR71XX_PLL_VAL_1000;
 553                 break;
 554
 555         case AR71XX_SOC_AR7240:
 556         case AR71XX_SOC_AR7241:
 557                 pll_10 = AR724X_PLL_VAL_10;
 558                 pll_100 = AR724X_PLL_VAL_100;
 559                 pll_1000 = AR724X_PLL_VAL_1000;
 560                 break;
 561
 562         case AR71XX_SOC_AR7242:
 563                 pll_10 = AR7242_PLL_VAL_10;
 564                 pll_100 = AR7242_PLL_VAL_100;
 565                 pll_1000 = AR7242_PLL_VAL_1000;
 566                 break;
 567
 568         case AR71XX_SOC_AR9130:
 569         case AR71XX_SOC_AR9132:
 570                 pll_10 = AR91XX_PLL_VAL_10;
 571                 pll_100 = AR91XX_PLL_VAL_100;
 572                 pll_1000 = AR91XX_PLL_VAL_1000;
 573                 break;
 574
 575         case AR71XX_SOC_AR9330:
 576         case AR71XX_SOC_AR9331:
 577                 pll_10 = AR933X_PLL_VAL_10;
 578                 pll_100 = AR933X_PLL_VAL_100;
 579                 pll_1000 = AR933X_PLL_VAL_1000;
 580                 break;
 581
 582         case AR71XX_SOC_AR9341:
 583         case AR71XX_SOC_AR9342:
 584         case AR71XX_SOC_AR9344:
 585                 pll_10 = AR934X_PLL_VAL_10;
 586                 pll_100 = AR934X_PLL_VAL_100;
 587                 pll_1000 = AR934X_PLL_VAL_1000;
 588                 break;
 589
 590         default:
 591                 BUG();
 592         }
 593
 594         if (!pll_data->pll_10)
 595                 pll_data->pll_10 = pll_10;
 596
 597         if (!pll_data->pll_100)
 598                 pll_data->pll_100 = pll_100;
 599
 600         if (!pll_data->pll_1000)
 601                 pll_data->pll_1000 = pll_1000;
 602 }
 603
 604 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
 605                                            struct ag71xx_platform_data *pdata)
 606 {
 607         unsigned int mii_if;
 608
 609         switch (id) {
 610         case 0:
 611                 switch (ar71xx_soc) {
 612                 case AR71XX_SOC_AR7130:
 613                 case AR71XX_SOC_AR7141:
 614                 case AR71XX_SOC_AR7161:
 615                 case AR71XX_SOC_AR9130:
 616                 case AR71XX_SOC_AR9132:
 617                         switch (pdata->phy_if_mode) {
 618                         case PHY_INTERFACE_MODE_MII:
 619                                 mii_if = MII0_CTRL_IF_MII;
 620                                 break;
 621                         case PHY_INTERFACE_MODE_GMII:
 622                                 mii_if = MII0_CTRL_IF_GMII;
 623                                 break;
 624                         case PHY_INTERFACE_MODE_RGMII:
 625                                 mii_if = MII0_CTRL_IF_RGMII;
 626                                 break;
 627                         case PHY_INTERFACE_MODE_RMII:
 628                                 mii_if = MII0_CTRL_IF_RMII;
 629                                 break;
 630                         default:
 631                                 return -EINVAL;
 632                         }
 633                         ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
 634                         break;
 635
 636                 case AR71XX_SOC_AR7240:
 637                 case AR71XX_SOC_AR7241:
 638                 case AR71XX_SOC_AR9330:
 639                 case AR71XX_SOC_AR9331:
 640                         pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 641                         break;
 642
 643                 case AR71XX_SOC_AR7242:
 644                         /* FIXME */
 645
 646                 case AR71XX_SOC_AR9341:
 647                 case AR71XX_SOC_AR9342:
 648                 case AR71XX_SOC_AR9344:
 649                         switch (pdata->phy_if_mode) {
 650                         case PHY_INTERFACE_MODE_MII:
 651                         case PHY_INTERFACE_MODE_GMII:
 652                         case PHY_INTERFACE_MODE_RGMII:
 653                         case PHY_INTERFACE_MODE_RMII:
 654                                 break;
 655                         default:
 656                                 return -EINVAL;
 657                         }
 658                         break;
 659
 660                 default:
 661                         BUG();
 662                 }
 663                 break;
 664         case 1:
 665                 switch (ar71xx_soc) {
 666                 case AR71XX_SOC_AR7130:
 667                 case AR71XX_SOC_AR7141:
 668                 case AR71XX_SOC_AR7161:
 669                 case AR71XX_SOC_AR9130:
 670                 case AR71XX_SOC_AR9132:
 671                         switch (pdata->phy_if_mode) {
 672                         case PHY_INTERFACE_MODE_RMII:
 673                                 mii_if = MII1_CTRL_IF_RMII;
 674                                 break;
 675                         case PHY_INTERFACE_MODE_RGMII:
 676                                 mii_if = MII1_CTRL_IF_RGMII;
 677                                 break;
 678                         default:
 679                                 return -EINVAL;
 680                         }
 681                         ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
 682                         break;
 683
 684                 case AR71XX_SOC_AR7240:
 685                 case AR71XX_SOC_AR7241:
 686                 case AR71XX_SOC_AR9330:
 687                 case AR71XX_SOC_AR9331:
 688                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 689                         break;
 690
 691                 case AR71XX_SOC_AR7242:
 692                         /* FIXME */
 693
 694                 case AR71XX_SOC_AR9341:
 695                 case AR71XX_SOC_AR9342:
 696                 case AR71XX_SOC_AR9344:
 697                         switch (pdata->phy_if_mode) {
 698                         case PHY_INTERFACE_MODE_MII:
 699                         case PHY_INTERFACE_MODE_GMII:
 700                                 break;
 701                         default:
 702                                 return -EINVAL;
 703                         }
 704                         break;
 705
 706                 default:
 707                         BUG();
 708                 }
 709                 break;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int ar71xx_eth_instance __initdata;
 716 void __init ar71xx_add_device_eth(unsigned int id)
 717 {
 718         struct platform_device *pdev;
 719         struct ag71xx_platform_data *pdata;
 720         int err;
 721
 722         if (id > 1) {
 723                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 724                 return;
 725         }
 726
 727         ar71xx_init_eth_pll_data(id);
 728
 729         if (id == 0)
 730                 pdev = &ar71xx_eth0_device;
 731         else
 732                 pdev = &ar71xx_eth1_device;
 733
 734         pdata = pdev->dev.platform_data;
 735
 736         err = ar71xx_setup_phy_if_mode(id, pdata);
 737         if (err) {
 738                 printk(KERN_ERR
 739                        "ar71xx: invalid PHY interface mode for GE%u\n", id);
 740                 return;
 741         }
 742
 743         switch (ar71xx_soc) {
 744         case AR71XX_SOC_AR7130:
 745                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 746                                       : ar71xx_ddr_flush_ge0;
 747                 pdata->set_speed = id ? ar71xx_set_speed_ge1
 748                                       : ar71xx_set_speed_ge0;
 749                 break;
 750
 751         case AR71XX_SOC_AR7141:
 752         case AR71XX_SOC_AR7161:
 753                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 754                                       : ar71xx_ddr_flush_ge0;
 755                 pdata->set_speed = id ? ar71xx_set_speed_ge1
 756                                       : ar71xx_set_speed_ge0;
 757                 pdata->has_gbit = 1;
 758                 break;
 759
 760         case AR71XX_SOC_AR7242:
 761                 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
 762                                               RESET_MODULE_GE0_PHY;
 763                 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
 764                                               RESET_MODULE_GE1_PHY;
 765                 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
 766                                       : ar724x_ddr_flush_ge0;
 767                 pdata->set_speed = id ? ar724x_set_speed_ge1
 768                                       : ar7242_set_speed_ge0;
 769                 pdata->has_gbit = 1;
 770                 pdata->is_ar724x = 1;
 771
 772                 if (!pdata->fifo_cfg1)
 773                         pdata->fifo_cfg1 = 0x0010ffff;
 774                 if (!pdata->fifo_cfg2)
 775                         pdata->fifo_cfg2 = 0x015500aa;
 776                 if (!pdata->fifo_cfg3)
 777                         pdata->fifo_cfg3 = 0x01f00140;
 778                 break;
 779
 780         case AR71XX_SOC_AR7241:
 781                 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
 782                 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
 783                 /* fall through */
 784         case AR71XX_SOC_AR7240:
 785                 ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
 786                 ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
 787                 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
 788                                       : ar724x_ddr_flush_ge0;
 789                 pdata->set_speed = id ? ar724x_set_speed_ge1
 790                                       : ar724x_set_speed_ge0;
 791                 pdata->is_ar724x = 1;
 792                 if (ar71xx_soc == AR71XX_SOC_AR7240)
 793                         pdata->is_ar7240 = 1;
 794
 795                 if (!pdata->fifo_cfg1)
 796                         pdata->fifo_cfg1 = 0x0010ffff;
 797                 if (!pdata->fifo_cfg2)
 798                         pdata->fifo_cfg2 = 0x015500aa;
 799                 if (!pdata->fifo_cfg3)
 800                         pdata->fifo_cfg3 = 0x01f00140;
 801                 break;
 802
 803         case AR71XX_SOC_AR9130:
 804                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 805                                       : ar91xx_ddr_flush_ge0;
 806                 pdata->set_speed = id ? ar91xx_set_speed_ge1
 807                                       : ar91xx_set_speed_ge0;
 808                 pdata->is_ar91xx = 1;
 809                 break;
 810
 811         case AR71XX_SOC_AR9132:
 812                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 813                                       : ar91xx_ddr_flush_ge0;
 814                 pdata->set_speed = id ? ar91xx_set_speed_ge1
 815                                       : ar91xx_set_speed_ge0;
 816                 pdata->is_ar91xx = 1;
 817                 pdata->has_gbit = 1;
 818                 break;
 819
 820         case AR71XX_SOC_AR9330:
 821         case AR71XX_SOC_AR9331:
 822                 ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
 823                                              AR933X_RESET_GE0_MDIO;
 824                 ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
 825                                              AR933X_RESET_GE1_MDIO;
 826                 pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
 827                                       : ar933x_ddr_flush_ge0;
 828                 pdata->set_speed = id ? ar933x_set_speed_ge1
 829                                       : ar933x_set_speed_ge0;
 830                 pdata->has_gbit = 1;
 831                 pdata->is_ar724x = 1;
 832
 833                 if (!pdata->fifo_cfg1)
 834                         pdata->fifo_cfg1 = 0x0010ffff;
 835                 if (!pdata->fifo_cfg2)
 836                         pdata->fifo_cfg2 = 0x015500aa;
 837                 if (!pdata->fifo_cfg3)
 838                         pdata->fifo_cfg3 = 0x01f00140;
 839                 break;
 840
 841         case AR71XX_SOC_AR9341:
 842         case AR71XX_SOC_AR9342:
 843         case AR71XX_SOC_AR9344:
 844                 ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
 845                                              AR934X_RESET_GE0_MDIO;
 846                 ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
 847                                              AR934X_RESET_GE1_MDIO;
 848                 pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
 849                                       : ar934x_ddr_flush_ge0;
 850                 pdata->set_speed = id ? ar934x_set_speed_ge1
 851                                       : ar934x_set_speed_ge0;
 852                 pdata->has_gbit = 1;
 853                 pdata->is_ar724x = 1;
 854
 855                 if (!pdata->fifo_cfg1)
 856                         pdata->fifo_cfg1 = 0x0010ffff;
 857                 if (!pdata->fifo_cfg2)
 858                         pdata->fifo_cfg2 = 0x015500aa;
 859                 if (!pdata->fifo_cfg3)
 860                         pdata->fifo_cfg3 = 0x01f00140;
 861                 break;
 862
 863         default:
 864                 BUG();
 865         }
 866
 867         switch (pdata->phy_if_mode) {
 868         case PHY_INTERFACE_MODE_GMII:
 869         case PHY_INTERFACE_MODE_RGMII:
 870                 if (!pdata->has_gbit) {
 871                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
 872                                         id);
 873                         return;
 874                 }
 875                 /* fallthrough */
 876         default:
 877                 break;
 878         }
 879
 880         if (!is_valid_ether_addr(pdata->mac_addr)) {
 881                 random_ether_addr(pdata->mac_addr);
 882                 printk(KERN_DEBUG
 883                         "ar71xx: using random MAC address for eth%d\n",
 884                         ar71xx_eth_instance);
 885         }
 886
 887         if (pdata->mii_bus_dev == NULL) {
 888                 switch (ar71xx_soc) {
 889                 case AR71XX_SOC_AR9341:
 890                 case AR71XX_SOC_AR9342:
 891                 case AR71XX_SOC_AR9344:
 892                         if (id == 0)
 893                                 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
 894                         else
 895                                 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
 896                         break;
 897
 898                 case AR71XX_SOC_AR7241:
 899                 case AR71XX_SOC_AR9330:
 900                 case AR71XX_SOC_AR9331:
 901                         pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
 902                         break;
 903
 904                 default:
 905                         pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
 906                         break;
 907                 }
 908         }
 909
 910         /* Reset the device */
 911         ar71xx_device_stop(pdata->reset_bit);
 912         mdelay(100);
 913
 914         ar71xx_device_start(pdata->reset_bit);
 915         mdelay(100);
 916
 917         platform_device_register(pdev);
 918         ar71xx_eth_instance++;
 919 }
 920
 921 static struct resource ar71xx_spi_resources[] = {
 922         [0] = {
 923                 .start  = AR71XX_SPI_BASE,
 924                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 925                 .flags  = IORESOURCE_MEM,
 926         },
 927 };
 928
 929 static struct platform_device ar71xx_spi_device = {
 930         .name           = "ar71xx-spi",
 931         .id             = -1,
 932         .resource       = ar71xx_spi_resources,
 933         .num_resources  = ARRAY_SIZE(ar71xx_spi_resources),
 934 };
 935
 936 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
 937                                 struct spi_board_info const *info,
 938                                 unsigned n)
 939 {
 940         spi_register_board_info(info, n);
 941         ar71xx_spi_device.dev.platform_data = pdata;
 942         platform_device_register(&ar71xx_spi_device);
 943 }
 944
 945 void __init ar71xx_add_device_wdt(void)
 946 {
 947         platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
 948 }
 949
 950 void __init ar71xx_set_mac_base(unsigned char *mac)
 951 {
 952         memcpy(ar71xx_mac_base, mac, ETH_ALEN);
 953 }
 954
 955 void __init ar71xx_parse_mac_addr(char *mac_str)
 956 {
 957         u8 tmp[ETH_ALEN];
 958         int t;
 959
 960         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 961                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 962
 963         if (t != ETH_ALEN)
 964                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
 965                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 966
 967         if (t == ETH_ALEN)
 968                 ar71xx_set_mac_base(tmp);
 969         else
 970                 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
 971                                 "\"%s\"\n", mac_str);
 972 }
 973
 974 static int __init ar71xx_ethaddr_setup(char *str)
 975 {
 976         ar71xx_parse_mac_addr(str);
 977         return 1;
 978 }
 979 __setup("ethaddr=", ar71xx_ethaddr_setup);
 980
 981 static int __init ar71xx_kmac_setup(char *str)
 982 {
 983         ar71xx_parse_mac_addr(str);
 984         return 1;
 985 }
 986 __setup("kmac=", ar71xx_kmac_setup);
 987
 988 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
 989                             unsigned offset)
 990 {
 991         u32 t;
 992
 993         if (!is_valid_ether_addr(src)) {
 994                 memset(dst, '\0', ETH_ALEN);
 995                 return;
 996         }
 997
 998         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
 999         t += offset;
1000
1001         dst[0] = src[0];
1002         dst[1] = src[1];
1003         dst[2] = src[2];
1004         dst[3] = (t >> 16) & 0xff;
1005         dst[4] = (t >> 8) & 0xff;
1006         dst[5] = t & 0xff;
1007 }