2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
30 static struct resource ar71xx_uart_resources[] = {
32 .start = AR71XX_UART_BASE,
33 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
34 .flags = IORESOURCE_MEM,
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data[] = {
41 .mapbase = AR71XX_UART_BASE,
42 .irq = AR71XX_MISC_IRQ_UART,
43 .flags = AR71XX_UART_FLAGS,
47 /* terminating entry */
51 static struct platform_device ar71xx_uart_device = {
53 .id = PLAT8250_DEV_PLATFORM,
54 .resource = ar71xx_uart_resources,
55 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
57 .platform_data = ar71xx_uart_data
61 static struct resource ar933x_uart_resources[] = {
63 .start = AR933X_UART_BASE,
64 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
65 .flags = IORESOURCE_MEM,
68 .start = AR71XX_MISC_IRQ_UART,
69 .end = AR71XX_MISC_IRQ_UART,
70 .flags = IORESOURCE_IRQ,
74 static struct ar933x_uart_platform_data ar933x_uart_data;
75 static struct platform_device ar933x_uart_device = {
76 .name = "ar933x-uart",
78 .resource = ar933x_uart_resources,
79 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
81 .platform_data = &ar933x_uart_data,
85 void __init ar71xx_add_device_uart(void)
87 struct platform_device *pdev;
90 case AR71XX_SOC_AR7130:
91 case AR71XX_SOC_AR7141:
92 case AR71XX_SOC_AR7161:
93 case AR71XX_SOC_AR7240:
94 case AR71XX_SOC_AR7241:
95 case AR71XX_SOC_AR7242:
96 case AR71XX_SOC_AR9130:
97 case AR71XX_SOC_AR9132:
98 pdev = &ar71xx_uart_device;
99 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
102 case AR71XX_SOC_AR9330:
103 case AR71XX_SOC_AR9331:
104 pdev = &ar933x_uart_device;
105 ar933x_uart_data.uartclk = ar71xx_ref_freq;
108 case AR71XX_SOC_AR9341:
109 case AR71XX_SOC_AR9342:
110 case AR71XX_SOC_AR9344:
111 pdev = &ar71xx_uart_device;
112 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
119 platform_device_register(pdev);
122 static struct resource ar71xx_mdio0_resources[] = {
125 .flags = IORESOURCE_MEM,
126 .start = AR71XX_GE0_BASE,
127 .end = AR71XX_GE0_BASE + 0x200 - 1,
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
133 struct platform_device ar71xx_mdio0_device = {
134 .name = "ag71xx-mdio",
136 .resource = ar71xx_mdio0_resources,
137 .num_resources = ARRAY_SIZE(ar71xx_mdio0_resources),
139 .platform_data = &ar71xx_mdio0_data,
143 static struct resource ar71xx_mdio1_resources[] = {
146 .flags = IORESOURCE_MEM,
147 .start = AR71XX_GE1_BASE,
148 .end = AR71XX_GE1_BASE + 0x200 - 1,
152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
154 struct platform_device ar71xx_mdio1_device = {
155 .name = "ag71xx-mdio",
157 .resource = ar71xx_mdio1_resources,
158 .num_resources = ARRAY_SIZE(ar71xx_mdio1_resources),
160 .platform_data = &ar71xx_mdio1_data,
164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
169 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
171 t = __raw_readl(base + cfg_reg);
174 __raw_writel(t, base + cfg_reg);
177 __raw_writel(pll_val, base + pll_reg);
180 __raw_writel(t, base + cfg_reg);
184 __raw_writel(t, base + cfg_reg);
187 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
188 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
193 static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
199 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
201 t = __raw_readl(base + reg);
202 t &= ~(MII_CTRL_IF_MASK);
203 t |= (mii_if & MII_CTRL_IF_MASK);
204 __raw_writel(t, base + reg);
209 static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
212 unsigned int mii_speed;
217 mii_speed = MII_CTRL_SPEED_10;
220 mii_speed = MII_CTRL_SPEED_100;
223 mii_speed = MII_CTRL_SPEED_1000;
229 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
231 t = __raw_readl(base + reg);
232 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
233 t |= mii_speed << MII_CTRL_SPEED_SHIFT;
234 __raw_writel(t, base + reg);
239 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
241 struct platform_device *mdio_dev;
242 struct ag71xx_mdio_platform_data *mdio_data;
245 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
246 ar71xx_soc == AR71XX_SOC_AR9342 ||
247 ar71xx_soc == AR71XX_SOC_AR9344)
253 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
257 switch (ar71xx_soc) {
258 case AR71XX_SOC_AR7241:
259 case AR71XX_SOC_AR9330:
260 case AR71XX_SOC_AR9331:
261 mdio_dev = &ar71xx_mdio1_device;
262 mdio_data = &ar71xx_mdio1_data;
265 case AR71XX_SOC_AR9341:
266 case AR71XX_SOC_AR9342:
267 case AR71XX_SOC_AR9344:
269 mdio_dev = &ar71xx_mdio0_device;
270 mdio_data = &ar71xx_mdio0_data;
272 mdio_dev = &ar71xx_mdio1_device;
273 mdio_data = &ar71xx_mdio1_data;
277 case AR71XX_SOC_AR7242:
278 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
279 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
280 AR71XX_ETH0_PLL_SHIFT);
283 mdio_dev = &ar71xx_mdio0_device;
284 mdio_data = &ar71xx_mdio0_data;
288 mdio_data->phy_mask = phy_mask;
290 switch (ar71xx_soc) {
291 case AR71XX_SOC_AR7240:
292 case AR71XX_SOC_AR7241:
293 case AR71XX_SOC_AR9330:
294 case AR71XX_SOC_AR9331:
295 mdio_data->is_ar7240 = 1;
298 case AR71XX_SOC_AR9341:
299 case AR71XX_SOC_AR9342:
300 case AR71XX_SOC_AR9344:
302 mdio_data->is_ar7240 = 1;
309 platform_device_register(mdio_dev);
312 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
313 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
315 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
317 struct ar71xx_eth_pll_data *pll_data;
322 pll_data = &ar71xx_eth0_pll_data;
325 pll_data = &ar71xx_eth1_pll_data;
333 pll_val = pll_data->pll_10;
336 pll_val = pll_data->pll_100;
339 pll_val = pll_data->pll_1000;
348 static void ar71xx_set_speed_ge0(int speed)
350 u32 val = ar71xx_get_eth_pll(0, speed);
352 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
353 val, AR71XX_ETH0_PLL_SHIFT);
354 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
357 static void ar71xx_set_speed_ge1(int speed)
359 u32 val = ar71xx_get_eth_pll(1, speed);
361 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
362 val, AR71XX_ETH1_PLL_SHIFT);
363 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
366 static void ar724x_set_speed_ge0(int speed)
371 static void ar724x_set_speed_ge1(int speed)
376 static void ar7242_set_speed_ge0(int speed)
378 u32 val = ar71xx_get_eth_pll(0, speed);
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
386 static void ar91xx_set_speed_ge0(int speed)
388 u32 val = ar71xx_get_eth_pll(0, speed);
390 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
391 val, AR91XX_ETH0_PLL_SHIFT);
392 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
395 static void ar91xx_set_speed_ge1(int speed)
397 u32 val = ar71xx_get_eth_pll(1, speed);
399 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
400 val, AR91XX_ETH1_PLL_SHIFT);
401 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
404 static void ar933x_set_speed_ge0(int speed)
409 static void ar933x_set_speed_ge1(int speed)
414 static void ar934x_set_speed_ge0(int speed)
419 static void ar934x_set_speed_ge1(int speed)
424 static void ar71xx_ddr_flush_ge0(void)
426 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
429 static void ar71xx_ddr_flush_ge1(void)
431 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
434 static void ar724x_ddr_flush_ge0(void)
436 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
439 static void ar724x_ddr_flush_ge1(void)
441 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
444 static void ar91xx_ddr_flush_ge0(void)
446 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
449 static void ar91xx_ddr_flush_ge1(void)
451 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
454 static void ar933x_ddr_flush_ge0(void)
456 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
459 static void ar933x_ddr_flush_ge1(void)
461 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
464 static void ar934x_ddr_flush_ge0(void)
466 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
469 static void ar934x_ddr_flush_ge1(void)
471 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
474 static struct resource ar71xx_eth0_resources[] = {
477 .flags = IORESOURCE_MEM,
478 .start = AR71XX_GE0_BASE,
479 .end = AR71XX_GE0_BASE + 0x200 - 1,
482 .flags = IORESOURCE_IRQ,
483 .start = AR71XX_CPU_IRQ_GE0,
484 .end = AR71XX_CPU_IRQ_GE0,
488 struct ag71xx_platform_data ar71xx_eth0_data = {
489 .reset_bit = RESET_MODULE_GE0_MAC,
492 struct platform_device ar71xx_eth0_device = {
495 .resource = ar71xx_eth0_resources,
496 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
498 .platform_data = &ar71xx_eth0_data,
502 static struct resource ar71xx_eth1_resources[] = {
505 .flags = IORESOURCE_MEM,
506 .start = AR71XX_GE1_BASE,
507 .end = AR71XX_GE1_BASE + 0x200 - 1,
510 .flags = IORESOURCE_IRQ,
511 .start = AR71XX_CPU_IRQ_GE1,
512 .end = AR71XX_CPU_IRQ_GE1,
516 struct ag71xx_platform_data ar71xx_eth1_data = {
517 .reset_bit = RESET_MODULE_GE1_MAC,
520 struct platform_device ar71xx_eth1_device = {
523 .resource = ar71xx_eth1_resources,
524 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
526 .platform_data = &ar71xx_eth1_data,
530 #define AR71XX_PLL_VAL_1000 0x00110000
531 #define AR71XX_PLL_VAL_100 0x00001099
532 #define AR71XX_PLL_VAL_10 0x00991099
534 #define AR724X_PLL_VAL_1000 0x00110000
535 #define AR724X_PLL_VAL_100 0x00001099
536 #define AR724X_PLL_VAL_10 0x00991099
538 #define AR7242_PLL_VAL_1000 0x16000000
539 #define AR7242_PLL_VAL_100 0x00000101
540 #define AR7242_PLL_VAL_10 0x00001616
542 #define AR91XX_PLL_VAL_1000 0x1a000000
543 #define AR91XX_PLL_VAL_100 0x13000a44
544 #define AR91XX_PLL_VAL_10 0x00441099
546 #define AR933X_PLL_VAL_1000 0x00110000
547 #define AR933X_PLL_VAL_100 0x00001099
548 #define AR933X_PLL_VAL_10 0x00991099
550 #define AR934X_PLL_VAL_1000 0x00110000
551 #define AR934X_PLL_VAL_100 0x00001099
552 #define AR934X_PLL_VAL_10 0x00991099
554 static void __init ar71xx_init_eth_pll_data(unsigned int id)
556 struct ar71xx_eth_pll_data *pll_data;
557 u32 pll_10, pll_100, pll_1000;
561 pll_data = &ar71xx_eth0_pll_data;
564 pll_data = &ar71xx_eth1_pll_data;
570 switch (ar71xx_soc) {
571 case AR71XX_SOC_AR7130:
572 case AR71XX_SOC_AR7141:
573 case AR71XX_SOC_AR7161:
574 pll_10 = AR71XX_PLL_VAL_10;
575 pll_100 = AR71XX_PLL_VAL_100;
576 pll_1000 = AR71XX_PLL_VAL_1000;
579 case AR71XX_SOC_AR7240:
580 case AR71XX_SOC_AR7241:
581 pll_10 = AR724X_PLL_VAL_10;
582 pll_100 = AR724X_PLL_VAL_100;
583 pll_1000 = AR724X_PLL_VAL_1000;
586 case AR71XX_SOC_AR7242:
587 pll_10 = AR7242_PLL_VAL_10;
588 pll_100 = AR7242_PLL_VAL_100;
589 pll_1000 = AR7242_PLL_VAL_1000;
592 case AR71XX_SOC_AR9130:
593 case AR71XX_SOC_AR9132:
594 pll_10 = AR91XX_PLL_VAL_10;
595 pll_100 = AR91XX_PLL_VAL_100;
596 pll_1000 = AR91XX_PLL_VAL_1000;
599 case AR71XX_SOC_AR9330:
600 case AR71XX_SOC_AR9331:
601 pll_10 = AR933X_PLL_VAL_10;
602 pll_100 = AR933X_PLL_VAL_100;
603 pll_1000 = AR933X_PLL_VAL_1000;
606 case AR71XX_SOC_AR9341:
607 case AR71XX_SOC_AR9342:
608 case AR71XX_SOC_AR9344:
609 pll_10 = AR934X_PLL_VAL_10;
610 pll_100 = AR934X_PLL_VAL_100;
611 pll_1000 = AR934X_PLL_VAL_1000;
618 if (!pll_data->pll_10)
619 pll_data->pll_10 = pll_10;
621 if (!pll_data->pll_100)
622 pll_data->pll_100 = pll_100;
624 if (!pll_data->pll_1000)
625 pll_data->pll_1000 = pll_1000;
628 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
629 struct ag71xx_platform_data *pdata)
635 switch (ar71xx_soc) {
636 case AR71XX_SOC_AR7130:
637 case AR71XX_SOC_AR7141:
638 case AR71XX_SOC_AR7161:
639 case AR71XX_SOC_AR9130:
640 case AR71XX_SOC_AR9132:
641 switch (pdata->phy_if_mode) {
642 case PHY_INTERFACE_MODE_MII:
643 mii_if = MII0_CTRL_IF_MII;
645 case PHY_INTERFACE_MODE_GMII:
646 mii_if = MII0_CTRL_IF_GMII;
648 case PHY_INTERFACE_MODE_RGMII:
649 mii_if = MII0_CTRL_IF_RGMII;
651 case PHY_INTERFACE_MODE_RMII:
652 mii_if = MII0_CTRL_IF_RMII;
657 ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
660 case AR71XX_SOC_AR7240:
661 case AR71XX_SOC_AR7241:
662 case AR71XX_SOC_AR9330:
663 case AR71XX_SOC_AR9331:
664 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
667 case AR71XX_SOC_AR7242:
670 case AR71XX_SOC_AR9341:
671 case AR71XX_SOC_AR9342:
672 case AR71XX_SOC_AR9344:
673 switch (pdata->phy_if_mode) {
674 case PHY_INTERFACE_MODE_MII:
675 case PHY_INTERFACE_MODE_GMII:
676 case PHY_INTERFACE_MODE_RGMII:
677 case PHY_INTERFACE_MODE_RMII:
689 switch (ar71xx_soc) {
690 case AR71XX_SOC_AR7130:
691 case AR71XX_SOC_AR7141:
692 case AR71XX_SOC_AR7161:
693 case AR71XX_SOC_AR9130:
694 case AR71XX_SOC_AR9132:
695 switch (pdata->phy_if_mode) {
696 case PHY_INTERFACE_MODE_RMII:
697 mii_if = MII1_CTRL_IF_RMII;
699 case PHY_INTERFACE_MODE_RGMII:
700 mii_if = MII1_CTRL_IF_RGMII;
705 ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
708 case AR71XX_SOC_AR7240:
709 case AR71XX_SOC_AR7241:
710 case AR71XX_SOC_AR9330:
711 case AR71XX_SOC_AR9331:
712 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
715 case AR71XX_SOC_AR7242:
718 case AR71XX_SOC_AR9341:
719 case AR71XX_SOC_AR9342:
720 case AR71XX_SOC_AR9344:
721 switch (pdata->phy_if_mode) {
722 case PHY_INTERFACE_MODE_MII:
723 case PHY_INTERFACE_MODE_GMII:
739 static int ar71xx_eth_instance __initdata;
740 void __init ar71xx_add_device_eth(unsigned int id)
742 struct platform_device *pdev;
743 struct ag71xx_platform_data *pdata;
747 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
751 ar71xx_init_eth_pll_data(id);
754 pdev = &ar71xx_eth0_device;
756 pdev = &ar71xx_eth1_device;
758 pdata = pdev->dev.platform_data;
760 err = ar71xx_setup_phy_if_mode(id, pdata);
763 "ar71xx: invalid PHY interface mode for GE%u\n", id);
767 switch (ar71xx_soc) {
768 case AR71XX_SOC_AR7130:
770 pdata->ddr_flush = ar71xx_ddr_flush_ge0;
771 pdata->set_speed = ar71xx_set_speed_ge0;
773 pdata->ddr_flush = ar71xx_ddr_flush_ge1;
774 pdata->set_speed = ar71xx_set_speed_ge1;
778 case AR71XX_SOC_AR7141:
779 case AR71XX_SOC_AR7161:
781 pdata->ddr_flush = ar71xx_ddr_flush_ge0;
782 pdata->set_speed = ar71xx_set_speed_ge0;
784 pdata->ddr_flush = ar71xx_ddr_flush_ge1;
785 pdata->set_speed = ar71xx_set_speed_ge1;
790 case AR71XX_SOC_AR7242:
792 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
793 RESET_MODULE_GE0_PHY;
794 pdata->ddr_flush = ar724x_ddr_flush_ge0;
795 pdata->set_speed = ar7242_set_speed_ge0;
797 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
798 RESET_MODULE_GE1_PHY;
799 pdata->ddr_flush = ar724x_ddr_flush_ge1;
800 pdata->set_speed = ar724x_set_speed_ge1;
803 pdata->is_ar724x = 1;
805 if (!pdata->fifo_cfg1)
806 pdata->fifo_cfg1 = 0x0010ffff;
807 if (!pdata->fifo_cfg2)
808 pdata->fifo_cfg2 = 0x015500aa;
809 if (!pdata->fifo_cfg3)
810 pdata->fifo_cfg3 = 0x01f00140;
813 case AR71XX_SOC_AR7241:
815 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
817 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
819 case AR71XX_SOC_AR7240:
821 pdata->reset_bit |= RESET_MODULE_GE0_PHY;
822 pdata->ddr_flush = ar724x_ddr_flush_ge0;
823 pdata->set_speed = ar724x_set_speed_ge0;
825 pdata->reset_bit |= RESET_MODULE_GE1_PHY;
826 pdata->ddr_flush = ar724x_ddr_flush_ge1;
827 pdata->set_speed = ar724x_set_speed_ge1;
830 pdata->is_ar724x = 1;
831 if (ar71xx_soc == AR71XX_SOC_AR7240)
832 pdata->is_ar7240 = 1;
834 if (!pdata->fifo_cfg1)
835 pdata->fifo_cfg1 = 0x0010ffff;
836 if (!pdata->fifo_cfg2)
837 pdata->fifo_cfg2 = 0x015500aa;
838 if (!pdata->fifo_cfg3)
839 pdata->fifo_cfg3 = 0x01f00140;
842 case AR71XX_SOC_AR9130:
844 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
845 pdata->set_speed = ar91xx_set_speed_ge0;
847 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
848 pdata->set_speed = ar91xx_set_speed_ge1;
850 pdata->is_ar91xx = 1;
853 case AR71XX_SOC_AR9132:
855 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
856 pdata->set_speed = ar91xx_set_speed_ge0;
858 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
859 pdata->set_speed = ar91xx_set_speed_ge1;
861 pdata->is_ar91xx = 1;
865 case AR71XX_SOC_AR9330:
866 case AR71XX_SOC_AR9331:
868 pdata->reset_bit = AR933X_RESET_GE0_MAC |
869 AR933X_RESET_GE0_MDIO;
870 pdata->ddr_flush = ar933x_ddr_flush_ge0;
871 pdata->set_speed = ar933x_set_speed_ge0;
873 pdata->reset_bit = AR933X_RESET_GE1_MAC |
874 AR933X_RESET_GE1_MDIO;
875 pdata->ddr_flush = ar933x_ddr_flush_ge1;
876 pdata->set_speed = ar933x_set_speed_ge1;
880 pdata->is_ar724x = 1;
882 if (!pdata->fifo_cfg1)
883 pdata->fifo_cfg1 = 0x0010ffff;
884 if (!pdata->fifo_cfg2)
885 pdata->fifo_cfg2 = 0x015500aa;
886 if (!pdata->fifo_cfg3)
887 pdata->fifo_cfg3 = 0x01f00140;
890 case AR71XX_SOC_AR9341:
891 case AR71XX_SOC_AR9342:
892 case AR71XX_SOC_AR9344:
894 pdata->reset_bit = AR934X_RESET_GE0_MAC |
895 AR934X_RESET_GE0_MDIO;
896 pdata->ddr_flush =ar934x_ddr_flush_ge0;
897 pdata->set_speed = ar934x_set_speed_ge0;
899 pdata->reset_bit = AR934X_RESET_GE1_MAC |
900 AR934X_RESET_GE1_MDIO;
901 pdata->ddr_flush = ar934x_ddr_flush_ge1;
902 pdata->set_speed = ar934x_set_speed_ge1
906 pdata->is_ar724x = 1;
908 if (!pdata->fifo_cfg1)
909 pdata->fifo_cfg1 = 0x0010ffff;
910 if (!pdata->fifo_cfg2)
911 pdata->fifo_cfg2 = 0x015500aa;
912 if (!pdata->fifo_cfg3)
913 pdata->fifo_cfg3 = 0x01f00140;
920 switch (pdata->phy_if_mode) {
921 case PHY_INTERFACE_MODE_GMII:
922 case PHY_INTERFACE_MODE_RGMII:
923 if (!pdata->has_gbit) {
924 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
933 if (!is_valid_ether_addr(pdata->mac_addr)) {
934 random_ether_addr(pdata->mac_addr);
936 "ar71xx: using random MAC address for eth%d\n",
937 ar71xx_eth_instance);
940 if (pdata->mii_bus_dev == NULL) {
941 switch (ar71xx_soc) {
942 case AR71XX_SOC_AR9341:
943 case AR71XX_SOC_AR9342:
944 case AR71XX_SOC_AR9344:
946 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
948 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
951 case AR71XX_SOC_AR7241:
952 case AR71XX_SOC_AR9330:
953 case AR71XX_SOC_AR9331:
954 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
958 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
963 /* Reset the device */
964 ar71xx_device_stop(pdata->reset_bit);
967 ar71xx_device_start(pdata->reset_bit);
970 platform_device_register(pdev);
971 ar71xx_eth_instance++;
974 static struct resource ar71xx_spi_resources[] = {
976 .start = AR71XX_SPI_BASE,
977 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
978 .flags = IORESOURCE_MEM,
982 static struct platform_device ar71xx_spi_device = {
983 .name = "ar71xx-spi",
985 .resource = ar71xx_spi_resources,
986 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
989 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
990 struct spi_board_info const *info,
993 spi_register_board_info(info, n);
994 ar71xx_spi_device.dev.platform_data = pdata;
995 platform_device_register(&ar71xx_spi_device);
998 void __init ar71xx_add_device_wdt(void)
1000 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
1003 void __init ar71xx_set_mac_base(unsigned char *mac)
1005 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
1008 void __init ar71xx_parse_mac_addr(char *mac_str)
1013 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1014 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1017 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1018 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1021 ar71xx_set_mac_base(tmp);
1023 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1024 "\"%s\"\n", mac_str);
1027 static int __init ar71xx_ethaddr_setup(char *str)
1029 ar71xx_parse_mac_addr(str);
1032 __setup("ethaddr=", ar71xx_ethaddr_setup);
1034 static int __init ar71xx_kmac_setup(char *str)
1036 ar71xx_parse_mac_addr(str);
1039 __setup("kmac=", ar71xx_kmac_setup);
1041 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
1046 if (!is_valid_ether_addr(src)) {
1047 memset(dst, '\0', ETH_ALEN);
1051 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1057 dst[3] = (t >> 16) & 0xff;
1058 dst[4] = (t >> 8) & 0xff;