2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
21 #include <linux/ath9k_platform.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
27 static u8 ar71xx_mac_base[ETH_ALEN] __initdata;
30 * OHCI (USB full speed host controller)
32 static struct resource ar71xx_ohci_resources[] = {
34 .start = AR71XX_OHCI_BASE,
35 .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1,
36 .flags = IORESOURCE_MEM,
39 .start = AR71XX_MISC_IRQ_OHCI,
40 .end = AR71XX_MISC_IRQ_OHCI,
41 .flags = IORESOURCE_IRQ,
45 static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32);
46 static struct platform_device ar71xx_ohci_device = {
47 .name = "ar71xx-ohci",
49 .resource = ar71xx_ohci_resources,
50 .num_resources = ARRAY_SIZE(ar71xx_ohci_resources),
52 .dma_mask = &ar71xx_ohci_dmamask,
53 .coherent_dma_mask = DMA_BIT_MASK(32),
58 * EHCI (USB full speed host controller)
60 static struct resource ar71xx_ehci_resources[] = {
62 .start = AR71XX_EHCI_BASE,
63 .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1,
64 .flags = IORESOURCE_MEM,
67 .start = AR71XX_CPU_IRQ_USB,
68 .end = AR71XX_CPU_IRQ_USB,
69 .flags = IORESOURCE_IRQ,
74 static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32);
75 static struct ar71xx_ehci_platform_data ar71xx_ehci_data;
77 static struct platform_device ar71xx_ehci_device = {
78 .name = "ar71xx-ehci",
80 .resource = ar71xx_ehci_resources,
81 .num_resources = ARRAY_SIZE(ar71xx_ehci_resources),
83 .dma_mask = &ar71xx_ehci_dmamask,
84 .coherent_dma_mask = DMA_BIT_MASK(32),
85 .platform_data = &ar71xx_ehci_data,
89 #define AR71XX_USB_RESET_MASK \
90 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
91 | RESET_MODULE_USB_OHCI_DLL)
93 static void ar71xx_usb_setup(void)
95 ar71xx_device_stop(AR71XX_USB_RESET_MASK);
97 ar71xx_device_start(AR71XX_USB_RESET_MASK);
99 /* Turning on the Buff and Desc swap bits */
100 ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000);
102 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
103 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00);
108 static void ar91xx_usb_setup(void)
110 ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE);
113 ar71xx_device_start(RESET_MODULE_USB_HOST);
116 ar71xx_device_start(RESET_MODULE_USB_PHY);
120 void __init ar71xx_add_device_usb(void)
122 switch (ar71xx_soc) {
123 case AR71XX_SOC_AR7130:
124 case AR71XX_SOC_AR7141:
125 case AR71XX_SOC_AR7161:
127 platform_device_register(&ar71xx_ohci_device);
128 platform_device_register(&ar71xx_ehci_device);
131 case AR71XX_SOC_AR9130:
132 case AR71XX_SOC_AR9132:
134 ar71xx_ehci_data.is_ar91xx = 1;
135 platform_device_register(&ar71xx_ehci_device);
143 #ifndef CONFIG_AR71XX_EARLY_SERIAL
144 static struct resource ar71xx_uart_resources[] = {
146 .start = AR71XX_UART_BASE,
147 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
148 .flags = IORESOURCE_MEM,
152 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
153 static struct plat_serial8250_port ar71xx_uart_data[] = {
155 .mapbase = AR71XX_UART_BASE,
156 .irq = AR71XX_MISC_IRQ_UART,
157 .flags = AR71XX_UART_FLAGS,
158 .iotype = UPIO_MEM32,
161 /* terminating entry */
165 static struct platform_device ar71xx_uart_device = {
166 .name = "serial8250",
167 .id = PLAT8250_DEV_PLATFORM,
168 .resource = ar71xx_uart_resources,
169 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
171 .platform_data = ar71xx_uart_data
175 void __init ar71xx_add_device_uart(void)
177 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
178 platform_device_register(&ar71xx_uart_device);
180 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
182 static struct resource ar71xx_mdio_resources[] = {
185 .flags = IORESOURCE_MEM,
186 .start = AR71XX_GE0_BASE + 0x20,
187 .end = AR71XX_GE0_BASE + 0x38 - 1,
191 static struct ag71xx_mdio_platform_data ar71xx_mdio_data = {
192 .phy_mask = 0xffffffff,
195 static struct platform_device ar71xx_mdio_device = {
196 .name = "ag71xx-mdio",
198 .resource = ar71xx_mdio_resources,
199 .num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
201 .platform_data = &ar71xx_mdio_data,
205 void __init ar71xx_add_device_mdio(u32 phy_mask)
207 ar71xx_mdio_data.phy_mask = phy_mask;
208 platform_device_register(&ar71xx_mdio_device);
211 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
216 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
218 t = __raw_readl(base + cfg_reg);
221 __raw_writel(t, base + cfg_reg);
224 __raw_writel(pll_val, base + pll_reg);
227 __raw_writel(t, base + cfg_reg);
231 __raw_writel(t, base + cfg_reg);
234 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
235 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
240 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
241 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
243 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
245 struct ar71xx_eth_pll_data *pll_data;
250 pll_data = &ar71xx_eth0_pll_data;
253 pll_data = &ar71xx_eth1_pll_data;
261 pll_val = pll_data->pll_10;
264 pll_val = pll_data->pll_100;
267 pll_val = pll_data->pll_1000;
276 static void ar71xx_set_pll_ge0(int speed)
278 u32 val = ar71xx_get_eth_pll(0, speed);
280 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
281 val, AR71XX_ETH0_PLL_SHIFT);
284 static void ar71xx_set_pll_ge1(int speed)
286 u32 val = ar71xx_get_eth_pll(1, speed);
288 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
289 val, AR71XX_ETH1_PLL_SHIFT);
292 static void ar724x_set_pll_ge0(int speed)
297 static void ar724x_set_pll_ge1(int speed)
302 static void ar91xx_set_pll_ge0(int speed)
304 u32 val = ar71xx_get_eth_pll(0, speed);
306 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR91XX_ETH0_PLL_SHIFT);
310 static void ar91xx_set_pll_ge1(int speed)
312 u32 val = ar71xx_get_eth_pll(1, speed);
314 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
315 val, AR91XX_ETH1_PLL_SHIFT);
318 static void ar71xx_ddr_flush_ge0(void)
320 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
323 static void ar71xx_ddr_flush_ge1(void)
325 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
328 static void ar724x_ddr_flush_ge0(void)
330 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
333 static void ar724x_ddr_flush_ge1(void)
335 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
338 static void ar91xx_ddr_flush_ge0(void)
340 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
343 static void ar91xx_ddr_flush_ge1(void)
345 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
348 static struct resource ar71xx_eth0_resources[] = {
351 .flags = IORESOURCE_MEM,
352 .start = AR71XX_GE0_BASE,
353 .end = AR71XX_GE0_BASE + 0x20 - 1,
356 .flags = IORESOURCE_MEM,
357 .start = AR71XX_GE0_BASE + 0x38,
358 .end = AR71XX_GE0_BASE + 0x200 - 1,
361 .flags = IORESOURCE_MEM,
362 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
363 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
366 .flags = IORESOURCE_IRQ,
367 .start = AR71XX_CPU_IRQ_GE0,
368 .end = AR71XX_CPU_IRQ_GE0,
372 struct ag71xx_platform_data ar71xx_eth0_data = {
373 .reset_bit = RESET_MODULE_GE0_MAC,
376 static struct platform_device ar71xx_eth0_device = {
379 .resource = ar71xx_eth0_resources,
380 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
382 .platform_data = &ar71xx_eth0_data,
386 static struct resource ar71xx_eth1_resources[] = {
389 .flags = IORESOURCE_MEM,
390 .start = AR71XX_GE1_BASE,
391 .end = AR71XX_GE1_BASE + 0x20 - 1,
394 .flags = IORESOURCE_MEM,
395 .start = AR71XX_GE1_BASE + 0x38,
396 .end = AR71XX_GE1_BASE + 0x200 - 1,
399 .flags = IORESOURCE_MEM,
400 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
401 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
404 .flags = IORESOURCE_IRQ,
405 .start = AR71XX_CPU_IRQ_GE1,
406 .end = AR71XX_CPU_IRQ_GE1,
410 struct ag71xx_platform_data ar71xx_eth1_data = {
411 .reset_bit = RESET_MODULE_GE1_MAC,
414 static struct platform_device ar71xx_eth1_device = {
417 .resource = ar71xx_eth1_resources,
418 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
420 .platform_data = &ar71xx_eth1_data,
424 #define AR71XX_PLL_VAL_1000 0x00110000
425 #define AR71XX_PLL_VAL_100 0x00001099
426 #define AR71XX_PLL_VAL_10 0x00991099
428 #define AR724X_PLL_VAL_1000 0x00110000
429 #define AR724X_PLL_VAL_100 0x00001099
430 #define AR724X_PLL_VAL_10 0x00991099
432 #define AR91XX_PLL_VAL_1000 0x1a000000
433 #define AR91XX_PLL_VAL_100 0x13000a44
434 #define AR91XX_PLL_VAL_10 0x00441099
436 static void __init ar71xx_init_eth_pll_data(unsigned int id)
438 struct ar71xx_eth_pll_data *pll_data;
439 u32 pll_10, pll_100, pll_1000;
443 pll_data = &ar71xx_eth0_pll_data;
446 pll_data = &ar71xx_eth1_pll_data;
452 switch (ar71xx_soc) {
453 case AR71XX_SOC_AR7130:
454 case AR71XX_SOC_AR7141:
455 case AR71XX_SOC_AR7161:
456 pll_10 = AR71XX_PLL_VAL_10;
457 pll_100 = AR71XX_PLL_VAL_100;
458 pll_1000 = AR71XX_PLL_VAL_1000;
461 case AR71XX_SOC_AR7240:
462 pll_10 = AR724X_PLL_VAL_10;
463 pll_100 = AR724X_PLL_VAL_100;
464 pll_1000 = AR724X_PLL_VAL_1000;
467 case AR71XX_SOC_AR9130:
468 case AR71XX_SOC_AR9132:
469 pll_10 = AR91XX_PLL_VAL_10;
470 pll_100 = AR91XX_PLL_VAL_100;
471 pll_1000 = AR91XX_PLL_VAL_1000;
477 if (!pll_data->pll_10)
478 pll_data->pll_10 = pll_10;
480 if (!pll_data->pll_100)
481 pll_data->pll_100 = pll_100;
483 if (!pll_data->pll_1000)
484 pll_data->pll_1000 = pll_1000;
487 static int ar71xx_eth_instance __initdata;
488 void __init ar71xx_add_device_eth(unsigned int id)
490 struct platform_device *pdev;
491 struct ag71xx_platform_data *pdata;
493 ar71xx_init_eth_pll_data(id);
497 switch (ar71xx_eth0_data.phy_if_mode) {
498 case PHY_INTERFACE_MODE_MII:
499 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
501 case PHY_INTERFACE_MODE_GMII:
502 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
504 case PHY_INTERFACE_MODE_RGMII:
505 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
507 case PHY_INTERFACE_MODE_RMII:
508 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
511 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
515 pdev = &ar71xx_eth0_device;
518 switch (ar71xx_eth1_data.phy_if_mode) {
519 case PHY_INTERFACE_MODE_RMII:
520 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
522 case PHY_INTERFACE_MODE_RGMII:
523 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
526 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
530 pdev = &ar71xx_eth1_device;
533 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
537 pdata = pdev->dev.platform_data;
539 switch (ar71xx_soc) {
540 case AR71XX_SOC_AR7130:
541 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
542 : ar71xx_ddr_flush_ge0;
543 pdata->set_pll = id ? ar71xx_set_pll_ge1
544 : ar71xx_set_pll_ge0;
547 case AR71XX_SOC_AR7141:
548 case AR71XX_SOC_AR7161:
549 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
550 : ar71xx_ddr_flush_ge0;
551 pdata->set_pll = id ? ar71xx_set_pll_ge1
552 : ar71xx_set_pll_ge0;
556 case AR71XX_SOC_AR7240:
557 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
558 : ar724x_ddr_flush_ge0;
559 pdata->set_pll = id ? ar724x_set_pll_ge1
560 : ar724x_set_pll_ge0;
561 pdata->is_ar724x = 1;
564 case AR71XX_SOC_AR9130:
565 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
566 : ar91xx_ddr_flush_ge0;
567 pdata->set_pll = id ? ar91xx_set_pll_ge1
568 : ar91xx_set_pll_ge0;
569 pdata->is_ar91xx = 1;
572 case AR71XX_SOC_AR9132:
573 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
574 : ar91xx_ddr_flush_ge0;
575 pdata->set_pll = id ? ar91xx_set_pll_ge1
576 : ar91xx_set_pll_ge0;
577 pdata->is_ar91xx = 1;
585 switch (pdata->phy_if_mode) {
586 case PHY_INTERFACE_MODE_GMII:
587 case PHY_INTERFACE_MODE_RGMII:
588 if (!pdata->has_gbit) {
589 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
598 if (is_valid_ether_addr(ar71xx_mac_base)) {
599 memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN);
600 pdata->mac_addr[5] += ar71xx_eth_instance;
602 random_ether_addr(pdata->mac_addr);
604 "ar71xx: using random MAC address for eth%d\n",
605 ar71xx_eth_instance);
608 platform_device_register(pdev);
609 ar71xx_eth_instance++;
612 static struct resource ar71xx_spi_resources[] = {
614 .start = AR71XX_SPI_BASE,
615 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
616 .flags = IORESOURCE_MEM,
620 static struct platform_device ar71xx_spi_device = {
621 .name = "ar71xx-spi",
623 .resource = ar71xx_spi_resources,
624 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
627 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
628 struct spi_board_info const *info,
631 spi_register_board_info(info, n);
632 ar71xx_spi_device.dev.platform_data = pdata;
633 platform_device_register(&ar71xx_spi_device);
636 void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds,
637 struct gpio_led *leds)
639 struct platform_device *pdev;
640 struct gpio_led_platform_data pdata;
644 p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
648 memcpy(p, leds, num_leds * sizeof(*p));
650 pdev = platform_device_alloc("leds-gpio", id);
654 memset(&pdata, 0, sizeof(pdata));
655 pdata.num_leds = num_leds;
658 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
662 err = platform_device_add(pdev);
669 platform_device_put(pdev);
675 void __init ar71xx_add_device_gpio_buttons(int id,
676 unsigned poll_interval,
678 struct gpio_button *buttons)
680 struct platform_device *pdev;
681 struct gpio_buttons_platform_data pdata;
682 struct gpio_button *p;
685 p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
689 memcpy(p, buttons, nbuttons * sizeof(*p));
691 pdev = platform_device_alloc("gpio-buttons", id);
693 goto err_free_buttons;
695 memset(&pdata, 0, sizeof(pdata));
696 pdata.poll_interval = poll_interval;
697 pdata.nbuttons = nbuttons;
700 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
705 err = platform_device_add(pdev);
712 platform_device_put(pdev);
718 void __init ar71xx_add_device_wdt(void)
720 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
723 void __init ar71xx_set_mac_base(unsigned char *mac)
725 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
728 void __init ar71xx_parse_mac_addr(char *mac_str)
733 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
734 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
737 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
738 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
741 ar71xx_set_mac_base(tmp);
743 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
744 "\"%s\"\n", mac_str);
747 static struct resource ar91xx_wmac_resources[] = {
749 .start = AR91XX_WMAC_BASE,
750 .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1,
751 .flags = IORESOURCE_MEM,
753 .start = AR71XX_CPU_IRQ_WMAC,
754 .end = AR71XX_CPU_IRQ_WMAC,
755 .flags = IORESOURCE_IRQ,
759 static struct ath9k_platform_data ar91xx_wmac_data;
761 static struct platform_device ar91xx_wmac_device = {
764 .resource = ar91xx_wmac_resources,
765 .num_resources = ARRAY_SIZE(ar91xx_wmac_resources),
767 .platform_data = &ar91xx_wmac_data,
771 void __init ar91xx_add_device_wmac(void)
773 u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
775 memcpy(ar91xx_wmac_data.eeprom_data, ee,
776 sizeof(ar91xx_wmac_data.eeprom_data));
778 ar71xx_device_stop(RESET_MODULE_AMBA2WMAC);
781 ar71xx_device_start(RESET_MODULE_AMBA2WMAC);
784 platform_device_register(&ar91xx_wmac_device);
787 static struct platform_device ar71xx_dsa_switch_device = {
792 void __init ar71xx_add_device_dsa(unsigned int id,
793 struct dsa_platform_data *d)
797 d->netdev = &ar71xx_eth0_device.dev;
800 d->netdev = &ar71xx_eth1_device.dev;
804 "ar71xx: invalid ethernet id %d for DSA switch\n",
808 d->mii_bus = &ar71xx_mdio_device.dev;
809 ar71xx_dsa_switch_device.dev.platform_data = d;
811 platform_device_register(&ar71xx_dsa_switch_device);