target/linux/ar7/patches-2.6.32/972-cpmac_multi_probe.patch

   1 Index: linux-2.6.32.26/arch/mips/ar7/platform.c
   2 ===================================================================
   3 --- linux-2.6.32.26.orig/arch/mips/ar7/platform.c       2010-11-28 03:22:24.522383766 -0800
   4 +++ linux-2.6.32.26/arch/mips/ar7/platform.c    2010-11-28 04:17:24.872413302 -0800
   5 @@ -46,7 +46,6 @@
   6         int reset_bit;
   7  };
   8
   9 -
  10  static int vlynq_on(struct vlynq_device *dev)
  11  {
  12         int result;
  13 @@ -72,7 +71,8 @@
  14
  15         msleep(50);
  16
  17 -       gpio_set_value(pdata->gpio_bit, 1);
  18 +       gpio_set_value(pdata->gpio_bit,
  19 +                       __vlynq_rev_reg(dev->local) < 0x00010205);
  20         msleep(50);
  21
  22         return 0;
  23 @@ -601,6 +601,18 @@
  24         }
  25  }
  26
  27 +static void auto_mdix_on(void)
  28 +{
  29 +       ar7_gpio_enable(28);
  30 +       ar7_gpio_disable(30);
  31 +}
  32 +
  33 +/*static void auto_mdix_off(void)
  34 +{
  35 +       ar7_gpio_disable(28);
  36 +       ar7_gpio_disable(30);
  37 +}*/
  38 +
  39  static void cpmac_get_mac(int instance, unsigned char *dev_addr)
  40  {
  41         int i;
  42 @@ -662,6 +674,7 @@
  43         u16 chip_id;
  44         int res;
  45         u32 *bootcr, val;
  46 +       void __iomem *mii_reg;
  47  #ifdef CONFIG_SERIAL_8250
  48         static struct uart_port uart_port[2];
  49
  50 @@ -715,27 +728,6 @@
  51                         return res;
  52         }
  53
  54 -       if (ar7_has_high_cpmac()) {
  55 -               res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_high_titan.id : cpmac_high.id,
  56 -                                               &fixed_phy_status);
  57 -               if (res && res != -ENODEV)
  58 -                       return res;
  59 -
  60 -               cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr :
  61 -                                               cpmac_high_data.dev_addr);
  62 -               res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan :
  63 -                                               &cpmac_high);
  64 -
  65 -               if (res)
  66 -                       return res;
  67 -       } else {
  68 -               if (ar7_is_titan())
  69 -                       cpmac_low_data_titan.phy_mask = 0xffffffff;
  70 -               else
  71 -                       cpmac_low_data.phy_mask = 0xffffffff;
  72 -
  73 -       }
  74 -
  75         res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_low_titan.id :
  76                         cpmac_low.id, &fixed_phy_status);
  77         if (res && res != -ENODEV)
  78 @@ -748,6 +740,34 @@
  79         if (res)
  80                 return res;
  81
  82 +       if (ar7_has_high_cpmac()) {
  83 +               res = fixed_phy_add(PHY_POLL, ar7_is_titan() ?
  84 +                               cpmac_high_titan.id : cpmac_high.id,
  85 +                               &fixed_phy_status);
  86 +               if (res && res != -ENODEV)
  87 +                       return res;
  88 +
  89 +               cpmac_get_mac(1, ar7_is_titan() ?
  90 +                               cpmac_high_data_titan.dev_addr :
  91 +                               cpmac_high_data.dev_addr);
  92 +               res = platform_device_register(ar7_is_titan() ?
  93 +                               &cpmac_high_titan : &cpmac_high);
  94 +
  95 +               if (res)
  96 +                       return res;
  97 +       } else {
  98 +               mii_reg = ioremap(AR7_REGS_MII, 4);
  99 +               if (mii_reg) {
 100 +                       writel(readl(mii_reg) | 1, mii_reg);
 101 +                       iounmap(mii_reg);
 102 +               }
 103 +
 104 +               ar7_gpio_disable(17);
 105 +               mdelay(20);
 106 +               ar7_gpio_enable(17);
 107 +               auto_mdix_on();
 108 +       }
 109 +
 110         detect_leds();
 111         res = platform_device_register(&ar7_gpio_leds);
 112         if (res)
 113 @@ -771,8 +791,10 @@
 114         ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
 115
 116         bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 117 -       val = *bootcr;
 118 -       iounmap(bootcr);
 119 +       if (bootcr) {
 120 +               val = *bootcr;
 121 +               iounmap(bootcr);
 122 +       }
 123
 124         /* Register watchdog only if enabled in hardware */
 125         if (val & AR7_WDT_HW_ENA)
 126 Index: linux-2.6.32.26/arch/mips/include/asm/mach-ar7/ar7.h
 127 ===================================================================
 128 --- linux-2.6.32.26.orig/arch/mips/include/asm/mach-ar7/ar7.h   2010-11-28 03:22:24.522383766 -0800
 129 +++ linux-2.6.32.26/arch/mips/include/asm/mach-ar7/ar7.h        2010-11-28 03:22:25.012385426 -0800
 130 @@ -41,6 +41,7 @@
 131  #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
 132  #define AR7_REGS_VLYNQ0        (AR7_REGS_BASE + 0x1800)
 133  #define AR7_REGS_DCL   (AR7_REGS_BASE + 0x1a00)
 134 +#define AR7_REGS_MII   (AR7_REGS_BASE + 0x1a08)
 135  #define AR7_REGS_VLYNQ1        (AR7_REGS_BASE + 0x1c00)
 136  #define AR7_REGS_MDIO  (AR7_REGS_BASE + 0x1e00)
 137  #define AR7_REGS_IRQ   (AR7_REGS_BASE + 0x2400)
 138 Index: linux-2.6.32.26/drivers/net/cpmac.c
 139 ===================================================================
 140 --- linux-2.6.32.26.orig/drivers/net/cpmac.c    2010-11-28 03:22:24.982383427 -0800
 141 +++ linux-2.6.32.26/drivers/net/cpmac.c 2010-11-28 05:23:59.482390691 -0800
 142 @@ -668,9 +668,8 @@
 143         for (i = 0; i < 8; i++)
 144                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 145         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 146 -       cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 147 -                   (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 148 -                   (dev->dev_addr[3] << 24));
 149 +       cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, be32_to_cpu(*(u32 *)
 150 +                       dev->dev_addr));
 151         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 152         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 153         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 154 @@ -1104,8 +1103,6 @@
 155         .ndo_set_mac_address    = eth_mac_addr,
 156  };
 157
 158 -static int external_switch;
 159 -
 160  static int __devinit cpmac_probe(struct platform_device *pdev)
 161  {
 162         int rc, phy_id;
 163 @@ -1117,24 +1114,26 @@
 164
 165         pdata = pdev->dev.platform_data;
 166
 167 -       if (external_switch || dumb_switch) {
 168 -               strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
 169 -               phy_id = pdev->id;
 170 -       } else {
 171 -               for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
 172 -                       if (!(pdata->phy_mask & (1 << phy_id)))
 173 -                               continue;
 174 -                       if (!cpmac_mii->phy_map[phy_id])
 175 -                               continue;
 176 -                       strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
 177 -                       break;
 178 -               }
 179 +       if (dumb_switch)
 180 +               phy_id = PHY_MAX_ADDR;
 181 +       else for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
 182 +               if (!((pdata->phy_mask | cpmac_mii->phy_mask) &
 183 +                               (1 << phy_id)))
 184 +                       continue;
 185 +               if (cpmac_mii->phy_map[phy_id])
 186 +                       continue;
 187 +               strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
 188 +               break;
 189         }
 190
 191         if (phy_id == PHY_MAX_ADDR) {
 192                 dev_err(&pdev->dev, "no PHY present, falling back to switch mode\n");
 193                 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
 194                 phy_id = pdev->id;
 195 +       } else {
 196 +               /* Now disable EPHY and enable MII */
 197 +               dev_info(&pdev->dev, "trying external MII\n");
 198 +               ar7_device_disable(AR7_RESET_BIT_EPHY);
 199         }
 200
 201         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
 202 @@ -1168,7 +1167,7 @@
 203         priv->dev = dev;
 204         priv->ring_size = 64;
 205         priv->msg_enable = netif_msg_init(debug_level, 0xff);
 206 -       memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
 207 +       memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
 208
 209         snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
 210
 211 @@ -1244,14 +1243,14 @@
 212         ar7_gpio_disable(26);
 213         ar7_gpio_disable(27);
 214
 215 -       if (!ar7_is_titan()) {
 216 +       if (ar7_is_titan()) {
 217 +               ar7_device_reset(AR7_RESET_BIT_EPHY);
 218 +               ar7_device_reset(TITAN_RESET_BIT_EPHY1);
 219 +       } else {
 220                 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
 221                 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
 222 -       }
 223 -       ar7_device_reset(AR7_RESET_BIT_EPHY);
 224
 225 -       if (ar7_is_titan()) {
 226 -               ar7_device_reset(TITAN_RESET_BIT_EPHY1);
 227 +               ar7_device_reset(AR7_RESET_BIT_EPHY);
 228         }
 229
 230         cpmac_mii->reset(cpmac_mii);
 231 @@ -1262,14 +1261,7 @@
 232                 else
 233                         msleep(10);
 234
 235 -       mask &= 0x7fffffff;
 236 -       if (mask & (mask - 1)) {
 237 -               external_switch = 1;
 238 -               mask = 0;
 239 -       }
 240 -
 241 -       cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000):
 242 -               ~(mask | 0x80000000);
 243 +       cpmac_mii->phy_mask = ~mask;
 244         snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
 245
 246         res = mdiobus_register(cpmac_mii);