target/linux/ar7/patches-2.6.23/100-board_support.patch

   1 Index: linux-2.6.23-rc6/arch/mips/Kconfig
   2 ===================================================================
   3 --- linux-2.6.23-rc6.orig/arch/mips/Kconfig     2007-09-21 16:23:51.000000000 +0800
   4 +++ linux-2.6.23-rc6/arch/mips/Kconfig  2007-09-21 16:24:11.000000000 +0800
   5 @@ -15,6 +15,23 @@
   6         prompt "System type"
   7         default SGI_IP22
   8
   9 +config AR7
  10 +       bool "Texas Instruments AR7"
  11 +       select BOOT_ELF32
  12 +       select DMA_NONCOHERENT
  13 +       select HW_HAS_PCI
  14 +       select IRQ_CPU
  15 +       select NO_EXCEPT_FILL
  16 +       select SWAP_IO_SPACE
  17 +       select SYS_HAS_CPU_MIPS32_R1
  18 +       select SYS_HAS_EARLY_PRINTK
  19 +       select SYS_SUPPORTS_32BIT_KERNEL
  20 +       select SYS_SUPPORTS_KGDB
  21 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  22 +       select SYS_SUPPORTS_BIG_ENDIAN
  23 +       select GENERIC_GPIO
  24 +       select GENERIC_HARDIRQS_NO__DO_IRQ
  25 +
  26  config MACH_ALCHEMY
  27         bool "Alchemy processor based machines"
  28
  29 Index: linux-2.6.23-rc6/arch/mips/kernel/traps.c
  30 ===================================================================
  31 --- linux-2.6.23-rc6.orig/arch/mips/kernel/traps.c      2007-09-21 16:23:51.000000000 +0800
  32 +++ linux-2.6.23-rc6/arch/mips/kernel/traps.c   2007-09-21 16:24:11.000000000 +0800
  33 @@ -1075,10 +1075,23 @@
  34
  35         exception_handlers[n] = handler;
  36         if (n == 0 && cpu_has_divec) {
  37 -               *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
  38 -                                                (0x03ffffff & (handler >> 2));
  39 -               flush_icache_range(ebase + 0x200, ebase + 0x204);
  40 -       }
  41 +               if ((handler ^ (ebase + 4)) & 0xfc000000) {
  42 +                       /* lui k0, 0x0000 */
  43 +                       *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
  44 +                       /* ori k0, 0x0000 */
  45 +                       *(u32 *)(ebase + 0x204) =
  46 +                                       0x375a0000 | (handler & 0xffff);
  47 +                       /* jr k0 */
  48 +                       *(u32 *)(ebase + 0x208) = 0x03400008;
  49 +                       /* nop */
  50 +                       *(u32 *)(ebase + 0x20C) = 0x00000000;
  51 +                       flush_icache_range(ebase + 0x200, ebase + 0x210);
  52 +               } else {
  53 +                       *(volatile u32 *)(ebase + 0x200) =
  54 +                               0x08000000 | (0x03ffffff & (handler >> 2));
  55 +                       flush_icache_range(ebase + 0x200, ebase + 0x204);
  56 +               }
  57 +       }
  58         return (void *)old_handler;
  59  }
  60
  61 Index: linux-2.6.23-rc6/arch/mips/Makefile
  62 ===================================================================
  63 --- linux-2.6.23-rc6.orig/arch/mips/Makefile    2007-09-21 16:24:05.000000000 +0800
  64 +++ linux-2.6.23-rc6/arch/mips/Makefile 2007-09-21 16:24:11.000000000 +0800
  65 @@ -161,6 +161,13 @@
  66  #
  67
  68  #
  69 +# Texas Instruments AR7
  70 +#
  71 +core-$(CONFIG_AR7)             += arch/mips/ar7/
  72 +cflags-$(CONFIG_AR7)           += -Iinclude/asm-mips/ar7
  73 +load-$(CONFIG_AR7)             += 0xffffffff94100000
  74 +
  75 +#
  76  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  77  #
  78  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  79 Index: linux-2.6.23-rc6/include/asm-mips/page.h
  80 ===================================================================
  81 --- linux-2.6.23-rc6.orig/include/asm-mips/page.h       2007-09-21 16:23:51.000000000 +0800
  82 +++ linux-2.6.23-rc6/include/asm-mips/page.h    2007-09-21 16:24:11.000000000 +0800
  83 @@ -184,8 +184,10 @@
  84  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  85                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  86
  87 -#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE)
  88 -#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET)
  89 +#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
  90 +                                PHYS_OFFSET)
  91 +#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
  92 +                                PHYS_OFFSET)
  93
  94  #include <asm-generic/memory_model.h>
  95  #include <asm-generic/page.h>