2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <asm/addrspace.h>
26 #include <asm/ar7/ar7.h>
28 #define BOOT_PLL_SOURCE_MASK 0x3
29 #define CPU_PLL_SOURCE_SHIFT 16
30 #define BUS_PLL_SOURCE_SHIFT 14
31 #define USB_PLL_SOURCE_SHIFT 18
32 #define DSP_PLL_SOURCE_SHIFT 22
33 #define BOOT_PLL_SOURCE_AFE 0
34 #define BOOT_PLL_SOURCE_BUS 0
35 #define BOOT_PLL_SOURCE_REF 1
36 #define BOOT_PLL_SOURCE_XTAL 2
37 #define BOOT_PLL_SOURCE_CPU 3
38 #define BOOT_PLL_BYPASS 0x00000020
39 #define BOOT_PLL_ASYNC_MODE 0x02000000
40 #define BOOT_PLL_2TO1_MODE 0x00008000
42 #define TNETD7200_CLOCK_ID_CPU 0
43 #define TNETD7200_CLOCK_ID_DSP 1
44 #define TNETD7200_CLOCK_ID_USB 2
46 #define TNETD7200_DEF_CPU_CLK 211000000
47 #define TNETD7200_DEF_DSP_CLK 125000000
48 #define TNETD7200_DEF_USB_CLK 48000000
50 struct tnetd7300_clock {
52 #define PREDIV_MASK 0x001f0000
53 #define PREDIV_SHIFT 16
54 #define POSTDIV_MASK 0x0000001f
57 #define MUL_MASK 0x0000f000
59 #define PLL_MODE_MASK 0x00000001
60 #define PLL_NDIV 0x00000800
61 #define PLL_DIV 0x00000002
62 #define PLL_STATUS 0x00000001
66 struct tnetd7300_clocks {
67 struct tnetd7300_clock bus;
68 struct tnetd7300_clock cpu;
69 struct tnetd7300_clock usb;
70 struct tnetd7300_clock dsp;
73 struct tnetd7200_clock {
76 #define DIVISOR_ENABLE_MASK 0x00008000
88 struct tnetd7200_clocks {
89 struct tnetd7200_clock cpu;
90 struct tnetd7200_clock dsp;
91 struct tnetd7200_clock usb;
94 int ar7_cpu_clock = 150000000;
95 EXPORT_SYMBOL(ar7_cpu_clock);
96 int ar7_bus_clock = 125000000;
97 EXPORT_SYMBOL(ar7_bus_clock);
99 EXPORT_SYMBOL(ar7_dsp_clock);
101 static int gcd(int a, int b)
110 while ((c = (a % b))) {
117 static void approximate(int base, int target, int *prediv,
118 int *postdiv, int *mul)
120 int i, j, k, freq, res = target;
121 for (i = 1; i <= 16; i++)
122 for (j = 1; j <= 32; j++)
123 for (k = 1; k <= 32; k++) {
124 freq = abs(base / j * i / k - target);
134 static void calculate(int base, int target, int *prediv, int *postdiv,
137 int tmp_gcd, tmp_base, tmp_freq;
139 for (*prediv = 1; *prediv <= 32; (*prediv)++) {
140 tmp_base = base / *prediv;
141 tmp_gcd = gcd(target, tmp_base);
142 *mul = target / tmp_gcd;
143 *postdiv = tmp_base / tmp_gcd;
144 if ((*mul < 1) || (*mul >= 16))
146 if ((*postdiv > 0) & (*postdiv <= 32))
150 if (base / (*prediv) * (*mul) / (*postdiv) != target) {
151 approximate(base, target, prediv, postdiv, mul);
152 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
154 "Adjusted requested frequency %d to %d\n",
158 printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
159 *prediv, *postdiv, *mul);
162 static int tnetd7300_dsp_clock(void)
165 u8 rev = ar7_chip_rev();
166 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
167 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
168 if (didr2 & (1 << 23))
170 if ((rev >= 0x23) && (rev != 0x57))
172 if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
178 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
179 u32 *bootcr, u32 bus_clock)
182 int base_clock = AR7_REF_CLOCK;
183 u32 ctrl = readl(&clock->ctrl);
184 u32 pll = readl(&clock->pll);
185 int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
186 int postdiv = (ctrl & POSTDIV_MASK) + 1;
187 int divisor = prediv * postdiv;
188 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
190 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
191 case BOOT_PLL_SOURCE_BUS:
192 base_clock = bus_clock;
194 case BOOT_PLL_SOURCE_REF:
195 base_clock = AR7_REF_CLOCK;
197 case BOOT_PLL_SOURCE_XTAL:
198 base_clock = AR7_XTAL_CLOCK;
200 case BOOT_PLL_SOURCE_CPU:
201 base_clock = ar7_cpu_clock;
205 if (*bootcr & BOOT_PLL_BYPASS)
206 return base_clock / divisor;
208 if ((pll & PLL_MODE_MASK) == 0)
209 return (base_clock >> (mul / 16 + 1)) / divisor;
211 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
212 product = (mul & 1) ?
213 (base_clock * mul) >> 1 :
214 (base_clock * (mul - 1)) >> 2;
215 return product / divisor;
219 return base_clock / divisor;
221 return base_clock * mul / divisor;
224 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
225 u32 *bootcr, u32 frequency)
227 int prediv, postdiv, mul;
228 int base_clock = ar7_bus_clock;
230 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
231 case BOOT_PLL_SOURCE_BUS:
232 base_clock = ar7_bus_clock;
234 case BOOT_PLL_SOURCE_REF:
235 base_clock = AR7_REF_CLOCK;
237 case BOOT_PLL_SOURCE_XTAL:
238 base_clock = AR7_XTAL_CLOCK;
240 case BOOT_PLL_SOURCE_CPU:
241 base_clock = ar7_cpu_clock;
245 calculate(base_clock, frequency, &prediv, &postdiv, &mul);
247 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
249 writel(4, &clock->pll);
250 while (readl(&clock->pll) & PLL_STATUS);
251 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
255 static void __init tnetd7300_init_clocks(void)
257 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
258 struct tnetd7300_clocks *clocks =
259 (struct tnetd7300_clocks *)
260 ioremap_nocache(AR7_REGS_POWER + 0x20,
261 sizeof(struct tnetd7300_clocks));
263 ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
264 &clocks->bus, bootcr, AR7_AFE_CLOCK);
266 if (*bootcr & BOOT_PLL_ASYNC_MODE)
267 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
268 &clocks->cpu, bootcr, AR7_AFE_CLOCK);
270 ar7_cpu_clock = ar7_bus_clock;
272 tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
275 if (ar7_dsp_clock == 250000000)
276 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
277 bootcr, ar7_dsp_clock);
283 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
284 u32 *bootcr, u32 bus_clock)
286 int divisor = ((readl(&clock->prediv) & 0x1f) + 1) *
287 ((readl(&clock->postdiv) & 0x1f) + 1);
289 if (*bootcr & BOOT_PLL_BYPASS)
290 return base / divisor;
292 return base * ((readl(&clock->mul) & 0xf) + 1) / divisor;
296 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
297 int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
300 "Clocks: base = %d, frequency = %u, prediv = %d, "
301 "postdiv = %d, postdiv2 = %d, mul = %d\n",
302 base, frequency, prediv, postdiv, postdiv2, mul);
304 writel(0, &clock->ctrl);
305 writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
306 writel((mul - 1) & 0xF, &clock->mul);
308 for (mul = 0; mul < 2000; mul++) /* nop */;
310 while (readl(&clock->status) & 0x1) /* nop */;
312 writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
314 writel(readl(&clock->cmden) | 1, &clock->cmden);
315 writel(readl(&clock->cmd) | 1, &clock->cmd);
317 while (readl(&clock->status) & 0x1) /* nop */;
319 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
321 writel(readl(&clock->cmden) | 1, &clock->cmden);
322 writel(readl(&clock->cmd) | 1, &clock->cmd);
324 while (readl(&clock->status) & 0x1) /* nop */;
326 writel(readl(&clock->ctrl) | 1, &clock->ctrl);
329 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
331 if (*bootcr & BOOT_PLL_ASYNC_MODE)
334 case TNETD7200_CLOCK_ID_DSP:
335 return AR7_REF_CLOCK;
337 return AR7_AFE_CLOCK;
341 if (*bootcr & BOOT_PLL_2TO1_MODE)
344 case TNETD7200_CLOCK_ID_DSP:
345 return AR7_REF_CLOCK;
347 return AR7_AFE_CLOCK;
351 return AR7_REF_CLOCK;
355 static void __init tnetd7200_init_clocks(void)
357 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
358 struct tnetd7200_clocks *clocks =
359 (struct tnetd7200_clocks *)
360 ioremap_nocache(AR7_REGS_POWER + 0x80,
361 sizeof(struct tnetd7200_clocks));
362 int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
363 int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
364 int usb_base, usb_mul, usb_prediv, usb_postdiv;
367 Log from Fritz!Box 7170 Annex B:
369 CPU revision is: 00018448
371 Clocks: Setting DSP clock
372 Clocks: prediv: 1, postdiv: 1, mul: 5
373 Clocks: base = 25000000, frequency = 125000000, prediv = 1,
374 postdiv = 2, postdiv2 = 1, mul = 10
375 Clocks: Setting CPU clock
376 Adjusted requested frequency 211000000 to 211968000
377 Clocks: prediv: 1, postdiv: 1, mul: 6
378 Clocks: base = 35328000, frequency = 211968000, prediv = 1,
379 postdiv = 1, postdiv2 = -1, mul = 6
380 Clocks: Setting USB clock
381 Adjusted requested frequency 48000000 to 48076920
382 Clocks: prediv: 13, postdiv: 1, mul: 5
383 Clocks: base = 125000000, frequency = 48000000, prediv = 13,
384 postdiv = 1, postdiv2 = -1, mul = 5
386 DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination,
387 driver hung on startup.
388 Haven't tested this on a synchronous board,
389 neither do i know what to do with ar7_dsp_clock
392 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
393 dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
395 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
396 printk(KERN_INFO "Clocks: Async mode\n");
398 printk(KERN_INFO "Clocks: Setting DSP clock\n");
399 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
400 &dsp_prediv, &dsp_postdiv, &dsp_mul);
402 ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
403 tnetd7200_set_clock(dsp_base, &clocks->dsp,
404 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
407 printk(KERN_INFO "Clocks: Setting CPU clock\n");
408 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
409 &cpu_postdiv, &cpu_mul);
411 ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
412 tnetd7200_set_clock(cpu_base, &clocks->cpu,
413 cpu_prediv, cpu_postdiv, -1, cpu_mul,
417 if (*bootcr & BOOT_PLL_2TO1_MODE) {
418 printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
420 printk(KERN_INFO "Clocks: Setting CPU clock\n");
421 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
422 &cpu_postdiv, &cpu_mul);
423 ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
425 tnetd7200_set_clock(cpu_base, &clocks->cpu,
426 cpu_prediv, cpu_postdiv, -1, cpu_mul,
429 printk(KERN_INFO "Clocks: Setting DSP clock\n");
430 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
431 &dsp_postdiv, &dsp_mul);
432 ar7_bus_clock = ar7_cpu_clock / 2;
433 tnetd7200_set_clock(dsp_base, &clocks->dsp,
434 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
435 dsp_mul * 2, ar7_bus_clock);
437 printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
439 printk(KERN_INFO "Clocks: Setting DSP clock\n");
440 calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv,
441 &dsp_postdiv, &dsp_mul);
442 ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
444 tnetd7200_set_clock(dsp_base, &clocks->dsp,
445 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
446 dsp_mul * 2, ar7_bus_clock);
448 ar7_cpu_clock = ar7_bus_clock;
451 printk(KERN_INFO "Clocks: Setting USB clock\n");
452 usb_base = ar7_bus_clock;
453 calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
454 &usb_postdiv, &usb_mul);
455 tnetd7200_set_clock(usb_base, &clocks->usb,
456 usb_prediv, usb_postdiv, -1, usb_mul,
457 TNETD7200_DEF_USB_CLK);
460 ar7_dsp_clock = ar7_cpu_clock;
466 void __init ar7_init_clocks(void)
468 switch (ar7_chip_id()) {
470 #warning FIXME: Check if the new 7200 clock init works for 7100
471 tnetd7200_init_clocks();
474 tnetd7200_init_clocks();
477 ar7_dsp_clock = tnetd7300_dsp_clock();
478 tnetd7300_init_clocks();