2 * Defines for ADM5120 built in ethernet switch driver
4 * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
6 * Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
7 * Copyright ADMtek Inc.
10 #ifndef _INCLUDE_ADM5120SW_H_
11 #define _INCLUDE_ADM5120SW_H_
13 #define SW_BASE KSEG1ADDR(0x12000000)
17 #define ETH_TX_TIMEOUT HZ/4
20 #define ADM5120_CODE 0x00 /* CPU description */
21 #define ADM5120_CODE_PQFP 0x20000000 /* package type */
22 #define ADM5120_CPUP_CONF 0x24 /* CPU port config */
23 #define ADM5120_DISCCPUPORT 0x00000001 /* disable cpu port */
24 #define ADM5120_CRC_PADDING 0x00000002 /* software crc */
25 #define ADM5120_DISUNSHIFT 9
26 #define ADM5120_DISUNALL 0x00007e00 /* disable unknown from all */
27 #define ADM5120_DISMCSHIFT 16
28 #define ADM5120_DISMCALL 0x003f0000 /* disable multicast from all */
29 #define ADM5120_PORT_CONF0 0x28
30 #define ADM5120_ENMC 0x00003f00 /* Enable MC routing (ex cpu) */
31 #define ADM5120_ENBP 0x003f0000 /* Enable Back Pressure */
32 #define ADM5120_VLAN_GI 0x40 /* VLAN settings */
33 #define ADM5120_VLAN_GII 0x44
34 #define ADM5120_SEND_TRIG 0x48
35 #define ADM5120_SEND_TRIG_L 0x00000001
36 #define ADM5120_SEND_TRIG_H 0x00000002
37 #define ADM5120_MAC_WT0 0x58
38 #define ADM5120_MAC_WRITE 0x00000001
39 #define ADM5120_MAC_WRITE_DONE 0x00000002
40 #define ADM5120_VLAN_EN 0x00000040
41 #define ADM5120_MAC_WT1 0x5c
42 #define ADM5120_PHY_CNTL2 0x7c
43 #define ADM5120_AUTONEG 0x0000001f /* Auto negotiate */
44 #define ADM5120_NORMAL 0x01f00000 /* PHY normal mode */
45 #define ADM5120_AUTOMDIX 0x3e000000 /* Auto MDIX */
46 #define ADM5120_PHY_CNTL3 0x80
47 #define ADM5120_PHY_NTH 0x00000400
48 #define ADM5120_INT_ST 0xb0
49 #define ADM5120_INT_RXH 0x0000004
50 #define ADM5120_INT_RXL 0x0000008
51 #define ADM5120_INT_HFULL 0x0000010
52 #define ADM5120_INT_LFULL 0x0000020
53 #define ADM5120_INT_TXH 0x0000001
54 #define ADM5120_INT_TXL 0x0000002
55 #define ADM5120_INT_MASK 0xb4
56 #define ADM5120_INTMASKALL 0x1FDEFFF /* All interrupts */
57 #define ADM5120_INTHANDLE (ADM5120_INT_RXH | ADM5120_INT_RXL | \
58 ADM5120_INT_HFULL | ADM5120_INT_LFULL | \
59 ADM5120_INT_TXH | ADM5120_INT_TXL)
60 #define ADM5120_SEND_HBADDR 0xd0
61 #define ADM5120_SEND_LBADDR 0xd4
62 #define ADM5120_RECEIVE_HBADDR 0xd8
63 #define ADM5120_RECEIVE_LBADDR 0xdc
70 } __attribute__ ((packed));
72 #define ADM5120_DMA_MASK 0x00ffffff
73 #define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
74 #define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */
76 #define ADM5120_DMA_ADDR(ptr) ((u32)(ptr) & ADM5120_DMA_MASK)
77 #define ADM5120_DMA_PORTID 0x00007000
78 #define ADM5120_DMA_PORTSHIFT 12
79 #define ADM5120_DMA_LEN 0x07ff0000
80 #define ADM5120_DMA_LENSHIFT 16
81 #define ADM5120_DMA_FCSERR 0x00000008
83 #define ADM5120_DMA_TXH 16
84 #define ADM5120_DMA_TXL 64
85 #define ADM5120_DMA_RXH 16
86 #define ADM5120_DMA_RXL 8
88 #define ADM5120_DMA_RXSIZE 1550
89 #define ADM5120_DMA_EXTRA 20
93 struct net_device_stats stats;
96 #define SIOCSMATRIX SIOCDEVPRIVATE
97 #define SIOCGMATRIX SIOCDEVPRIVATE+1
98 #define SIOCGADMINFO SIOCDEVPRIVATE+2
100 struct adm5120_info {
106 #endif /* _INCLUDE_ADM5120SW_H_ */