2 * ADM5120 specific interrupt handlers
4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/version.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
20 #include <asm/irq_cpu.h>
21 #include <asm/mipsregs.h>
22 #include <asm/bitops.h>
24 #include <asm/mach-adm5120/adm5120_defs.h>
25 #include <asm/mach-adm5120/adm5120_irq.h>
27 static void adm5120_intc_irq_unmask(unsigned int irq);
28 static void adm5120_intc_irq_mask(unsigned int irq);
29 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
31 static inline void intc_write_reg(unsigned int reg, u32 val)
33 void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
35 __raw_writel(val, base + reg);
38 static inline u32 intc_read_reg(unsigned int reg)
40 void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
42 return __raw_readl(base + reg);
45 static struct irq_chip adm5120_intc_irq_chip = {
47 .unmask = adm5120_intc_irq_unmask,
48 .mask = adm5120_intc_irq_mask,
49 .mask_ack = adm5120_intc_irq_mask,
50 .set_type = adm5120_intc_irq_set_type
53 static struct irqaction adm5120_intc_irq_action = {
55 .name = "cascade [INTC]"
58 static void adm5120_intc_irq_unmask(unsigned int irq)
60 irq -= ADM5120_INTC_IRQ_BASE;
61 intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
64 static void adm5120_intc_irq_mask(unsigned int irq)
66 irq -= ADM5120_INTC_IRQ_BASE;
67 intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
70 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
76 sense = flow_type & (IRQ_TYPE_SENSE_MASK);
79 case IRQ_TYPE_LEVEL_HIGH:
81 case IRQ_TYPE_LEVEL_LOW:
83 case ADM5120_IRQ_GPIO2:
84 case ADM5120_IRQ_GPIO4:
100 case ADM5120_IRQ_GPIO2:
101 case ADM5120_IRQ_GPIO4:
102 mode = intc_read_reg(INTC_REG_INT_MODE);
103 if (sense == IRQ_TYPE_LEVEL_LOW)
104 mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
106 mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
108 intc_write_reg(INTC_REG_INT_MODE, mode);
111 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
112 irq_desc[irq].status |= sense;
119 static void adm5120_intc_irq_dispatch(void)
121 unsigned long status;
124 /* dispatch only one IRQ at a time */
125 status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
128 irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
131 spurious_interrupt();
134 asmlinkage void plat_irq_dispatch(void)
136 unsigned long pending;
138 pending = read_c0_status() & read_c0_cause() & ST0_IM;
140 if (pending & STATUSF_IP7)
141 do_IRQ(ADM5120_IRQ_COUNTER);
142 else if (pending & STATUSF_IP2)
143 adm5120_intc_irq_dispatch();
145 spurious_interrupt();
148 #define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
149 static void __init adm5120_intc_irq_init(void)
153 /* disable all interrupts */
154 intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
156 /* setup all interrupts to generate IRQ instead of FIQ */
157 intc_write_reg(INTC_REG_INT_MODE, 0);
159 /* set active level for all external interrupts to HIGH */
160 intc_write_reg(INTC_REG_INT_LEVEL, 0);
162 /* disable usage of the TEST_SOURCE register */
163 intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
165 for (i = ADM5120_INTC_IRQ_BASE;
166 i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
168 irq_desc[i].status = INTC_IRQ_STATUS;
169 set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
173 setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
176 void __init arch_init_irq(void) {
178 adm5120_intc_irq_init();