4 * ADM5120 PCI Host Controller driver
6 * Copyright (C) ADMtek Incorporated.
7 * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
8 * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
9 * Copyright (C) 2007 OpenWrt.org
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
24 * Boston, MA 02110-1301, USA.
27 #include <linux/types.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
32 #include <linux/pci.h>
33 #include <linux/pci_ids.h>
34 #include <linux/pci_regs.h>
37 #include <asm/delay.h>
38 #include <asm/bootinfo.h>
40 #include <adm5120_defs.h>
41 #include <adm5120_info.h>
42 #include <adm5120_defs.h>
43 #include <adm5120_platform.h>
48 #define DBG(f, a...) printk(KERN_DEBUG f, ## a )
50 #define DBG(f, a...) do {} while (0)
53 #define PCI_ENABLE 0x80000000
55 /* -------------------------------------------------------------------------*/
57 static unsigned int adm5120_pci_nr_irqs __initdata = 0;
58 static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata = NULL;
60 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
62 /* -------------------------------------------------------------------------*/
64 static inline void write_cfgaddr(u32 addr)
66 __raw_writel((addr | PCI_ENABLE),
67 (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
70 static inline void write_cfgdata(u32 data)
72 __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
75 static inline u32 read_cfgdata(void)
77 return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
80 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
82 return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
86 /* -------------------------------------------------------------------------*/
88 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
94 spin_lock_irqsave(&pci_lock, flags);
96 write_cfgaddr(mkaddr(bus,devfn,where));
97 data = read_cfgdata();
99 DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
100 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
119 DBG(", 0x%08X returned\n", data);
121 spin_unlock_irqrestore(&pci_lock, flags);
123 return PCIBIOS_SUCCESSFUL;
126 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
133 spin_lock_irqsave(&pci_lock, flags);
135 write_cfgaddr(mkaddr(bus,devfn,where));
136 data = read_cfgdata();
138 DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
139 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
144 s = ((where & 3) << 3);
145 data &= ~(0xFF << s);
146 data |= ((val & 0xFF) << s);
149 s = ((where & 2) << 4);
150 data &= ~(0xFFFF << s);
151 data |= ((val & 0xFFFF) << s);
159 DBG(", 0x%08X written\n", data);
161 spin_unlock_irqrestore(&pci_lock, flags);
163 return PCIBIOS_SUCCESSFUL;
166 struct pci_ops adm5120_pci_ops = {
167 .read = pci_config_read,
168 .write = pci_config_write,
171 /* -------------------------------------------------------------------------*/
173 static void adm5120_pci_fixup(struct pci_dev *dev)
178 /* setup COMMAND register */
179 pci_write_config_word(dev, PCI_COMMAND,
180 (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
182 /* setup CACHE_LINE_SIZE register */
183 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
186 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
187 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
193 /* -------------------------------------------------------------------------*/
195 void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
196 struct adm5120_pci_irq *map)
198 adm5120_pci_nr_irqs = nr_irqs;
199 adm5120_pci_irq_map = map;
202 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
207 if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
208 printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
212 if (slot < 1 || slot > 3) {
213 printk(KERN_ALERT "PCI: slot number %u is not supported\n",
218 for (i = 0; i < adm5120_pci_nr_irqs; i++) {
219 if ((adm5120_pci_irq_map[i].slot == slot)
220 && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
221 && (adm5120_pci_irq_map[i].pin == pin)) {
222 irq = adm5120_pci_irq_map[i].irq;
228 printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
231 printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
232 pci_name(dev), pin, irq);
239 int pcibios_plat_dev_init(struct pci_dev *dev)
244 /* -------------------------------------------------------------------------*/
246 static struct resource pci_io_resource = {
247 .name = "ADM5120 PCI I/O",
248 .start = ADM5120_PCIIO_BASE,
249 .end = ADM5120_PCICFG_ADDR-1,
250 .flags = IORESOURCE_IO
253 static struct resource pci_mem_resource = {
254 .name = "ADM5120 PCI MEM",
255 .start = ADM5120_PCIMEM_BASE,
256 .end = ADM5120_PCIIO_BASE-1,
257 .flags = IORESOURCE_MEM
260 static struct pci_controller adm5120_controller = {
261 .pci_ops = &adm5120_pci_ops,
262 .io_resource = &pci_io_resource,
263 .mem_resource = &pci_mem_resource,
266 static int __init adm5120_pci_setup(void)
270 pci_bios = adm5120_has_pci();
272 printk(KERN_INFO "adm5120: system has %sPCI BIOS\n",
273 pci_bios ? "" : "no ");
277 /* Avoid ISA compat ranges. */
278 PCIBIOS_MIN_IO = 0x00000000;
279 PCIBIOS_MIN_MEM = 0x00000000;
281 /* Set I/O resource limits. */
282 ioport_resource.end = 0x1fffffff;
283 iomem_resource.end = 0xffffffff;
285 register_pci_controller(&adm5120_controller);
289 arch_initcall(adm5120_pci_setup);