1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
41 #include "davinci-mcasp.h"
43 #define MCASP_MAX_AFIFO_DEPTH 64
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_PFUNC_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
81 struct snd_pcm_substream *substreams[2];
84 /* McASP specific data */
102 unsigned long pdir; /* Pin direction bitfield */
104 /* McASP FIFO related */
110 /* Used for comstraint setting on the second stream */
113 #ifdef CONFIG_GPIOLIB
114 struct gpio_chip gpio_chip;
118 struct davinci_mcasp_context context;
121 struct davinci_mcasp_ruledata ruledata[2];
122 struct snd_pcm_hw_constraint_list chconstr[2];
125 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
128 void __iomem *reg = mcasp->base + offset;
129 __raw_writel(__raw_readl(reg) | val, reg);
132 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
135 void __iomem *reg = mcasp->base + offset;
136 __raw_writel((__raw_readl(reg) & ~(val)), reg);
139 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
142 void __iomem *reg = mcasp->base + offset;
143 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
146 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
149 __raw_writel(val, mcasp->base + offset);
152 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
154 return (u32)__raw_readl(mcasp->base + offset);
157 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
161 mcasp_set_bits(mcasp, ctl_reg, val);
163 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
164 /* loop count is to avoid the lock-up */
165 for (i = 0; i < 1000; i++) {
166 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
170 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
171 printk(KERN_ERR "GBLCTL write error\n");
174 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
176 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
177 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
179 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
182 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
184 u32 bit = PIN_BIT_AMUTE;
186 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
188 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
190 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
194 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
198 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
200 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
202 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
206 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
208 if (mcasp->rxnumevt) { /* enable FIFO */
209 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
211 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
212 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
216 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
219 * When ASYNC == 0 the transmit and receive sections operate
220 * synchronously from the transmit clock and frame sync. We need to make
221 * sure that the TX signlas are enabled when starting reception.
223 if (mcasp_is_synchronous(mcasp)) {
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
226 mcasp_set_clk_pdir(mcasp, true);
229 /* Activate serializer(s) */
230 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
232 /* Release RX state machine */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
234 /* Release Frame Sync generator */
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
236 if (mcasp_is_synchronous(mcasp))
237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
239 /* enable receive IRQs */
240 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
241 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
244 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
248 if (mcasp->txnumevt) { /* enable FIFO */
249 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
251 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
252 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
256 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
257 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
258 mcasp_set_clk_pdir(mcasp, true);
260 /* Activate serializer(s) */
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
264 /* wait for XDATA to be cleared */
266 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
270 mcasp_set_axr_pdir(mcasp, true);
272 /* Release TX state machine */
273 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
274 /* Release Frame Sync generator */
275 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
277 /* enable transmit IRQs */
278 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
279 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
282 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
286 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
287 mcasp_start_tx(mcasp);
289 mcasp_start_rx(mcasp);
292 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
294 /* disable IRQ sources */
295 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
296 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
299 * In synchronous mode stop the TX clocks if no other stream is
302 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
303 mcasp_set_clk_pdir(mcasp, false);
304 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
308 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
310 if (mcasp->rxnumevt) { /* disable FIFO */
311 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
313 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
317 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
321 /* disable IRQ sources */
322 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
323 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
326 * In synchronous mode keep TX clocks running if the capture stream is
329 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
330 val = TXHCLKRST | TXCLKRST | TXFSRST;
332 mcasp_set_clk_pdir(mcasp, false);
335 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
336 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
338 if (mcasp->txnumevt) { /* disable FIFO */
339 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
341 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
344 mcasp_set_axr_pdir(mcasp, false);
347 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
351 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
352 mcasp_stop_tx(mcasp);
354 mcasp_stop_rx(mcasp);
357 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
359 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
360 struct snd_pcm_substream *substream;
361 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
362 u32 handled_mask = 0;
365 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
366 if (stat & XUNDRN & irq_mask) {
367 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
368 handled_mask |= XUNDRN;
370 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
372 snd_pcm_stop_xrun(substream);
376 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
380 handled_mask |= XRERR;
382 /* Ack the handled event only */
383 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
385 return IRQ_RETVAL(handled_mask);
388 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
390 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
391 struct snd_pcm_substream *substream;
392 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
393 u32 handled_mask = 0;
396 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
397 if (stat & ROVRN & irq_mask) {
398 dev_warn(mcasp->dev, "Receive buffer overflow\n");
399 handled_mask |= ROVRN;
401 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
403 snd_pcm_stop_xrun(substream);
407 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
411 handled_mask |= XRERR;
413 /* Ack the handled event only */
414 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
416 return IRQ_RETVAL(handled_mask);
419 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
421 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
422 irqreturn_t ret = IRQ_NONE;
424 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
425 ret = davinci_mcasp_tx_irq_handler(irq, data);
427 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
428 ret |= davinci_mcasp_rx_irq_handler(irq, data);
433 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
436 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
445 pm_runtime_get_sync(mcasp->dev);
446 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
447 case SND_SOC_DAIFMT_DSP_A:
448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
449 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
450 /* 1st data bit occur one ACLK cycle after the frame sync */
453 case SND_SOC_DAIFMT_DSP_B:
454 case SND_SOC_DAIFMT_AC97:
455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
457 /* No delay after FS */
460 case SND_SOC_DAIFMT_I2S:
461 /* configure a full-word SYNC pulse (LRCLK) */
462 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
464 /* 1st data bit occur one ACLK cycle after the frame sync */
466 /* FS need to be inverted */
469 case SND_SOC_DAIFMT_LEFT_J:
470 /* configure a full-word SYNC pulse (LRCLK) */
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
473 /* No delay after FS */
481 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
483 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
486 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
487 case SND_SOC_DAIFMT_CBS_CFS:
488 /* codec is clock and frame slave */
489 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
490 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
492 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
496 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
497 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
499 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
500 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
502 mcasp->bclk_master = 1;
504 case SND_SOC_DAIFMT_CBS_CFM:
505 /* codec is clock slave and frame master */
506 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
513 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
514 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
516 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
517 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
519 mcasp->bclk_master = 1;
521 case SND_SOC_DAIFMT_CBM_CFS:
522 /* codec is clock master and frame slave */
523 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
524 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
530 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
531 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
533 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
534 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
536 mcasp->bclk_master = 0;
538 case SND_SOC_DAIFMT_CBM_CFM:
539 /* codec is clock and frame master */
540 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
541 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
547 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
548 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
550 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
551 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
553 mcasp->bclk_master = 0;
560 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
561 case SND_SOC_DAIFMT_IB_NF:
562 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
563 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564 fs_pol_rising = true;
566 case SND_SOC_DAIFMT_NB_IF:
567 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
568 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
569 fs_pol_rising = false;
571 case SND_SOC_DAIFMT_IB_IF:
572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
573 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
574 fs_pol_rising = false;
576 case SND_SOC_DAIFMT_NB_NF:
577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
578 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
579 fs_pol_rising = true;
587 fs_pol_rising = !fs_pol_rising;
590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
591 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
593 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
594 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
597 mcasp->dai_fmt = fmt;
599 pm_runtime_put(mcasp->dev);
603 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
604 int div, bool explicit)
606 pm_runtime_get_sync(mcasp->dev);
608 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
609 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
610 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
612 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
615 case MCASP_CLKDIV_BCLK: /* BCLK divider */
616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
617 ACLKXDIV(div - 1), ACLKXDIV_MASK);
618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
619 ACLKRDIV(div - 1), ACLKRDIV_MASK);
621 mcasp->bclk_div = div;
624 case MCASP_CLKDIV_BCLK_FS_RATIO:
626 * BCLK/LRCLK ratio descries how many bit-clock cycles
627 * fit into one frame. The clock ratio is given for a
628 * full period of data (for I2S format both left and
629 * right channels), so it has to be divided by number
630 * of tdm-slots (for I2S - divided by 2).
631 * Instead of storing this ratio, we calculate a new
632 * tdm_slot width by dividing the the ratio by the
633 * number of configured tdm slots.
635 mcasp->slot_width = div / mcasp->tdm_slots;
636 if (div % mcasp->tdm_slots)
638 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
639 __func__, div, mcasp->tdm_slots);
646 pm_runtime_put(mcasp->dev);
650 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
653 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
655 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
658 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
659 unsigned int freq, int dir)
661 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
663 pm_runtime_get_sync(mcasp->dev);
664 if (dir == SND_SOC_CLOCK_OUT) {
665 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
666 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
667 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
669 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
670 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
671 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
674 mcasp->sysclk_freq = freq;
676 pm_runtime_put(mcasp->dev);
680 /* All serializers must have equal number of channels */
681 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
684 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
685 unsigned int *list = (unsigned int *) cl->list;
686 int slots = mcasp->tdm_slots;
689 if (mcasp->tdm_mask[stream])
690 slots = hweight32(mcasp->tdm_mask[stream]);
692 for (i = 1; i <= slots; i++)
695 for (i = 2; i <= serializers; i++)
696 list[count++] = i*slots;
703 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
705 int rx_serializers = 0, tx_serializers = 0, ret, i;
707 for (i = 0; i < mcasp->num_serializer; i++)
708 if (mcasp->serial_dir[i] == TX_MODE)
710 else if (mcasp->serial_dir[i] == RX_MODE)
713 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
718 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
725 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
726 unsigned int tx_mask,
727 unsigned int rx_mask,
728 int slots, int slot_width)
730 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
733 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
734 __func__, tx_mask, rx_mask, slots, slot_width);
736 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
738 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
739 tx_mask, rx_mask, slots);
744 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
745 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
746 __func__, slot_width);
750 mcasp->tdm_slots = slots;
751 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
752 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
753 mcasp->slot_width = slot_width;
755 return davinci_mcasp_set_ch_constraints(mcasp);
758 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
762 u32 tx_rotate = (sample_width / 4) & 0x7;
763 u32 mask = (1ULL << sample_width) - 1;
764 u32 slot_width = sample_width;
767 * For captured data we should not rotate, inversion and masking is
768 * enoguh to get the data to the right position:
769 * Format data from bus after reverse (XRBUF)
770 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
771 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
772 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
773 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
778 * Setting the tdm slot width either with set_clkdiv() or
779 * set_tdm_slot() allows us to for example send 32 bits per
780 * channel to the codec, while only 16 of them carry audio
783 if (mcasp->slot_width) {
785 * When we have more bclk then it is needed for the
786 * data, we need to use the rotation to move the
787 * received samples to have correct alignment.
789 slot_width = mcasp->slot_width;
790 rx_rotate = (slot_width - sample_width) / 4;
793 /* mapping of the XSSZ bit-field as described in the datasheet */
794 fmt = (slot_width >> 1) - 1;
796 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
799 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
801 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
803 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
805 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
808 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
813 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
814 int period_words, int channels)
816 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
820 u8 slots = mcasp->tdm_slots;
821 u8 max_active_serializers = (channels + slots - 1) / slots;
822 int active_serializers, numevt;
824 /* Default configuration */
825 if (mcasp->version < MCASP_VERSION_3)
826 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
828 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
830 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
833 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
836 for (i = 0; i < mcasp->num_serializer; i++) {
837 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
838 mcasp->serial_dir[i]);
839 if (mcasp->serial_dir[i] == TX_MODE &&
840 tx_ser < max_active_serializers) {
841 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
842 mcasp->dismod, DISMOD_MASK);
843 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
845 } else if (mcasp->serial_dir[i] == RX_MODE &&
846 rx_ser < max_active_serializers) {
847 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
850 /* Inactive or unused pin, set it to inactive */
851 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
852 SRMOD_INACTIVE, SRMOD_MASK);
853 /* If unused, set DISMOD for the pin */
854 if (mcasp->serial_dir[i] != INACTIVE_MODE)
855 mcasp_mod_bits(mcasp,
856 DAVINCI_MCASP_XRSRCTL_REG(i),
857 mcasp->dismod, DISMOD_MASK);
858 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
862 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
863 active_serializers = tx_ser;
864 numevt = mcasp->txnumevt;
865 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
867 active_serializers = rx_ser;
868 numevt = mcasp->rxnumevt;
869 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
872 if (active_serializers < max_active_serializers) {
873 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
874 "enabled in mcasp (%d)\n", channels,
875 active_serializers * slots);
879 /* AFIFO is not in use */
881 /* Configure the burst size for platform drivers */
882 if (active_serializers > 1) {
884 * If more than one serializers are in use we have one
885 * DMA request to provide data for all serializers.
886 * For example if three serializers are enabled the DMA
887 * need to transfer three words per DMA request.
889 dma_data->maxburst = active_serializers;
891 dma_data->maxburst = 0;
896 if (period_words % active_serializers) {
897 dev_err(mcasp->dev, "Invalid combination of period words and "
898 "active serializers: %d, %d\n", period_words,
904 * Calculate the optimal AFIFO depth for platform side:
905 * The number of words for numevt need to be in steps of active
908 numevt = (numevt / active_serializers) * active_serializers;
910 while (period_words % numevt && numevt > 0)
911 numevt -= active_serializers;
913 numevt = active_serializers;
915 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
916 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
918 /* Configure the burst size for platform drivers */
921 dma_data->maxburst = numevt;
926 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
931 int active_serializers;
935 total_slots = mcasp->tdm_slots;
938 * If more than one serializer is needed, then use them with
939 * all the specified tdm_slots. Otherwise, one serializer can
940 * cope with the transaction using just as many slots as there
941 * are channels in the stream.
943 if (mcasp->tdm_mask[stream]) {
944 active_slots = hweight32(mcasp->tdm_mask[stream]);
945 active_serializers = (channels + active_slots - 1) /
947 if (active_serializers == 1)
948 active_slots = channels;
949 for (i = 0; i < total_slots; i++) {
950 if ((1 << i) & mcasp->tdm_mask[stream]) {
952 if (--active_slots <= 0)
957 active_serializers = (channels + total_slots - 1) / total_slots;
958 if (active_serializers == 1)
959 active_slots = channels;
961 active_slots = total_slots;
963 for (i = 0; i < active_slots; i++)
967 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
969 if (!mcasp->dat_port)
972 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
973 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
974 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
975 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
976 FSXMOD(total_slots), FSXMOD(0x1FF));
977 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
978 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
979 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
980 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
981 FSRMOD(total_slots), FSRMOD(0x1FF));
983 * If McASP is set to be TX/RX synchronous and the playback is
984 * not running already we need to configure the TX slots in
985 * order to have correct FSX on the bus
987 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
988 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
989 FSXMOD(total_slots), FSXMOD(0x1FF));
996 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1000 u8 *cs_bytes = (u8*) &cs_value;
1002 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1004 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1006 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1007 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1009 /* Set the TX tdm : for all the slots */
1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1012 /* Set the TX clock controls : div = 1 and internal */
1013 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1015 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1017 /* Only 44100 and 48000 are valid, both have the same setting */
1018 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1020 /* Enable the DIT */
1021 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1023 /* Set S/PDIF channel status bits */
1024 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1025 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1029 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1032 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1035 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1038 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1041 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1044 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1047 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1050 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1053 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1056 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1060 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1061 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1066 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1067 unsigned int sysclk_freq,
1068 unsigned int bclk_freq, bool set)
1070 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1071 int div = sysclk_freq / bclk_freq;
1072 int rem = sysclk_freq % bclk_freq;
1076 if (div > (ACLKXDIV_MASK + 1)) {
1077 if (reg & AHCLKXE) {
1078 aux_div = div / (ACLKXDIV_MASK + 1);
1079 if (div % (ACLKXDIV_MASK + 1))
1082 sysclk_freq /= aux_div;
1083 div = sysclk_freq / bclk_freq;
1084 rem = sysclk_freq % bclk_freq;
1086 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1093 ((sysclk_freq / div) - bclk_freq) >
1094 (bclk_freq - (sysclk_freq / (div+1)))) {
1096 rem = rem - bclk_freq;
1099 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1100 (int)bclk_freq)) / div - 1000000;
1104 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1107 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1109 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1116 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1118 if (!mcasp->txnumevt)
1121 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1124 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1126 if (!mcasp->rxnumevt)
1129 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1132 static snd_pcm_sframes_t davinci_mcasp_delay(
1133 struct snd_pcm_substream *substream,
1134 struct snd_soc_dai *cpu_dai)
1136 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1139 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1140 fifo_use = davinci_mcasp_tx_delay(mcasp);
1142 fifo_use = davinci_mcasp_rx_delay(mcasp);
1145 * Divide the used locations with the channel count to get the
1146 * FIFO usage in samples (don't care about partial samples in the
1149 return fifo_use / substream->runtime->channels;
1152 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1153 struct snd_pcm_hw_params *params,
1154 struct snd_soc_dai *cpu_dai)
1156 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1158 int channels = params_channels(params);
1159 int period_size = params_period_size(params);
1162 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1167 * If mcasp is BCLK master, and a BCLK divider was not provided by
1168 * the machine driver, we need to calculate the ratio.
1170 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1171 int slots = mcasp->tdm_slots;
1172 int rate = params_rate(params);
1173 int sbits = params_width(params);
1175 if (mcasp->slot_width)
1176 sbits = mcasp->slot_width;
1178 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1179 rate * sbits * slots, true);
1182 ret = mcasp_common_hw_param(mcasp, substream->stream,
1183 period_size * channels, channels);
1187 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1188 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1190 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1196 switch (params_format(params)) {
1197 case SNDRV_PCM_FORMAT_U8:
1198 case SNDRV_PCM_FORMAT_S8:
1202 case SNDRV_PCM_FORMAT_U16_LE:
1203 case SNDRV_PCM_FORMAT_S16_LE:
1207 case SNDRV_PCM_FORMAT_U24_3LE:
1208 case SNDRV_PCM_FORMAT_S24_3LE:
1212 case SNDRV_PCM_FORMAT_U24_LE:
1213 case SNDRV_PCM_FORMAT_S24_LE:
1217 case SNDRV_PCM_FORMAT_U32_LE:
1218 case SNDRV_PCM_FORMAT_S32_LE:
1223 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1227 davinci_config_channel_size(mcasp, word_length);
1229 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1230 mcasp->channels = channels;
1235 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1236 int cmd, struct snd_soc_dai *cpu_dai)
1238 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1242 case SNDRV_PCM_TRIGGER_RESUME:
1243 case SNDRV_PCM_TRIGGER_START:
1244 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1245 davinci_mcasp_start(mcasp, substream->stream);
1247 case SNDRV_PCM_TRIGGER_SUSPEND:
1248 case SNDRV_PCM_TRIGGER_STOP:
1249 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1250 davinci_mcasp_stop(mcasp, substream->stream);
1260 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1261 struct snd_pcm_hw_rule *rule)
1263 struct davinci_mcasp_ruledata *rd = rule->private;
1264 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1265 struct snd_mask nfmt;
1268 snd_mask_none(&nfmt);
1269 slot_width = rd->mcasp->slot_width;
1271 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1272 if (snd_mask_test(fmt, i)) {
1273 if (snd_pcm_format_width(i) <= slot_width) {
1274 snd_mask_set(&nfmt, i);
1279 return snd_mask_refine(fmt, &nfmt);
1282 static const unsigned int davinci_mcasp_dai_rates[] = {
1283 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1284 88200, 96000, 176400, 192000,
1287 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1289 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1290 struct snd_pcm_hw_rule *rule)
1292 struct davinci_mcasp_ruledata *rd = rule->private;
1293 struct snd_interval *ri =
1294 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1295 int sbits = params_width(params);
1296 int slots = rd->mcasp->tdm_slots;
1297 struct snd_interval range;
1300 if (rd->mcasp->slot_width)
1301 sbits = rd->mcasp->slot_width;
1303 snd_interval_any(&range);
1306 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1307 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1308 uint bclk_freq = sbits * slots *
1309 davinci_mcasp_dai_rates[i];
1310 unsigned int sysclk_freq;
1313 if (rd->mcasp->auxclk_fs_ratio)
1314 sysclk_freq = davinci_mcasp_dai_rates[i] *
1315 rd->mcasp->auxclk_fs_ratio;
1317 sysclk_freq = rd->mcasp->sysclk_freq;
1319 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1321 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1323 range.min = davinci_mcasp_dai_rates[i];
1326 range.max = davinci_mcasp_dai_rates[i];
1331 dev_dbg(rd->mcasp->dev,
1332 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1333 ri->min, ri->max, range.min, range.max, sbits, slots);
1335 return snd_interval_refine(hw_param_interval(params, rule->var),
1339 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1340 struct snd_pcm_hw_rule *rule)
1342 struct davinci_mcasp_ruledata *rd = rule->private;
1343 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1344 struct snd_mask nfmt;
1345 int rate = params_rate(params);
1346 int slots = rd->mcasp->tdm_slots;
1349 snd_mask_none(&nfmt);
1351 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1352 if (snd_mask_test(fmt, i)) {
1353 uint sbits = snd_pcm_format_width(i);
1354 unsigned int sysclk_freq;
1357 if (rd->mcasp->auxclk_fs_ratio)
1358 sysclk_freq = rate *
1359 rd->mcasp->auxclk_fs_ratio;
1361 sysclk_freq = rd->mcasp->sysclk_freq;
1363 if (rd->mcasp->slot_width)
1364 sbits = rd->mcasp->slot_width;
1366 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1367 sbits * slots * rate,
1369 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1370 snd_mask_set(&nfmt, i);
1375 dev_dbg(rd->mcasp->dev,
1376 "%d possible sample format for %d Hz and %d tdm slots\n",
1377 count, rate, slots);
1379 return snd_mask_refine(fmt, &nfmt);
1382 static int davinci_mcasp_hw_rule_min_periodsize(
1383 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1385 struct snd_interval *period_size = hw_param_interval(params,
1386 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1387 struct snd_interval frames;
1389 snd_interval_any(&frames);
1393 return snd_interval_refine(period_size, &frames);
1396 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1397 struct snd_soc_dai *cpu_dai)
1399 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1400 struct davinci_mcasp_ruledata *ruledata =
1401 &mcasp->ruledata[substream->stream];
1402 u32 max_channels = 0;
1404 int tdm_slots = mcasp->tdm_slots;
1406 /* Do not allow more then one stream per direction */
1407 if (mcasp->substreams[substream->stream])
1410 mcasp->substreams[substream->stream] = substream;
1412 if (mcasp->tdm_mask[substream->stream])
1413 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1415 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1419 * Limit the maximum allowed channels for the first stream:
1420 * number of serializers for the direction * tdm slots per serializer
1422 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1427 for (i = 0; i < mcasp->num_serializer; i++) {
1428 if (mcasp->serial_dir[i] == dir)
1431 ruledata->serializers = max_channels;
1432 ruledata->mcasp = mcasp;
1433 max_channels *= tdm_slots;
1435 * If the already active stream has less channels than the calculated
1436 * limnit based on the seirializers * tdm_slots, we need to use that as
1437 * a constraint for the second stream.
1438 * Otherwise (first stream or less allowed channels) we use the
1439 * calculated constraint.
1441 if (mcasp->channels && mcasp->channels < max_channels)
1442 max_channels = mcasp->channels;
1444 * But we can always allow channels upto the amount of
1445 * the available tdm_slots.
1447 if (max_channels < tdm_slots)
1448 max_channels = tdm_slots;
1450 snd_pcm_hw_constraint_minmax(substream->runtime,
1451 SNDRV_PCM_HW_PARAM_CHANNELS,
1454 snd_pcm_hw_constraint_list(substream->runtime,
1455 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1456 &mcasp->chconstr[substream->stream]);
1458 if (mcasp->slot_width) {
1459 /* Only allow formats require <= slot_width bits on the bus */
1460 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1461 SNDRV_PCM_HW_PARAM_FORMAT,
1462 davinci_mcasp_hw_rule_slot_width,
1464 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1470 * If we rely on implicit BCLK divider setting we should
1471 * set constraints based on what we can provide.
1473 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1474 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1475 SNDRV_PCM_HW_PARAM_RATE,
1476 davinci_mcasp_hw_rule_rate,
1478 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1481 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1482 SNDRV_PCM_HW_PARAM_FORMAT,
1483 davinci_mcasp_hw_rule_format,
1485 SNDRV_PCM_HW_PARAM_RATE, -1);
1490 snd_pcm_hw_rule_add(substream->runtime, 0,
1491 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1492 davinci_mcasp_hw_rule_min_periodsize, NULL,
1493 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1498 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1499 struct snd_soc_dai *cpu_dai)
1501 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1503 mcasp->substreams[substream->stream] = NULL;
1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1508 if (!cpu_dai->active)
1509 mcasp->channels = 0;
1512 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1513 .startup = davinci_mcasp_startup,
1514 .shutdown = davinci_mcasp_shutdown,
1515 .trigger = davinci_mcasp_trigger,
1516 .delay = davinci_mcasp_delay,
1517 .hw_params = davinci_mcasp_hw_params,
1518 .set_fmt = davinci_mcasp_set_dai_fmt,
1519 .set_clkdiv = davinci_mcasp_set_clkdiv,
1520 .set_sysclk = davinci_mcasp_set_sysclk,
1521 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1524 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1526 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1528 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1529 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1534 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1536 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1537 SNDRV_PCM_FMTBIT_U8 | \
1538 SNDRV_PCM_FMTBIT_S16_LE | \
1539 SNDRV_PCM_FMTBIT_U16_LE | \
1540 SNDRV_PCM_FMTBIT_S24_LE | \
1541 SNDRV_PCM_FMTBIT_U24_LE | \
1542 SNDRV_PCM_FMTBIT_S24_3LE | \
1543 SNDRV_PCM_FMTBIT_U24_3LE | \
1544 SNDRV_PCM_FMTBIT_S32_LE | \
1545 SNDRV_PCM_FMTBIT_U32_LE)
1547 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1549 .name = "davinci-mcasp.0",
1550 .probe = davinci_mcasp_dai_probe,
1553 .channels_max = 32 * 16,
1554 .rates = DAVINCI_MCASP_RATES,
1555 .formats = DAVINCI_MCASP_PCM_FMTS,
1559 .channels_max = 32 * 16,
1560 .rates = DAVINCI_MCASP_RATES,
1561 .formats = DAVINCI_MCASP_PCM_FMTS,
1563 .ops = &davinci_mcasp_dai_ops,
1565 .symmetric_samplebits = 1,
1566 .symmetric_rates = 1,
1569 .name = "davinci-mcasp.1",
1570 .probe = davinci_mcasp_dai_probe,
1573 .channels_max = 384,
1574 .rates = DAVINCI_MCASP_RATES,
1575 .formats = DAVINCI_MCASP_PCM_FMTS,
1577 .ops = &davinci_mcasp_dai_ops,
1582 static const struct snd_soc_component_driver davinci_mcasp_component = {
1583 .name = "davinci-mcasp",
1586 /* Some HW specific values and defaults. The rest is filled in from DT. */
1587 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1588 .tx_dma_offset = 0x400,
1589 .rx_dma_offset = 0x400,
1590 .version = MCASP_VERSION_1,
1593 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1594 .tx_dma_offset = 0x2000,
1595 .rx_dma_offset = 0x2000,
1596 .version = MCASP_VERSION_2,
1599 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1602 .version = MCASP_VERSION_3,
1605 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1606 /* The CFG port offset will be calculated if it is needed */
1609 .version = MCASP_VERSION_4,
1612 static const struct of_device_id mcasp_dt_ids[] = {
1614 .compatible = "ti,dm646x-mcasp-audio",
1615 .data = &dm646x_mcasp_pdata,
1618 .compatible = "ti,da830-mcasp-audio",
1619 .data = &da830_mcasp_pdata,
1622 .compatible = "ti,am33xx-mcasp-audio",
1623 .data = &am33xx_mcasp_pdata,
1626 .compatible = "ti,dra7-mcasp-audio",
1627 .data = &dra7_mcasp_pdata,
1631 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1633 static int mcasp_reparent_fck(struct platform_device *pdev)
1635 struct device_node *node = pdev->dev.of_node;
1636 struct clk *gfclk, *parent_clk;
1637 const char *parent_name;
1643 parent_name = of_get_property(node, "fck_parent", NULL);
1647 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1649 gfclk = clk_get(&pdev->dev, "fck");
1650 if (IS_ERR(gfclk)) {
1651 dev_err(&pdev->dev, "failed to get fck\n");
1652 return PTR_ERR(gfclk);
1655 parent_clk = clk_get(NULL, parent_name);
1656 if (IS_ERR(parent_clk)) {
1657 dev_err(&pdev->dev, "failed to get parent clock\n");
1658 ret = PTR_ERR(parent_clk);
1662 ret = clk_set_parent(gfclk, parent_clk);
1664 dev_err(&pdev->dev, "failed to reparent fck\n");
1669 clk_put(parent_clk);
1675 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1676 struct platform_device *pdev)
1678 struct device_node *np = pdev->dev.of_node;
1679 struct davinci_mcasp_pdata *pdata = NULL;
1680 const struct of_device_id *match =
1681 of_match_device(mcasp_dt_ids, &pdev->dev);
1682 struct of_phandle_args dma_spec;
1684 const u32 *of_serial_dir32;
1688 if (pdev->dev.platform_data) {
1689 pdata = pdev->dev.platform_data;
1690 pdata->dismod = DISMOD_LOW;
1693 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1700 /* control shouldn't reach here. something is wrong */
1705 ret = of_property_read_u32(np, "op-mode", &val);
1707 pdata->op_mode = val;
1709 ret = of_property_read_u32(np, "tdm-slots", &val);
1711 if (val < 2 || val > 32) {
1713 "tdm-slots must be in rage [2-32]\n");
1718 pdata->tdm_slots = val;
1721 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1723 if (of_serial_dir32) {
1724 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1725 (sizeof(*of_serial_dir) * val),
1727 if (!of_serial_dir) {
1732 for (i = 0; i < val; i++)
1733 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1735 pdata->num_serializer = val;
1736 pdata->serial_dir = of_serial_dir;
1739 ret = of_property_match_string(np, "dma-names", "tx");
1743 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1748 pdata->tx_dma_channel = dma_spec.args[0];
1750 /* RX is not valid in DIT mode */
1751 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1752 ret = of_property_match_string(np, "dma-names", "rx");
1756 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1761 pdata->rx_dma_channel = dma_spec.args[0];
1764 ret = of_property_read_u32(np, "tx-num-evt", &val);
1766 pdata->txnumevt = val;
1768 ret = of_property_read_u32(np, "rx-num-evt", &val);
1770 pdata->rxnumevt = val;
1772 ret = of_property_read_u32(np, "sram-size-playback", &val);
1774 pdata->sram_size_playback = val;
1776 ret = of_property_read_u32(np, "sram-size-capture", &val);
1778 pdata->sram_size_capture = val;
1780 ret = of_property_read_u32(np, "dismod", &val);
1782 if (val == 0 || val == 2 || val == 3) {
1783 pdata->dismod = DISMOD_VAL(val);
1785 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1786 pdata->dismod = DISMOD_LOW;
1789 pdata->dismod = DISMOD_LOW;
1796 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1807 static const char *sdma_prefix = "ti,omap";
1809 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1811 struct dma_chan *chan;
1815 if (!mcasp->dev->of_node)
1818 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1819 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1821 if (PTR_ERR(chan) != -EPROBE_DEFER)
1823 "Can't verify DMA configuration (%ld)\n",
1825 return PTR_ERR(chan);
1827 if (WARN_ON(!chan->device || !chan->device->dev))
1830 if (chan->device->dev->of_node)
1831 ret = of_property_read_string(chan->device->dev->of_node,
1832 "compatible", &tmp);
1834 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1836 dma_release_channel(chan);
1840 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1841 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1847 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1852 if (pdata->version != MCASP_VERSION_4)
1853 return pdata->tx_dma_offset;
1855 for (i = 0; i < pdata->num_serializer; i++) {
1856 if (pdata->serial_dir[i] == TX_MODE) {
1858 offset = DAVINCI_MCASP_TXBUF_REG(i);
1860 pr_err("%s: Only one serializer allowed!\n",
1870 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1875 if (pdata->version != MCASP_VERSION_4)
1876 return pdata->rx_dma_offset;
1878 for (i = 0; i < pdata->num_serializer; i++) {
1879 if (pdata->serial_dir[i] == RX_MODE) {
1881 offset = DAVINCI_MCASP_RXBUF_REG(i);
1883 pr_err("%s: Only one serializer allowed!\n",
1893 #ifdef CONFIG_GPIOLIB
1894 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1896 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1898 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1899 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1900 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1904 /* Do not change the PIN yet */
1906 return pm_runtime_get_sync(mcasp->dev);
1909 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1911 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1913 /* Set the direction to input */
1914 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1916 /* Set the pin as McASP pin */
1917 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1919 pm_runtime_put_sync(mcasp->dev);
1922 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1923 unsigned offset, int value)
1925 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1929 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1931 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1933 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1934 if (!(val & BIT(offset))) {
1935 /* Set the pin as GPIO pin */
1936 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1938 /* Set the direction to output */
1939 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1945 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
1948 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1951 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1953 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1956 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
1959 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1962 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1963 if (!(val & BIT(offset))) {
1964 /* Set the direction to input */
1965 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1967 /* Set the pin as GPIO pin */
1968 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1974 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
1976 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1979 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
1980 if (val & BIT(offset))
1986 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
1989 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1992 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1993 if (val & BIT(offset))
1999 static const struct gpio_chip davinci_mcasp_template_chip = {
2000 .owner = THIS_MODULE,
2001 .request = davinci_mcasp_gpio_request,
2002 .free = davinci_mcasp_gpio_free,
2003 .direction_output = davinci_mcasp_gpio_direction_out,
2004 .set = davinci_mcasp_gpio_set,
2005 .direction_input = davinci_mcasp_gpio_direction_in,
2006 .get = davinci_mcasp_gpio_get,
2007 .get_direction = davinci_mcasp_gpio_get_direction,
2012 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2014 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2017 mcasp->gpio_chip = davinci_mcasp_template_chip;
2018 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2019 mcasp->gpio_chip.parent = mcasp->dev;
2020 #ifdef CONFIG_OF_GPIO
2021 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2024 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2027 #else /* CONFIG_GPIOLIB */
2028 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2032 #endif /* CONFIG_GPIOLIB */
2034 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2036 struct device_node *np = mcasp->dev->of_node;
2043 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2045 mcasp->auxclk_fs_ratio = val;
2050 static int davinci_mcasp_probe(struct platform_device *pdev)
2052 struct snd_dmaengine_dai_dma_data *dma_data;
2053 struct resource *mem, *res, *dat;
2054 struct davinci_mcasp_pdata *pdata;
2055 struct davinci_mcasp *mcasp;
2061 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2062 dev_err(&pdev->dev, "No platform data supplied\n");
2066 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2071 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2073 dev_err(&pdev->dev, "no platform data\n");
2077 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2079 dev_warn(mcasp->dev,
2080 "\"mpu\" mem resource not found, using index 0\n");
2081 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2083 dev_err(&pdev->dev, "no mem resource?\n");
2088 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2089 if (IS_ERR(mcasp->base))
2090 return PTR_ERR(mcasp->base);
2092 pm_runtime_enable(&pdev->dev);
2094 mcasp->op_mode = pdata->op_mode;
2095 /* sanity check for tdm slots parameter */
2096 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2097 if (pdata->tdm_slots < 2) {
2098 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2100 mcasp->tdm_slots = 2;
2101 } else if (pdata->tdm_slots > 32) {
2102 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2104 mcasp->tdm_slots = 32;
2106 mcasp->tdm_slots = pdata->tdm_slots;
2110 mcasp->num_serializer = pdata->num_serializer;
2112 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2113 mcasp->num_serializer, sizeof(u32),
2115 if (!mcasp->context.xrsr_regs) {
2120 mcasp->serial_dir = pdata->serial_dir;
2121 mcasp->version = pdata->version;
2122 mcasp->txnumevt = pdata->txnumevt;
2123 mcasp->rxnumevt = pdata->rxnumevt;
2124 mcasp->dismod = pdata->dismod;
2126 mcasp->dev = &pdev->dev;
2128 irq = platform_get_irq_byname(pdev, "common");
2130 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2131 dev_name(&pdev->dev));
2136 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2137 davinci_mcasp_common_irq_handler,
2138 IRQF_ONESHOT | IRQF_SHARED,
2141 dev_err(&pdev->dev, "common IRQ request failed\n");
2145 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2146 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2149 irq = platform_get_irq_byname(pdev, "rx");
2151 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2152 dev_name(&pdev->dev));
2157 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2158 davinci_mcasp_rx_irq_handler,
2159 IRQF_ONESHOT, irq_name, mcasp);
2161 dev_err(&pdev->dev, "RX IRQ request failed\n");
2165 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2168 irq = platform_get_irq_byname(pdev, "tx");
2170 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2171 dev_name(&pdev->dev));
2176 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2177 davinci_mcasp_tx_irq_handler,
2178 IRQF_ONESHOT, irq_name, mcasp);
2180 dev_err(&pdev->dev, "TX IRQ request failed\n");
2184 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2187 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2189 mcasp->dat_port = true;
2191 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2193 dma_data->addr = dat->start;
2195 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2197 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2198 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2202 *dma = pdata->tx_dma_channel;
2204 /* dmaengine filter data for DT and non-DT boot */
2205 if (pdev->dev.of_node)
2206 dma_data->filter_data = "tx";
2208 dma_data->filter_data = dma;
2210 /* RX is not valid in DIT mode */
2211 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2212 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2214 dma_data->addr = dat->start;
2217 mem->start + davinci_mcasp_rxdma_offset(pdata);
2219 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2220 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2224 *dma = pdata->rx_dma_channel;
2226 /* dmaengine filter data for DT and non-DT boot */
2227 if (pdev->dev.of_node)
2228 dma_data->filter_data = "rx";
2230 dma_data->filter_data = dma;
2233 if (mcasp->version < MCASP_VERSION_3) {
2234 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2235 /* dma_params->dma_addr is pointing to the data port address */
2236 mcasp->dat_port = true;
2238 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2241 /* Allocate memory for long enough list for all possible
2242 * scenarios. Maximum number tdm slots is 32 and there cannot
2243 * be more serializers than given in the configuration. The
2244 * serializer directions could be taken into account, but it
2245 * would make code much more complex and save only couple of
2248 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2249 devm_kcalloc(mcasp->dev,
2250 32 + mcasp->num_serializer - 1,
2251 sizeof(unsigned int),
2254 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2255 devm_kcalloc(mcasp->dev,
2256 32 + mcasp->num_serializer - 1,
2257 sizeof(unsigned int),
2260 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2261 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2266 ret = davinci_mcasp_set_ch_constraints(mcasp);
2270 dev_set_drvdata(&pdev->dev, mcasp);
2272 mcasp_reparent_fck(pdev);
2274 /* All PINS as McASP */
2275 pm_runtime_get_sync(mcasp->dev);
2276 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2277 pm_runtime_put(mcasp->dev);
2279 ret = davinci_mcasp_init_gpiochip(mcasp);
2283 ret = davinci_mcasp_get_dt_params(mcasp);
2287 ret = devm_snd_soc_register_component(&pdev->dev,
2288 &davinci_mcasp_component,
2289 &davinci_mcasp_dai[pdata->op_mode], 1);
2294 ret = davinci_mcasp_get_dma_type(mcasp);
2297 ret = edma_pcm_platform_register(&pdev->dev);
2300 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2303 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2310 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2317 pm_runtime_disable(&pdev->dev);
2321 static int davinci_mcasp_remove(struct platform_device *pdev)
2323 pm_runtime_disable(&pdev->dev);
2329 static int davinci_mcasp_runtime_suspend(struct device *dev)
2331 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2332 struct davinci_mcasp_context *context = &mcasp->context;
2336 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2337 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2339 if (mcasp->txnumevt) {
2340 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2341 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2343 if (mcasp->rxnumevt) {
2344 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2345 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2348 for (i = 0; i < mcasp->num_serializer; i++)
2349 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2350 DAVINCI_MCASP_XRSRCTL_REG(i));
2355 static int davinci_mcasp_runtime_resume(struct device *dev)
2357 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2358 struct davinci_mcasp_context *context = &mcasp->context;
2362 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2363 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2365 if (mcasp->txnumevt) {
2366 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2367 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2369 if (mcasp->rxnumevt) {
2370 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2371 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2374 for (i = 0; i < mcasp->num_serializer; i++)
2375 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2376 context->xrsr_regs[i]);
2383 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2384 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2385 davinci_mcasp_runtime_resume,
2389 static struct platform_driver davinci_mcasp_driver = {
2390 .probe = davinci_mcasp_probe,
2391 .remove = davinci_mcasp_remove,
2393 .name = "davinci-mcasp",
2394 .pm = &davinci_mcasp_pm_ops,
2395 .of_match_table = mcasp_dt_ids,
2399 module_platform_driver(davinci_mcasp_driver);
2401 MODULE_AUTHOR("Steve Chen");
2402 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2403 MODULE_LICENSE("GPL");