sound/soc/mediatek/mt8183/mt8183-afe-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Mediatek ALSA SoC AFE platform driver for 8183
   4 //
   5 // Copyright (c) 2018 MediaTek Inc.
   6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pm_runtime.h>
  14
  15 #include "mt8183-afe-common.h"
  16 #include "mt8183-afe-clk.h"
  17 #include "mt8183-interconnection.h"
  18 #include "mt8183-reg.h"
  19 #include "../common/mtk-afe-platform-driver.h"
  20 #include "../common/mtk-afe-fe-dai.h"
  21
  22 enum {
  23         MTK_AFE_RATE_8K = 0,
  24         MTK_AFE_RATE_11K = 1,
  25         MTK_AFE_RATE_12K = 2,
  26         MTK_AFE_RATE_384K = 3,
  27         MTK_AFE_RATE_16K = 4,
  28         MTK_AFE_RATE_22K = 5,
  29         MTK_AFE_RATE_24K = 6,
  30         MTK_AFE_RATE_130K = 7,
  31         MTK_AFE_RATE_32K = 8,
  32         MTK_AFE_RATE_44K = 9,
  33         MTK_AFE_RATE_48K = 10,
  34         MTK_AFE_RATE_88K = 11,
  35         MTK_AFE_RATE_96K = 12,
  36         MTK_AFE_RATE_176K = 13,
  37         MTK_AFE_RATE_192K = 14,
  38         MTK_AFE_RATE_260K = 15,
  39 };
  40
  41 enum {
  42         MTK_AFE_DAI_MEMIF_RATE_8K = 0,
  43         MTK_AFE_DAI_MEMIF_RATE_16K = 1,
  44         MTK_AFE_DAI_MEMIF_RATE_32K = 2,
  45         MTK_AFE_DAI_MEMIF_RATE_48K = 3,
  46 };
  47
  48 enum {
  49         MTK_AFE_PCM_RATE_8K = 0,
  50         MTK_AFE_PCM_RATE_16K = 1,
  51         MTK_AFE_PCM_RATE_32K = 2,
  52         MTK_AFE_PCM_RATE_48K = 3,
  53 };
  54
  55 unsigned int mt8183_general_rate_transform(struct device *dev,
  56                                            unsigned int rate)
  57 {
  58         switch (rate) {
  59         case 8000:
  60                 return MTK_AFE_RATE_8K;
  61         case 11025:
  62                 return MTK_AFE_RATE_11K;
  63         case 12000:
  64                 return MTK_AFE_RATE_12K;
  65         case 16000:
  66                 return MTK_AFE_RATE_16K;
  67         case 22050:
  68                 return MTK_AFE_RATE_22K;
  69         case 24000:
  70                 return MTK_AFE_RATE_24K;
  71         case 32000:
  72                 return MTK_AFE_RATE_32K;
  73         case 44100:
  74                 return MTK_AFE_RATE_44K;
  75         case 48000:
  76                 return MTK_AFE_RATE_48K;
  77         case 88200:
  78                 return MTK_AFE_RATE_88K;
  79         case 96000:
  80                 return MTK_AFE_RATE_96K;
  81         case 130000:
  82                 return MTK_AFE_RATE_130K;
  83         case 176400:
  84                 return MTK_AFE_RATE_176K;
  85         case 192000:
  86                 return MTK_AFE_RATE_192K;
  87         case 260000:
  88                 return MTK_AFE_RATE_260K;
  89         default:
  90                 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
  91                          __func__, rate, MTK_AFE_RATE_48K);
  92                 return MTK_AFE_RATE_48K;
  93         }
  94 }
  95
  96 static unsigned int dai_memif_rate_transform(struct device *dev,
  97                                              unsigned int rate)
  98 {
  99         switch (rate) {
 100         case 8000:
 101                 return MTK_AFE_DAI_MEMIF_RATE_8K;
 102         case 16000:
 103                 return MTK_AFE_DAI_MEMIF_RATE_16K;
 104         case 32000:
 105                 return MTK_AFE_DAI_MEMIF_RATE_32K;
 106         case 48000:
 107                 return MTK_AFE_DAI_MEMIF_RATE_48K;
 108         default:
 109                 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
 110                          __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
 111                 return MTK_AFE_DAI_MEMIF_RATE_16K;
 112         }
 113 }
 114
 115 unsigned int mt8183_rate_transform(struct device *dev,
 116                                    unsigned int rate, int aud_blk)
 117 {
 118         switch (aud_blk) {
 119         case MT8183_MEMIF_MOD_DAI:
 120                 return dai_memif_rate_transform(dev, rate);
 121         default:
 122                 return mt8183_general_rate_transform(dev, rate);
 123         }
 124 }
 125
 126 static const struct snd_pcm_hardware mt8183_afe_hardware = {
 127         .info = SNDRV_PCM_INFO_MMAP |
 128                 SNDRV_PCM_INFO_INTERLEAVED |
 129                 SNDRV_PCM_INFO_MMAP_VALID,
 130         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 131                    SNDRV_PCM_FMTBIT_S24_LE |
 132                    SNDRV_PCM_FMTBIT_S32_LE,
 133         .period_bytes_min = 256,
 134         .period_bytes_max = 4 * 48 * 1024,
 135         .periods_min = 2,
 136         .periods_max = 256,
 137         .buffer_bytes_max = 8 * 48 * 1024,
 138         .fifo_size = 0,
 139 };
 140
 141 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
 142                            unsigned int rate)
 143 {
 144         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 145         struct snd_soc_component *component =
 146                 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
 147         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
 148         int id = rtd->cpu_dai->id;
 149
 150         return mt8183_rate_transform(afe->dev, rate, id);
 151 }
 152
 153 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
 154 {
 155         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 156         struct snd_soc_component *component =
 157                 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
 158         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
 159
 160         return mt8183_general_rate_transform(afe->dev, rate);
 161 }
 162
 163 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
 164                        SNDRV_PCM_RATE_88200 |\
 165                        SNDRV_PCM_RATE_96000 |\
 166                        SNDRV_PCM_RATE_176400 |\
 167                        SNDRV_PCM_RATE_192000)
 168
 169 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
 170                            SNDRV_PCM_RATE_16000 |\
 171                            SNDRV_PCM_RATE_32000 |\
 172                            SNDRV_PCM_RATE_48000)
 173
 174 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 175                          SNDRV_PCM_FMTBIT_S24_LE |\
 176                          SNDRV_PCM_FMTBIT_S32_LE)
 177
 178 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
 179         /* FE DAIs: memory intefaces to CPU */
 180         {
 181                 .name = "DL1",
 182                 .id = MT8183_MEMIF_DL1,
 183                 .playback = {
 184                         .stream_name = "DL1",
 185                         .channels_min = 1,
 186                         .channels_max = 2,
 187                         .rates = MTK_PCM_RATES,
 188                         .formats = MTK_PCM_FORMATS,
 189                 },
 190                 .ops = &mtk_afe_fe_ops,
 191         },
 192         {
 193                 .name = "DL2",
 194                 .id = MT8183_MEMIF_DL2,
 195                 .playback = {
 196                         .stream_name = "DL2",
 197                         .channels_min = 1,
 198                         .channels_max = 2,
 199                         .rates = MTK_PCM_RATES,
 200                         .formats = MTK_PCM_FORMATS,
 201                 },
 202                 .ops = &mtk_afe_fe_ops,
 203         },
 204         {
 205                 .name = "DL3",
 206                 .id = MT8183_MEMIF_DL3,
 207                 .playback = {
 208                         .stream_name = "DL3",
 209                         .channels_min = 1,
 210                         .channels_max = 2,
 211                         .rates = MTK_PCM_RATES,
 212                         .formats = MTK_PCM_FORMATS,
 213                 },
 214                 .ops = &mtk_afe_fe_ops,
 215         },
 216         {
 217                 .name = "UL1",
 218                 .id = MT8183_MEMIF_VUL12,
 219                 .capture = {
 220                         .stream_name = "UL1",
 221                         .channels_min = 1,
 222                         .channels_max = 2,
 223                         .rates = MTK_PCM_RATES,
 224                         .formats = MTK_PCM_FORMATS,
 225                 },
 226                 .ops = &mtk_afe_fe_ops,
 227         },
 228         {
 229                 .name = "UL2",
 230                 .id = MT8183_MEMIF_AWB,
 231                 .capture = {
 232                         .stream_name = "UL2",
 233                         .channels_min = 1,
 234                         .channels_max = 2,
 235                         .rates = MTK_PCM_RATES,
 236                         .formats = MTK_PCM_FORMATS,
 237                 },
 238                 .ops = &mtk_afe_fe_ops,
 239         },
 240         {
 241                 .name = "UL3",
 242                 .id = MT8183_MEMIF_VUL2,
 243                 .capture = {
 244                         .stream_name = "UL3",
 245                         .channels_min = 1,
 246                         .channels_max = 2,
 247                         .rates = MTK_PCM_RATES,
 248                         .formats = MTK_PCM_FORMATS,
 249                 },
 250                 .ops = &mtk_afe_fe_ops,
 251         },
 252         {
 253                 .name = "UL4",
 254                 .id = MT8183_MEMIF_AWB2,
 255                 .capture = {
 256                         .stream_name = "UL4",
 257                         .channels_min = 1,
 258                         .channels_max = 2,
 259                         .rates = MTK_PCM_RATES,
 260                         .formats = MTK_PCM_FORMATS,
 261                 },
 262                 .ops = &mtk_afe_fe_ops,
 263         },
 264         {
 265                 .name = "UL_MONO_1",
 266                 .id = MT8183_MEMIF_MOD_DAI,
 267                 .capture = {
 268                         .stream_name = "UL_MONO_1",
 269                         .channels_min = 1,
 270                         .channels_max = 1,
 271                         .rates = MTK_PCM_DAI_RATES,
 272                         .formats = MTK_PCM_FORMATS,
 273                 },
 274                 .ops = &mtk_afe_fe_ops,
 275         },
 276         {
 277                 .name = "HDMI",
 278                 .id = MT8183_MEMIF_HDMI,
 279                 .playback = {
 280                         .stream_name = "HDMI",
 281                         .channels_min = 2,
 282                         .channels_max = 8,
 283                         .rates = MTK_PCM_RATES,
 284                         .formats = MTK_PCM_FORMATS,
 285                 },
 286                 .ops = &mtk_afe_fe_ops,
 287         },
 288 };
 289
 290 /* dma widget & routes*/
 291 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
 292         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
 293                                     I_ADDA_UL_CH1, 1, 0),
 294         SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
 295                                     I_I2S0_CH1, 1, 0),
 296 };
 297
 298 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
 299         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
 300                                     I_ADDA_UL_CH2, 1, 0),
 301         SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
 302                                     I_I2S0_CH2, 1, 0),
 303 };
 304
 305 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
 306         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
 307                                     I_ADDA_UL_CH1, 1, 0),
 308         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
 309                                     I_DL1_CH1, 1, 0),
 310         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
 311                                     I_DL2_CH1, 1, 0),
 312         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
 313                                     I_DL3_CH1, 1, 0),
 314         SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
 315                                     I_I2S2_CH1, 1, 0),
 316 };
 317
 318 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
 319         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
 320                                     I_ADDA_UL_CH2, 1, 0),
 321         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
 322                                     I_DL1_CH2, 1, 0),
 323         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
 324                                     I_DL2_CH2, 1, 0),
 325         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
 326                                     I_DL3_CH2, 1, 0),
 327         SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
 328                                     I_I2S2_CH2, 1, 0),
 329 };
 330
 331 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
 332         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
 333                                     I_ADDA_UL_CH1, 1, 0),
 334         SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
 335                                     I_I2S2_CH1, 1, 0),
 336 };
 337
 338 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
 339         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
 340                                     I_ADDA_UL_CH2, 1, 0),
 341         SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
 342                                     I_I2S2_CH2, 1, 0),
 343 };
 344
 345 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
 346         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
 347                                     I_ADDA_UL_CH1, 1, 0),
 348 };
 349
 350 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
 351         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
 352                                     I_ADDA_UL_CH2, 1, 0),
 353 };
 354
 355 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
 356         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
 357                                     I_ADDA_UL_CH1, 1, 0),
 358         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
 359                                     I_ADDA_UL_CH2, 1, 0),
 360 };
 361
 362 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
 363         /* memif */
 364         SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
 365                            memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
 366         SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
 367                            memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
 368
 369         SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
 370                            memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
 371         SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
 372                            memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
 373
 374         SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
 375                            memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
 376         SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
 377                            memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
 378
 379         SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
 380                            memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
 381         SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
 382                            memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
 383
 384         SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
 385                            memif_ul_mono_1_mix,
 386                            ARRAY_SIZE(memif_ul_mono_1_mix)),
 387 };
 388
 389 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
 390         /* capture */
 391         {"UL1", NULL, "UL1_CH1"},
 392         {"UL1", NULL, "UL1_CH2"},
 393         {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
 394         {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
 395         {"UL1_CH1", "I2S0_CH1", "I2S0"},
 396         {"UL1_CH2", "I2S0_CH2", "I2S0"},
 397
 398         {"UL2", NULL, "UL2_CH1"},
 399         {"UL2", NULL, "UL2_CH2"},
 400         {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
 401         {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
 402         {"UL2_CH1", "I2S2_CH1", "I2S2"},
 403         {"UL2_CH2", "I2S2_CH2", "I2S2"},
 404
 405         {"UL3", NULL, "UL3_CH1"},
 406         {"UL3", NULL, "UL3_CH2"},
 407         {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
 408         {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
 409         {"UL3_CH1", "I2S2_CH1", "I2S2"},
 410         {"UL3_CH2", "I2S2_CH2", "I2S2"},
 411
 412         {"UL4", NULL, "UL4_CH1"},
 413         {"UL4", NULL, "UL4_CH2"},
 414         {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
 415         {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
 416
 417         {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
 418         {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
 419         {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
 420 };
 421
 422 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
 423         .name = "mt8183-afe-pcm-dai",
 424 };
 425
 426 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
 427         [MT8183_MEMIF_DL1] = {
 428                 .name = "DL1",
 429                 .id = MT8183_MEMIF_DL1,
 430                 .reg_ofs_base = AFE_DL1_BASE,
 431                 .reg_ofs_cur = AFE_DL1_CUR,
 432                 .fs_reg = AFE_DAC_CON1,
 433                 .fs_shift = DL1_MODE_SFT,
 434                 .fs_maskbit = DL1_MODE_MASK,
 435                 .mono_reg = AFE_DAC_CON1,
 436                 .mono_shift = DL1_DATA_SFT,
 437                 .enable_reg = AFE_DAC_CON0,
 438                 .enable_shift = DL1_ON_SFT,
 439                 .hd_reg = AFE_MEMIF_HD_MODE,
 440                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 441                 .hd_shift = DL1_HD_SFT,
 442                 .hd_align_mshift = DL1_HD_ALIGN_SFT,
 443                 .agent_disable_reg = -1,
 444                 .agent_disable_shift = -1,
 445                 .msb_reg = -1,
 446                 .msb_shift = -1,
 447         },
 448         [MT8183_MEMIF_DL2] = {
 449                 .name = "DL2",
 450                 .id = MT8183_MEMIF_DL2,
 451                 .reg_ofs_base = AFE_DL2_BASE,
 452                 .reg_ofs_cur = AFE_DL2_CUR,
 453                 .fs_reg = AFE_DAC_CON1,
 454                 .fs_shift = DL2_MODE_SFT,
 455                 .fs_maskbit = DL2_MODE_MASK,
 456                 .mono_reg = AFE_DAC_CON1,
 457                 .mono_shift = DL2_DATA_SFT,
 458                 .enable_reg = AFE_DAC_CON0,
 459                 .enable_shift = DL2_ON_SFT,
 460                 .hd_reg = AFE_MEMIF_HD_MODE,
 461                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 462                 .hd_shift = DL2_HD_SFT,
 463                 .hd_align_mshift = DL2_HD_ALIGN_SFT,
 464                 .agent_disable_reg = -1,
 465                 .agent_disable_shift = -1,
 466                 .msb_reg = -1,
 467                 .msb_shift = -1,
 468         },
 469         [MT8183_MEMIF_DL3] = {
 470                 .name = "DL3",
 471                 .id = MT8183_MEMIF_DL3,
 472                 .reg_ofs_base = AFE_DL3_BASE,
 473                 .reg_ofs_cur = AFE_DL3_CUR,
 474                 .fs_reg = AFE_DAC_CON2,
 475                 .fs_shift = DL3_MODE_SFT,
 476                 .fs_maskbit = DL3_MODE_MASK,
 477                 .mono_reg = AFE_DAC_CON1,
 478                 .mono_shift = DL3_DATA_SFT,
 479                 .enable_reg = AFE_DAC_CON0,
 480                 .enable_shift = DL3_ON_SFT,
 481                 .hd_reg = AFE_MEMIF_HD_MODE,
 482                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 483                 .hd_shift = DL3_HD_SFT,
 484                 .hd_align_mshift = DL3_HD_ALIGN_SFT,
 485                 .agent_disable_reg = -1,
 486                 .agent_disable_shift = -1,
 487                 .msb_reg = -1,
 488                 .msb_shift = -1,
 489         },
 490         [MT8183_MEMIF_VUL2] = {
 491                 .name = "VUL2",
 492                 .id = MT8183_MEMIF_VUL2,
 493                 .reg_ofs_base = AFE_VUL2_BASE,
 494                 .reg_ofs_cur = AFE_VUL2_CUR,
 495                 .fs_reg = AFE_DAC_CON2,
 496                 .fs_shift = VUL2_MODE_SFT,
 497                 .fs_maskbit = VUL2_MODE_MASK,
 498                 .mono_reg = AFE_DAC_CON2,
 499                 .mono_shift = VUL2_DATA_SFT,
 500                 .enable_reg = AFE_DAC_CON0,
 501                 .enable_shift = VUL2_ON_SFT,
 502                 .hd_reg = AFE_MEMIF_HD_MODE,
 503                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 504                 .hd_shift = VUL2_HD_SFT,
 505                 .hd_align_mshift = VUL2_HD_ALIGN_SFT,
 506                 .agent_disable_reg = -1,
 507                 .agent_disable_shift = -1,
 508                 .msb_reg = -1,
 509                 .msb_shift = -1,
 510         },
 511         [MT8183_MEMIF_AWB] = {
 512                 .name = "AWB",
 513                 .id = MT8183_MEMIF_AWB,
 514                 .reg_ofs_base = AFE_AWB_BASE,
 515                 .reg_ofs_cur = AFE_AWB_CUR,
 516                 .fs_reg = AFE_DAC_CON1,
 517                 .fs_shift = AWB_MODE_SFT,
 518                 .fs_maskbit = AWB_MODE_MASK,
 519                 .mono_reg = AFE_DAC_CON1,
 520                 .mono_shift = AWB_DATA_SFT,
 521                 .enable_reg = AFE_DAC_CON0,
 522                 .enable_shift = AWB_ON_SFT,
 523                 .hd_reg = AFE_MEMIF_HD_MODE,
 524                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 525                 .hd_shift = AWB_HD_SFT,
 526                 .hd_align_mshift = AWB_HD_ALIGN_SFT,
 527                 .agent_disable_reg = -1,
 528                 .agent_disable_shift = -1,
 529                 .msb_reg = -1,
 530                 .msb_shift = -1,
 531         },
 532         [MT8183_MEMIF_AWB2] = {
 533                 .name = "AWB2",
 534                 .id = MT8183_MEMIF_AWB2,
 535                 .reg_ofs_base = AFE_AWB2_BASE,
 536                 .reg_ofs_cur = AFE_AWB2_CUR,
 537                 .fs_reg = AFE_DAC_CON2,
 538                 .fs_shift = AWB2_MODE_SFT,
 539                 .fs_maskbit = AWB2_MODE_MASK,
 540                 .mono_reg = AFE_DAC_CON2,
 541                 .mono_shift = AWB2_DATA_SFT,
 542                 .enable_reg = AFE_DAC_CON0,
 543                 .enable_shift = AWB2_ON_SFT,
 544                 .hd_reg = AFE_MEMIF_HD_MODE,
 545                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 546                 .hd_shift = AWB2_HD_SFT,
 547                 .hd_align_mshift = AWB2_ALIGN_SFT,
 548                 .agent_disable_reg = -1,
 549                 .agent_disable_shift = -1,
 550                 .msb_reg = -1,
 551                 .msb_shift = -1,
 552         },
 553         [MT8183_MEMIF_VUL12] = {
 554                 .name = "VUL12",
 555                 .id = MT8183_MEMIF_VUL12,
 556                 .reg_ofs_base = AFE_VUL_D2_BASE,
 557                 .reg_ofs_cur = AFE_VUL_D2_CUR,
 558                 .fs_reg = AFE_DAC_CON0,
 559                 .fs_shift = VUL12_MODE_SFT,
 560                 .fs_maskbit = VUL12_MODE_MASK,
 561                 .mono_reg = AFE_DAC_CON0,
 562                 .mono_shift = VUL12_MONO_SFT,
 563                 .enable_reg = AFE_DAC_CON0,
 564                 .enable_shift = VUL12_ON_SFT,
 565                 .hd_reg = AFE_MEMIF_HD_MODE,
 566                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 567                 .hd_shift = VUL12_HD_SFT,
 568                 .hd_align_mshift = VUL12_HD_ALIGN_SFT,
 569                 .agent_disable_reg = -1,
 570                 .agent_disable_shift = -1,
 571                 .msb_reg = -1,
 572                 .msb_shift = -1,
 573         },
 574         [MT8183_MEMIF_MOD_DAI] = {
 575                 .name = "MOD_DAI",
 576                 .id = MT8183_MEMIF_MOD_DAI,
 577                 .reg_ofs_base = AFE_MOD_DAI_BASE,
 578                 .reg_ofs_cur = AFE_MOD_DAI_CUR,
 579                 .fs_reg = AFE_DAC_CON1,
 580                 .fs_shift = MOD_DAI_MODE_SFT,
 581                 .fs_maskbit = MOD_DAI_MODE_MASK,
 582                 .mono_reg = -1,
 583                 .mono_shift = 0,
 584                 .enable_reg = AFE_DAC_CON0,
 585                 .enable_shift = MOD_DAI_ON_SFT,
 586                 .hd_reg = AFE_MEMIF_HD_MODE,
 587                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 588                 .hd_shift = MOD_DAI_HD_SFT,
 589                 .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
 590                 .agent_disable_reg = -1,
 591                 .agent_disable_shift = -1,
 592                 .msb_reg = -1,
 593                 .msb_shift = -1,
 594         },
 595         [MT8183_MEMIF_HDMI] = {
 596                 .name = "HDMI",
 597                 .id = MT8183_MEMIF_HDMI,
 598                 .reg_ofs_base = AFE_HDMI_OUT_BASE,
 599                 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
 600                 .fs_reg = -1,
 601                 .fs_shift = -1,
 602                 .fs_maskbit = -1,
 603                 .mono_reg = -1,
 604                 .mono_shift = -1,
 605                 .enable_reg = -1,       /* control in tdm for sync start */
 606                 .enable_shift = -1,
 607                 .hd_reg = AFE_MEMIF_HD_MODE,
 608                 .hd_align_reg = AFE_MEMIF_HDALIGN,
 609                 .hd_shift = HDMI_HD_SFT,
 610                 .hd_align_mshift = HDMI_HD_ALIGN_SFT,
 611                 .agent_disable_reg = -1,
 612                 .agent_disable_shift = -1,
 613                 .msb_reg = -1,
 614                 .msb_shift = -1,
 615         },
 616 };
 617
 618 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
 619         [MT8183_IRQ_0] = {
 620                 .id = MT8183_IRQ_0,
 621                 .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
 622                 .irq_cnt_shift = 0,
 623                 .irq_cnt_maskbit = 0x3ffff,
 624                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 625                 .irq_fs_shift = IRQ0_MCU_MODE_SFT,
 626                 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
 627                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 628                 .irq_en_shift = IRQ0_MCU_ON_SFT,
 629                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 630                 .irq_clr_shift = IRQ0_MCU_CLR_SFT,
 631         },
 632         [MT8183_IRQ_1] = {
 633                 .id = MT8183_IRQ_1,
 634                 .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
 635                 .irq_cnt_shift = 0,
 636                 .irq_cnt_maskbit = 0x3ffff,
 637                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 638                 .irq_fs_shift = IRQ1_MCU_MODE_SFT,
 639                 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
 640                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 641                 .irq_en_shift = IRQ1_MCU_ON_SFT,
 642                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 643                 .irq_clr_shift = IRQ1_MCU_CLR_SFT,
 644         },
 645         [MT8183_IRQ_2] = {
 646                 .id = MT8183_IRQ_2,
 647                 .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
 648                 .irq_cnt_shift = 0,
 649                 .irq_cnt_maskbit = 0x3ffff,
 650                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 651                 .irq_fs_shift = IRQ2_MCU_MODE_SFT,
 652                 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
 653                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 654                 .irq_en_shift = IRQ2_MCU_ON_SFT,
 655                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 656                 .irq_clr_shift = IRQ2_MCU_CLR_SFT,
 657         },
 658         [MT8183_IRQ_3] = {
 659                 .id = MT8183_IRQ_3,
 660                 .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
 661                 .irq_cnt_shift = 0,
 662                 .irq_cnt_maskbit = 0x3ffff,
 663                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 664                 .irq_fs_shift = IRQ3_MCU_MODE_SFT,
 665                 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
 666                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 667                 .irq_en_shift = IRQ3_MCU_ON_SFT,
 668                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 669                 .irq_clr_shift = IRQ3_MCU_CLR_SFT,
 670         },
 671         [MT8183_IRQ_4] = {
 672                 .id = MT8183_IRQ_4,
 673                 .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
 674                 .irq_cnt_shift = 0,
 675                 .irq_cnt_maskbit = 0x3ffff,
 676                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 677                 .irq_fs_shift = IRQ4_MCU_MODE_SFT,
 678                 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
 679                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 680                 .irq_en_shift = IRQ4_MCU_ON_SFT,
 681                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 682                 .irq_clr_shift = IRQ4_MCU_CLR_SFT,
 683         },
 684         [MT8183_IRQ_5] = {
 685                 .id = MT8183_IRQ_5,
 686                 .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
 687                 .irq_cnt_shift = 0,
 688                 .irq_cnt_maskbit = 0x3ffff,
 689                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 690                 .irq_fs_shift = IRQ5_MCU_MODE_SFT,
 691                 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
 692                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 693                 .irq_en_shift = IRQ5_MCU_ON_SFT,
 694                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 695                 .irq_clr_shift = IRQ5_MCU_CLR_SFT,
 696         },
 697         [MT8183_IRQ_6] = {
 698                 .id = MT8183_IRQ_6,
 699                 .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
 700                 .irq_cnt_shift = 0,
 701                 .irq_cnt_maskbit = 0x3ffff,
 702                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 703                 .irq_fs_shift = IRQ6_MCU_MODE_SFT,
 704                 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
 705                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 706                 .irq_en_shift = IRQ6_MCU_ON_SFT,
 707                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 708                 .irq_clr_shift = IRQ6_MCU_CLR_SFT,
 709         },
 710         [MT8183_IRQ_7] = {
 711                 .id = MT8183_IRQ_7,
 712                 .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
 713                 .irq_cnt_shift = 0,
 714                 .irq_cnt_maskbit = 0x3ffff,
 715                 .irq_fs_reg = AFE_IRQ_MCU_CON1,
 716                 .irq_fs_shift = IRQ7_MCU_MODE_SFT,
 717                 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
 718                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 719                 .irq_en_shift = IRQ7_MCU_ON_SFT,
 720                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 721                 .irq_clr_shift = IRQ7_MCU_CLR_SFT,
 722         },
 723         [MT8183_IRQ_8] = {
 724                 .id = MT8183_IRQ_8,
 725                 .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
 726                 .irq_cnt_shift = 0,
 727                 .irq_cnt_maskbit = 0x3ffff,
 728                 .irq_fs_reg = -1,
 729                 .irq_fs_shift = -1,
 730                 .irq_fs_maskbit = -1,
 731                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 732                 .irq_en_shift = IRQ8_MCU_ON_SFT,
 733                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 734                 .irq_clr_shift = IRQ8_MCU_CLR_SFT,
 735         },
 736         [MT8183_IRQ_11] = {
 737                 .id = MT8183_IRQ_11,
 738                 .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
 739                 .irq_cnt_shift = 0,
 740                 .irq_cnt_maskbit = 0x3ffff,
 741                 .irq_fs_reg = AFE_IRQ_MCU_CON2,
 742                 .irq_fs_shift = IRQ11_MCU_MODE_SFT,
 743                 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
 744                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 745                 .irq_en_shift = IRQ11_MCU_ON_SFT,
 746                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 747                 .irq_clr_shift = IRQ11_MCU_CLR_SFT,
 748         },
 749         [MT8183_IRQ_12] = {
 750                 .id = MT8183_IRQ_12,
 751                 .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
 752                 .irq_cnt_shift = 0,
 753                 .irq_cnt_maskbit = 0x3ffff,
 754                 .irq_fs_reg = AFE_IRQ_MCU_CON2,
 755                 .irq_fs_shift = IRQ12_MCU_MODE_SFT,
 756                 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
 757                 .irq_en_reg = AFE_IRQ_MCU_CON0,
 758                 .irq_en_shift = IRQ12_MCU_ON_SFT,
 759                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
 760                 .irq_clr_shift = IRQ12_MCU_CLR_SFT,
 761         },
 762 };
 763
 764 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
 765 {
 766         /* these auto-gen reg has read-only bit, so put it as volatile */
 767         /* volatile reg cannot be cached, so cannot be set when power off */
 768         switch (reg) {
 769         case AUDIO_TOP_CON0:    /* reg bit controlled by CCF */
 770         case AUDIO_TOP_CON1:    /* reg bit controlled by CCF */
 771         case AUDIO_TOP_CON3:
 772         case AFE_DL1_CUR:
 773         case AFE_DL1_END:
 774         case AFE_DL2_CUR:
 775         case AFE_DL2_END:
 776         case AFE_AWB_END:
 777         case AFE_AWB_CUR:
 778         case AFE_VUL_END:
 779         case AFE_VUL_CUR:
 780         case AFE_MEMIF_MON0:
 781         case AFE_MEMIF_MON1:
 782         case AFE_MEMIF_MON2:
 783         case AFE_MEMIF_MON3:
 784         case AFE_MEMIF_MON4:
 785         case AFE_MEMIF_MON5:
 786         case AFE_MEMIF_MON6:
 787         case AFE_MEMIF_MON7:
 788         case AFE_MEMIF_MON8:
 789         case AFE_MEMIF_MON9:
 790         case AFE_ADDA_SRC_DEBUG_MON0:
 791         case AFE_ADDA_SRC_DEBUG_MON1:
 792         case AFE_ADDA_UL_SRC_MON0:
 793         case AFE_ADDA_UL_SRC_MON1:
 794         case AFE_SIDETONE_MON:
 795         case AFE_SIDETONE_CON0:
 796         case AFE_SIDETONE_COEFF:
 797         case AFE_BUS_MON0:
 798         case AFE_MRGIF_MON0:
 799         case AFE_MRGIF_MON1:
 800         case AFE_MRGIF_MON2:
 801         case AFE_I2S_MON:
 802         case AFE_DAC_MON:
 803         case AFE_VUL2_END:
 804         case AFE_VUL2_CUR:
 805         case AFE_IRQ0_MCU_CNT_MON:
 806         case AFE_IRQ6_MCU_CNT_MON:
 807         case AFE_MOD_DAI_END:
 808         case AFE_MOD_DAI_CUR:
 809         case AFE_VUL_D2_END:
 810         case AFE_VUL_D2_CUR:
 811         case AFE_DL3_CUR:
 812         case AFE_DL3_END:
 813         case AFE_HDMI_OUT_CON0:
 814         case AFE_HDMI_OUT_CUR:
 815         case AFE_HDMI_OUT_END:
 816         case AFE_IRQ3_MCU_CNT_MON:
 817         case AFE_IRQ4_MCU_CNT_MON:
 818         case AFE_IRQ_MCU_STATUS:
 819         case AFE_IRQ_MCU_CLR:
 820         case AFE_IRQ_MCU_MON2:
 821         case AFE_IRQ1_MCU_CNT_MON:
 822         case AFE_IRQ2_MCU_CNT_MON:
 823         case AFE_IRQ1_MCU_EN_CNT_MON:
 824         case AFE_IRQ5_MCU_CNT_MON:
 825         case AFE_IRQ7_MCU_CNT_MON:
 826         case AFE_GAIN1_CUR:
 827         case AFE_GAIN2_CUR:
 828         case AFE_SRAM_DELSEL_CON0:
 829         case AFE_SRAM_DELSEL_CON2:
 830         case AFE_SRAM_DELSEL_CON3:
 831         case AFE_ASRC_2CH_CON12:
 832         case AFE_ASRC_2CH_CON13:
 833         case PCM_INTF_CON2:
 834         case FPGA_CFG0:
 835         case FPGA_CFG1:
 836         case FPGA_CFG2:
 837         case FPGA_CFG3:
 838         case AUDIO_TOP_DBG_MON0:
 839         case AUDIO_TOP_DBG_MON1:
 840         case AFE_IRQ8_MCU_CNT_MON:
 841         case AFE_IRQ11_MCU_CNT_MON:
 842         case AFE_IRQ12_MCU_CNT_MON:
 843         case AFE_CBIP_MON0:
 844         case AFE_CBIP_SLV_MUX_MON0:
 845         case AFE_CBIP_SLV_DECODER_MON0:
 846         case AFE_ADDA6_SRC_DEBUG_MON0:
 847         case AFE_ADD6A_UL_SRC_MON0:
 848         case AFE_ADDA6_UL_SRC_MON1:
 849         case AFE_DL1_CUR_MSB:
 850         case AFE_DL2_CUR_MSB:
 851         case AFE_AWB_CUR_MSB:
 852         case AFE_VUL_CUR_MSB:
 853         case AFE_VUL2_CUR_MSB:
 854         case AFE_MOD_DAI_CUR_MSB:
 855         case AFE_VUL_D2_CUR_MSB:
 856         case AFE_DL3_CUR_MSB:
 857         case AFE_HDMI_OUT_CUR_MSB:
 858         case AFE_AWB2_END:
 859         case AFE_AWB2_CUR:
 860         case AFE_AWB2_CUR_MSB:
 861         case AFE_ADDA_DL_SDM_FIFO_MON:
 862         case AFE_ADDA_DL_SRC_LCH_MON:
 863         case AFE_ADDA_DL_SRC_RCH_MON:
 864         case AFE_ADDA_DL_SDM_OUT_MON:
 865         case AFE_CONNSYS_I2S_MON:
 866         case AFE_ASRC_2CH_CON0:
 867         case AFE_ASRC_2CH_CON2:
 868         case AFE_ASRC_2CH_CON3:
 869         case AFE_ASRC_2CH_CON4:
 870         case AFE_ASRC_2CH_CON5:
 871         case AFE_ASRC_2CH_CON7:
 872         case AFE_ASRC_2CH_CON8:
 873         case AFE_MEMIF_MON12:
 874         case AFE_MEMIF_MON13:
 875         case AFE_MEMIF_MON14:
 876         case AFE_MEMIF_MON15:
 877         case AFE_MEMIF_MON16:
 878         case AFE_MEMIF_MON17:
 879         case AFE_MEMIF_MON18:
 880         case AFE_MEMIF_MON19:
 881         case AFE_MEMIF_MON20:
 882         case AFE_MEMIF_MON21:
 883         case AFE_MEMIF_MON22:
 884         case AFE_MEMIF_MON23:
 885         case AFE_MEMIF_MON24:
 886         case AFE_ADDA_MTKAIF_MON0:
 887         case AFE_ADDA_MTKAIF_MON1:
 888         case AFE_AUD_PAD_TOP:
 889         case AFE_GENERAL1_ASRC_2CH_CON0:
 890         case AFE_GENERAL1_ASRC_2CH_CON2:
 891         case AFE_GENERAL1_ASRC_2CH_CON3:
 892         case AFE_GENERAL1_ASRC_2CH_CON4:
 893         case AFE_GENERAL1_ASRC_2CH_CON5:
 894         case AFE_GENERAL1_ASRC_2CH_CON7:
 895         case AFE_GENERAL1_ASRC_2CH_CON8:
 896         case AFE_GENERAL1_ASRC_2CH_CON12:
 897         case AFE_GENERAL1_ASRC_2CH_CON13:
 898         case AFE_GENERAL2_ASRC_2CH_CON0:
 899         case AFE_GENERAL2_ASRC_2CH_CON2:
 900         case AFE_GENERAL2_ASRC_2CH_CON3:
 901         case AFE_GENERAL2_ASRC_2CH_CON4:
 902         case AFE_GENERAL2_ASRC_2CH_CON5:
 903         case AFE_GENERAL2_ASRC_2CH_CON7:
 904         case AFE_GENERAL2_ASRC_2CH_CON8:
 905         case AFE_GENERAL2_ASRC_2CH_CON12:
 906         case AFE_GENERAL2_ASRC_2CH_CON13:
 907                 return true;
 908         default:
 909                 return false;
 910         };
 911 }
 912
 913 static const struct regmap_config mt8183_afe_regmap_config = {
 914         .reg_bits = 32,
 915         .reg_stride = 4,
 916         .val_bits = 32,
 917
 918         .volatile_reg = mt8183_is_volatile_reg,
 919
 920         .max_register = AFE_MAX_REGISTER,
 921         .num_reg_defaults_raw = AFE_MAX_REGISTER,
 922
 923         .cache_type = REGCACHE_FLAT,
 924 };
 925
 926 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
 927 {
 928         struct mtk_base_afe *afe = dev;
 929         struct mtk_base_afe_irq *irq;
 930         unsigned int status;
 931         unsigned int status_mcu;
 932         unsigned int mcu_en;
 933         int ret;
 934         int i;
 935         irqreturn_t irq_ret = IRQ_HANDLED;
 936
 937         /* get irq that is sent to MCU */
 938         regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
 939
 940         ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
 941         /* only care IRQ which is sent to MCU */
 942         status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
 943
 944         if (ret || status_mcu == 0) {
 945                 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
 946                         __func__, ret, status, mcu_en);
 947
 948                 irq_ret = IRQ_NONE;
 949                 goto err_irq;
 950         }
 951
 952         for (i = 0; i < MT8183_MEMIF_NUM; i++) {
 953                 struct mtk_base_afe_memif *memif = &afe->memif[i];
 954
 955                 if (!memif->substream)
 956                         continue;
 957
 958                 if (memif->irq_usage < 0)
 959                         continue;
 960
 961                 irq = &afe->irqs[memif->irq_usage];
 962
 963                 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
 964                         snd_pcm_period_elapsed(memif->substream);
 965         }
 966
 967 err_irq:
 968         /* clear irq */
 969         regmap_write(afe->regmap,
 970                      AFE_IRQ_MCU_CLR,
 971                      status_mcu);
 972
 973         return irq_ret;
 974 }
 975
 976 static int mt8183_afe_runtime_suspend(struct device *dev)
 977 {
 978         struct mtk_base_afe *afe = dev_get_drvdata(dev);
 979         struct mt8183_afe_private *afe_priv = afe->platform_priv;
 980         unsigned int value;
 981         int ret;
 982
 983         if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
 984                 goto skip_regmap;
 985
 986         /* disable AFE */
 987         regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
 988
 989         ret = regmap_read_poll_timeout(afe->regmap,
 990                                        AFE_DAC_MON,
 991                                        value,
 992                                        (value & AFE_ON_RETM_MASK_SFT) == 0,
 993                                        20,
 994                                        1 * 1000 * 1000);
 995         if (ret)
 996                 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
 997
 998         /* make sure all irq status are cleared, twice intended */
 999         regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1000         regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1001
1002         /* cache only */
1003         regcache_cache_only(afe->regmap, true);
1004         regcache_mark_dirty(afe->regmap);
1005
1006 skip_regmap:
1007         return mt8183_afe_disable_clock(afe);
1008 }
1009
1010 static int mt8183_afe_runtime_resume(struct device *dev)
1011 {
1012         struct mtk_base_afe *afe = dev_get_drvdata(dev);
1013         struct mt8183_afe_private *afe_priv = afe->platform_priv;
1014         int ret;
1015
1016         ret = mt8183_afe_enable_clock(afe);
1017         if (ret)
1018                 return ret;
1019
1020         if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
1021                 goto skip_regmap;
1022
1023         regcache_cache_only(afe->regmap, false);
1024         regcache_sync(afe->regmap);
1025
1026         /* enable audio sys DCM for power saving */
1027         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
1028
1029         /* force cpu use 8_24 format when writing 32bit data */
1030         regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
1031                            CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
1032
1033         /* set all output port to 24bit */
1034         regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
1035         regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
1036
1037         /* enable AFE */
1038         regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1039
1040 skip_regmap:
1041         return 0;
1042 }
1043
1044 static int mt8183_afe_component_probe(struct snd_soc_component *component)
1045 {
1046         return mtk_afe_add_sub_dai_control(component);
1047 }
1048
1049 static const struct snd_soc_component_driver mt8183_afe_component = {
1050         .name = AFE_PCM_NAME,
1051         .ops = &mtk_afe_pcm_ops,
1052         .pcm_new = mtk_afe_pcm_new,
1053         .pcm_free = mtk_afe_pcm_free,
1054         .probe = mt8183_afe_component_probe,
1055 };
1056
1057 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
1058 {
1059         struct mtk_base_afe_dai *dai;
1060
1061         dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1062         if (!dai)
1063                 return -ENOMEM;
1064
1065         list_add(&dai->list, &afe->sub_dais);
1066
1067         dai->dai_drivers = mt8183_memif_dai_driver;
1068         dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
1069
1070         dai->dapm_widgets = mt8183_memif_widgets;
1071         dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
1072         dai->dapm_routes = mt8183_memif_routes;
1073         dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
1074         return 0;
1075 }
1076
1077 typedef int (*dai_register_cb)(struct mtk_base_afe *);
1078 static const dai_register_cb dai_register_cbs[] = {
1079         mt8183_dai_adda_register,
1080         mt8183_dai_i2s_register,
1081         mt8183_dai_pcm_register,
1082         mt8183_dai_tdm_register,
1083         mt8183_dai_hostless_register,
1084         mt8183_dai_memif_register,
1085 };
1086
1087 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
1088 {
1089         struct mtk_base_afe *afe;
1090         struct mt8183_afe_private *afe_priv;
1091         struct device *dev;
1092         int i, irq_id, ret;
1093
1094         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1095         if (!afe)
1096                 return -ENOMEM;
1097         platform_set_drvdata(pdev, afe);
1098
1099         afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1100                                           GFP_KERNEL);
1101         if (!afe->platform_priv)
1102                 return -ENOMEM;
1103
1104         afe_priv = afe->platform_priv;
1105         afe->dev = &pdev->dev;
1106         dev = afe->dev;
1107
1108         /* initial audio related clock */
1109         ret = mt8183_init_clock(afe);
1110         if (ret) {
1111                 dev_err(dev, "init clock error\n");
1112                 return ret;
1113         }
1114
1115         pm_runtime_enable(dev);
1116
1117         /* regmap init */
1118         afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1119         if (IS_ERR(afe->regmap)) {
1120                 dev_err(dev, "could not get regmap from parent\n");
1121                 return PTR_ERR(afe->regmap);
1122         }
1123         ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
1124         if (ret) {
1125                 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
1126                 return ret;
1127         }
1128
1129         /* enable clock for regcache get default value from hw */
1130         afe_priv->pm_runtime_bypass_reg_ctl = true;
1131         pm_runtime_get_sync(&pdev->dev);
1132
1133         ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
1134         if (ret) {
1135                 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
1136                 return ret;
1137         }
1138
1139         pm_runtime_put_sync(&pdev->dev);
1140         afe_priv->pm_runtime_bypass_reg_ctl = false;
1141
1142         regcache_cache_only(afe->regmap, true);
1143         regcache_mark_dirty(afe->regmap);
1144
1145         /* init memif */
1146         afe->memif_size = MT8183_MEMIF_NUM;
1147         afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1148                                   GFP_KERNEL);
1149         if (!afe->memif)
1150                 return -ENOMEM;
1151
1152         for (i = 0; i < afe->memif_size; i++) {
1153                 afe->memif[i].data = &memif_data[i];
1154                 afe->memif[i].irq_usage = -1;
1155         }
1156
1157         afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
1158         afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
1159
1160         mutex_init(&afe->irq_alloc_lock);
1161
1162         /* init memif */
1163         /* irq initialize */
1164         afe->irqs_size = MT8183_IRQ_NUM;
1165         afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1166                                  GFP_KERNEL);
1167         if (!afe->irqs)
1168                 return -ENOMEM;
1169
1170         for (i = 0; i < afe->irqs_size; i++)
1171                 afe->irqs[i].irq_data = &irq_data[i];
1172
1173         /* request irq */
1174         irq_id = platform_get_irq(pdev, 0);
1175         if (!irq_id) {
1176                 dev_err(dev, "%pOFn no irq found\n", dev->of_node);
1177                 return -ENXIO;
1178         }
1179         ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
1180                                IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1181         if (ret) {
1182                 dev_err(dev, "could not request_irq for asys-isr\n");
1183                 return ret;
1184         }
1185
1186         /* init sub_dais */
1187         INIT_LIST_HEAD(&afe->sub_dais);
1188
1189         for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
1190                 ret = dai_register_cbs[i](afe);
1191                 if (ret) {
1192                         dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
1193                                  i, ret);
1194                         return ret;
1195                 }
1196         }
1197
1198         /* init dai_driver and component_driver */
1199         ret = mtk_afe_combine_sub_dai(afe);
1200         if (ret) {
1201                 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
1202                          ret);
1203                 return ret;
1204         }
1205
1206         afe->mtk_afe_hardware = &mt8183_afe_hardware;
1207         afe->memif_fs = mt8183_memif_fs;
1208         afe->irq_fs = mt8183_irq_fs;
1209
1210         afe->runtime_resume = mt8183_afe_runtime_resume;
1211         afe->runtime_suspend = mt8183_afe_runtime_suspend;
1212
1213         /* register component */
1214         ret = devm_snd_soc_register_component(&pdev->dev,
1215                                               &mt8183_afe_component,
1216                                               NULL, 0);
1217         if (ret) {
1218                 dev_warn(dev, "err_platform\n");
1219                 return ret;
1220         }
1221
1222         ret = devm_snd_soc_register_component(afe->dev,
1223                                               &mt8183_afe_pcm_dai_component,
1224                                               afe->dai_drivers,
1225                                               afe->num_dai_drivers);
1226         if (ret) {
1227                 dev_warn(dev, "err_dai_component\n");
1228                 return ret;
1229         }
1230
1231         return ret;
1232 }
1233
1234 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
1235 {
1236         pm_runtime_disable(&pdev->dev);
1237         if (!pm_runtime_status_suspended(&pdev->dev))
1238                 mt8183_afe_runtime_suspend(&pdev->dev);
1239
1240         return 0;
1241 }
1242
1243 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
1244         { .compatible = "mediatek,mt8183-audio", },
1245         {},
1246 };
1247 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
1248
1249 static const struct dev_pm_ops mt8183_afe_pm_ops = {
1250         SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
1251                            mt8183_afe_runtime_resume, NULL)
1252 };
1253
1254 static struct platform_driver mt8183_afe_pcm_driver = {
1255         .driver = {
1256                    .name = "mt8183-audio",
1257                    .of_match_table = mt8183_afe_pcm_dt_match,
1258 #ifdef CONFIG_PM
1259                    .pm = &mt8183_afe_pm_ops,
1260 #endif
1261         },
1262         .probe = mt8183_afe_pcm_dev_probe,
1263         .remove = mt8183_afe_pcm_dev_remove,
1264 };
1265
1266 module_platform_driver(mt8183_afe_pcm_driver);
1267
1268 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
1269 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1270 MODULE_LICENSE("GPL v2");