1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel SST Haswell/Broadwell IPC Support
5 * Copyright (C) 2013, Intel Corporation. All rights reserved.
8 #ifndef __SST_HASWELL_IPC_H
9 #define __SST_HASWELL_IPC_H
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
14 #include <sound/asound.h>
16 #define DRV_NAME "haswell-dai"
18 #define SST_HSW_NO_CHANNELS 4
19 #define SST_HSW_MAX_DX_REGIONS 14
20 #define SST_HSW_DX_CONTEXT_SIZE (640 * 1024)
21 #define SST_HSW_CHANNELS_ALL 0xffffffff
23 #define SST_HSW_FW_LOG_CONFIG_DWORDS 12
24 #define SST_HSW_GLOBAL_LOG 15
27 * Upfront defined maximum message size that is
28 * expected by the in/out communication pipes in FW.
30 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400
31 #define SST_HSW_MAX_INFO_SIZE 64
32 #define SST_HSW_BUILD_HASH_LENGTH 40
33 #define SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE 500
34 #define WAVES_PARAM_COUNT 128
35 #define WAVES_PARAM_LINES 160
38 struct sst_hsw_stream;
39 struct sst_hsw_log_stream;
42 struct sst_module_runtime;
43 extern struct sst_ops haswell_ops;
45 /* Stream Allocate Path ID */
46 enum sst_hsw_stream_path_id {
47 SST_HSW_STREAM_PATH_SSP0_OUT = 0,
48 SST_HSW_STREAM_PATH_SSP0_IN = 1,
49 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
52 /* Stream Allocate Stream Type */
53 enum sst_hsw_stream_type {
54 SST_HSW_STREAM_TYPE_RENDER = 0,
55 SST_HSW_STREAM_TYPE_SYSTEM = 1,
56 SST_HSW_STREAM_TYPE_CAPTURE = 2,
57 SST_HSW_STREAM_TYPE_LOOPBACK = 3,
58 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
61 /* Stream Allocate Stream Format */
62 enum sst_hsw_stream_format {
63 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
64 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
65 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
66 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
70 enum sst_hsw_device_id {
71 SST_HSW_DEVICE_SSP_0 = 0,
72 SST_HSW_DEVICE_SSP_1 = 1,
75 /* Device Master Clock Frequency */
76 enum sst_hsw_device_mclk {
77 SST_HSW_DEVICE_MCLK_OFF = 0,
78 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1,
79 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
80 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
83 /* Device Clock Master */
84 enum sst_hsw_device_mode {
85 SST_HSW_DEVICE_CLOCK_SLAVE = 0,
86 SST_HSW_DEVICE_CLOCK_MASTER = 1,
87 SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
91 enum sst_hsw_dx_state {
92 SST_HSW_DX_STATE_D0 = 0,
93 SST_HSW_DX_STATE_D1 = 1,
94 SST_HSW_DX_STATE_D3 = 3,
95 SST_HSW_DX_STATE_MAX = 3,
98 /* Audio stream stage IDs */
99 enum sst_hsw_fx_stage_id {
100 SST_HSW_STAGE_ID_WAVES = 0,
101 SST_HSW_STAGE_ID_DTS = 1,
102 SST_HSW_STAGE_ID_DOLBY = 2,
103 SST_HSW_STAGE_ID_BOOST = 3,
104 SST_HSW_STAGE_ID_MAX_FX_ID
108 enum sst_hsw_dx_type {
109 SST_HSW_DX_TYPE_FW_IMAGE = 0,
110 SST_HSW_DX_TYPE_MEMORY_DUMP = 1
113 /* Volume Curve Type*/
114 enum sst_hsw_volume_curve {
115 SST_HSW_VOLUME_CURVE_NONE = 0,
116 SST_HSW_VOLUME_CURVE_FADE = 1
119 /* Sample ordering */
120 enum sst_hsw_interleaving {
121 SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
122 SST_HSW_INTERLEAVING_PER_SAMPLE = 1,
125 /* Channel indices */
126 enum sst_hsw_channel_index {
127 SST_HSW_CHANNEL_LEFT = 0,
128 SST_HSW_CHANNEL_CENTER = 1,
129 SST_HSW_CHANNEL_RIGHT = 2,
130 SST_HSW_CHANNEL_LEFT_SURROUND = 3,
131 SST_HSW_CHANNEL_CENTER_SURROUND = 3,
132 SST_HSW_CHANNEL_RIGHT_SURROUND = 4,
133 SST_HSW_CHANNEL_LFE = 7,
134 SST_HSW_CHANNEL_INVALID = 0xF,
137 /* List of supported channel maps. */
138 enum sst_hsw_channel_config {
139 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */
140 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */
141 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
142 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
143 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
144 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */
145 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
146 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
147 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
148 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
149 SST_HSW_CHANNEL_CONFIG_INVALID,
152 /* List of supported bit depths. */
153 enum sst_hsw_bitdepth {
154 SST_HSW_DEPTH_8BIT = 8,
155 SST_HSW_DEPTH_16BIT = 16,
156 SST_HSW_DEPTH_24BIT = 24, /* Default. */
157 SST_HSW_DEPTH_32BIT = 32,
158 SST_HSW_DEPTH_INVALID = 33,
161 enum sst_hsw_module_id {
162 SST_HSW_MODULE_BASE_FW = 0x0,
163 SST_HSW_MODULE_MP3 = 0x1,
164 SST_HSW_MODULE_AAC_5_1 = 0x2,
165 SST_HSW_MODULE_AAC_2_0 = 0x3,
166 SST_HSW_MODULE_SRC = 0x4,
167 SST_HSW_MODULE_WAVES = 0x5,
168 SST_HSW_MODULE_DOLBY = 0x6,
169 SST_HSW_MODULE_BOOST = 0x7,
170 SST_HSW_MODULE_LPAL = 0x8,
171 SST_HSW_MODULE_DTS = 0x9,
172 SST_HSW_MODULE_PCM_CAPTURE = 0xA,
173 SST_HSW_MODULE_PCM_SYSTEM = 0xB,
174 SST_HSW_MODULE_PCM_REFERENCE = 0xC,
175 SST_HSW_MODULE_PCM = 0xD,
176 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
177 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
178 SST_HSW_MAX_MODULE_ID,
181 enum sst_hsw_performance_action {
182 SST_HSW_PERF_START = 0,
183 SST_HSW_PERF_STOP = 1,
186 struct sst_hsw_transfer_info {
187 uint32_t destination; /* destination address */
188 uint32_t reverse:1; /* if 1 data flows from destination */
189 uint32_t size:31; /* transfer size in bytes.*/
190 uint16_t first_page_offset; /* offset to data in the first page. */
191 uint8_t packed_pages; /* page addresses. Each occupies 20 bits */
192 } __attribute__((packed));
194 struct sst_hsw_transfer_list {
195 uint32_t transfers_count;
196 struct sst_hsw_transfer_info transfers;
197 } __attribute__((packed));
199 struct sst_hsw_transfer_parameter {
200 uint32_t parameter_id;
204 struct sst_hsw_transfer_list transfer_list;
206 } __attribute__((packed));
208 /* SST firmware module info */
209 struct sst_hsw_module_info {
210 u8 name[SST_HSW_MAX_INFO_SIZE];
211 u8 version[SST_HSW_MAX_INFO_SIZE];
212 } __attribute__((packed));
214 /* Module entry point */
215 struct sst_hsw_module_entry {
216 enum sst_hsw_module_id module_id;
218 } __attribute__((packed));
220 /* Module map - alignement matches DSP */
221 struct sst_hsw_module_map {
222 u8 module_entries_count;
223 struct sst_hsw_module_entry module_entries[1];
224 } __attribute__((packed));
226 struct sst_hsw_memory_info {
229 } __attribute__((packed));
231 struct sst_hsw_fx_enable {
232 struct sst_hsw_module_map module_map;
233 struct sst_hsw_memory_info persistent_mem;
234 } __attribute__((packed));
236 struct sst_hsw_ipc_module_config {
237 struct sst_hsw_module_map map;
238 struct sst_hsw_memory_info persistent_mem;
239 struct sst_hsw_memory_info scratch_mem;
240 } __attribute__((packed));
242 struct sst_hsw_get_fx_param {
245 } __attribute__((packed));
247 struct sst_hsw_perf_action {
249 } __attribute__((packed));
251 struct sst_hsw_perf_data {
255 } __attribute__((packed));
258 struct sst_hsw_ipc_fw_version {
263 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
264 u32 fw_log_providers_hash;
265 } __attribute__((packed));
267 /* Stream ring info */
268 struct sst_hsw_ipc_stream_ring {
274 } __attribute__((packed));
276 /* Debug Dump Log Enable Request */
277 struct sst_hsw_ipc_debug_log_enable_req {
278 struct sst_hsw_ipc_stream_ring ringinfo;
279 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
280 } __attribute__((packed));
282 /* Debug Dump Log Reply */
283 struct sst_hsw_ipc_debug_log_reply {
284 u32 log_buffer_begining;
286 } __attribute__((packed));
288 /* Stream glitch position */
289 struct sst_hsw_ipc_stream_glitch_position {
293 } __attribute__((packed));
295 /* Stream get position */
296 struct sst_hsw_ipc_stream_get_position {
299 } __attribute__((packed));
301 /* Stream set position */
302 struct sst_hsw_ipc_stream_set_position {
305 } __attribute__((packed));
307 /* Stream Free Request */
308 struct sst_hsw_ipc_stream_free_req {
311 } __attribute__((packed));
313 /* Set Volume Request */
314 struct sst_hsw_ipc_volume_req {
319 } __attribute__((packed));
321 /* Device Configuration Request */
322 struct sst_hsw_ipc_device_config_req {
329 } __attribute__((packed));
331 /* Audio Data formats */
332 struct sst_hsw_audio_data_format_ipc {
341 } __attribute__((packed));
343 /* Stream Allocate Request */
344 struct sst_hsw_ipc_stream_alloc_req {
349 struct sst_hsw_audio_data_format_ipc format;
350 struct sst_hsw_ipc_stream_ring ringinfo;
351 struct sst_hsw_module_map map;
352 struct sst_hsw_memory_info persistent_mem;
353 struct sst_hsw_memory_info scratch_mem;
354 u32 number_of_notifications;
355 } __attribute__((packed));
357 /* Stream Allocate Reply */
358 struct sst_hsw_ipc_stream_alloc_reply {
360 u32 mixer_hw_id; // returns rate ????
361 u32 read_position_register_address;
362 u32 presentation_position_register_address;
363 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
364 u32 volume_register_address[SST_HSW_NO_CHANNELS];
365 } __attribute__((packed));
367 /* Get Mixer Stream Info */
368 struct sst_hsw_ipc_stream_info_reply {
370 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
371 u32 volume_register_address[SST_HSW_NO_CHANNELS];
372 } __attribute__((packed));
374 /* DX State Request */
375 struct sst_hsw_ipc_dx_req {
378 } __attribute__((packed));
380 /* DX State Reply Memory Info Item */
381 struct sst_hsw_ipc_dx_memory_item {
385 } __attribute__((packed));
388 struct sst_hsw_ipc_dx_reply {
390 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
391 } __attribute__((packed));
393 struct sst_hsw_ipc_fw_version;
395 /* SST Init & Free */
396 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
398 void sst_hsw_free(struct sst_hsw *hsw);
399 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
400 struct sst_hsw_ipc_fw_version *version);
401 u32 create_channel_map(enum sst_hsw_channel_config config);
403 /* Stream Mixer Controls - */
404 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
405 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
406 int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
407 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
409 /* Global Mixer Controls - */
410 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
412 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
416 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
417 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
420 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
422 /* Stream Configuration */
423 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
424 enum sst_hsw_stream_path_id path_id,
425 enum sst_hsw_stream_type stream_type,
426 enum sst_hsw_stream_format format_id);
428 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
429 u32 ring_pt_address, u32 num_pages,
430 u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
432 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
434 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
436 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
438 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
439 enum sst_hsw_bitdepth bits);
440 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
441 struct sst_hsw_stream *stream, int channels);
442 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
443 struct sst_hsw_stream *stream, u32 map,
444 enum sst_hsw_channel_config config);
445 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
446 enum sst_hsw_interleaving style);
447 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
448 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
449 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
450 struct sst_hsw_stream *stream, u32 offset, u32 size);
451 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
452 struct sst_hsw_stream *stream, u32 offset, u32 size);
453 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
454 struct sst_hsw_stream *stream);
455 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
456 struct sst_hsw_stream *stream, snd_pcm_uframes_t val);
457 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
458 struct sst_hsw_stream *stream);
459 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
460 struct sst_hsw_stream *stream, bool val);
461 int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
463 /* Stream ALSA trigger operations */
464 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
466 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
468 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
470 /* Stream pointer positions */
471 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
472 struct sst_hsw_stream *stream, u32 *position);
473 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
474 struct sst_hsw_stream *stream, u32 *position);
475 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
476 struct sst_hsw_stream *stream);
477 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
478 struct sst_hsw_stream *stream);
481 int sst_hsw_device_set_config(struct sst_hsw *hsw,
482 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
483 enum sst_hsw_device_mode mode, u32 clock_divider);
486 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
487 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
490 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
491 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
492 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
494 /* fw module function */
495 void sst_hsw_init_module_state(struct sst_hsw *hsw);
496 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id);
497 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id);
498 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id);
499 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id);
500 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id);
501 void sst_hsw_reset_param_buf(struct sst_hsw *hsw);
502 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf);
503 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf);
504 int sst_hsw_launch_param_buf(struct sst_hsw *hsw);
506 int sst_hsw_module_load(struct sst_hsw *hsw,
507 u32 module_id, u32 instance_id, char *name);
508 int sst_hsw_module_enable(struct sst_hsw *hsw,
509 u32 module_id, u32 instance_id);
510 int sst_hsw_module_disable(struct sst_hsw *hsw,
511 u32 module_id, u32 instance_id);
512 int sst_hsw_module_set_param(struct sst_hsw *hsw,
513 u32 module_id, u32 instance_id, u32 parameter_id,
514 u32 param_size, char *param);
516 /* runtime module management */
517 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
518 int mod_id, int offset);
519 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
522 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
523 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
524 int sst_hsw_dsp_load(struct sst_hsw *hsw);
525 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);