sound/soc/intel/haswell/sst-haswell-ipc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Intel SST Haswell/Broadwell IPC Support
   4  *
   5  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   6  */
   7
   8 #include <linux/types.h>
   9 #include <linux/kernel.h>
  10 #include <linux/list.h>
  11 #include <linux/device.h>
  12 #include <linux/wait.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/workqueue.h>
  15 #include <linux/export.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/sched.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/firmware.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/debugfs.h>
  23 #include <linux/pm_runtime.h>
  24 #include <sound/asound.h>
  25
  26 #include "sst-haswell-ipc.h"
  27 #include "../common/sst-dsp.h"
  28 #include "../common/sst-dsp-priv.h"
  29 #include "../common/sst-ipc.h"
  30
  31 /* Global Message - Generic */
  32 #define IPC_GLB_TYPE_SHIFT      24
  33 #define IPC_GLB_TYPE_MASK       (0x1f << IPC_GLB_TYPE_SHIFT)
  34 #define IPC_GLB_TYPE(x)         (x << IPC_GLB_TYPE_SHIFT)
  35
  36 /* Global Message - Reply */
  37 #define IPC_GLB_REPLY_SHIFT     0
  38 #define IPC_GLB_REPLY_MASK      (0x1f << IPC_GLB_REPLY_SHIFT)
  39 #define IPC_GLB_REPLY_TYPE(x)   (x << IPC_GLB_REPLY_TYPE_SHIFT)
  40
  41 /* Stream Message - Generic */
  42 #define IPC_STR_TYPE_SHIFT      20
  43 #define IPC_STR_TYPE_MASK       (0xf << IPC_STR_TYPE_SHIFT)
  44 #define IPC_STR_TYPE(x)         (x << IPC_STR_TYPE_SHIFT)
  45 #define IPC_STR_ID_SHIFT        16
  46 #define IPC_STR_ID_MASK         (0xf << IPC_STR_ID_SHIFT)
  47 #define IPC_STR_ID(x)           (x << IPC_STR_ID_SHIFT)
  48
  49 /* Stream Message - Reply */
  50 #define IPC_STR_REPLY_SHIFT     0
  51 #define IPC_STR_REPLY_MASK      (0x1f << IPC_STR_REPLY_SHIFT)
  52
  53 /* Stream Stage Message - Generic */
  54 #define IPC_STG_TYPE_SHIFT      12
  55 #define IPC_STG_TYPE_MASK       (0xf << IPC_STG_TYPE_SHIFT)
  56 #define IPC_STG_TYPE(x)         (x << IPC_STG_TYPE_SHIFT)
  57 #define IPC_STG_ID_SHIFT        10
  58 #define IPC_STG_ID_MASK         (0x3 << IPC_STG_ID_SHIFT)
  59 #define IPC_STG_ID(x)           (x << IPC_STG_ID_SHIFT)
  60
  61 /* Stream Stage Message - Reply */
  62 #define IPC_STG_REPLY_SHIFT     0
  63 #define IPC_STG_REPLY_MASK      (0x1f << IPC_STG_REPLY_SHIFT)
  64
  65 /* Debug Log Message - Generic */
  66 #define IPC_LOG_OP_SHIFT        20
  67 #define IPC_LOG_OP_MASK         (0xf << IPC_LOG_OP_SHIFT)
  68 #define IPC_LOG_OP_TYPE(x)      (x << IPC_LOG_OP_SHIFT)
  69 #define IPC_LOG_ID_SHIFT        16
  70 #define IPC_LOG_ID_MASK         (0xf << IPC_LOG_ID_SHIFT)
  71 #define IPC_LOG_ID(x)           (x << IPC_LOG_ID_SHIFT)
  72
  73 /* Module Message */
  74 #define IPC_MODULE_OPERATION_SHIFT      20
  75 #define IPC_MODULE_OPERATION_MASK       (0xf << IPC_MODULE_OPERATION_SHIFT)
  76 #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
  77
  78 #define IPC_MODULE_ID_SHIFT     16
  79 #define IPC_MODULE_ID_MASK      (0xf << IPC_MODULE_ID_SHIFT)
  80 #define IPC_MODULE_ID(x)        (x << IPC_MODULE_ID_SHIFT)
  81
  82 /* IPC message timeout (msecs) */
  83 #define IPC_TIMEOUT_MSECS       300
  84 #define IPC_BOOT_MSECS          200
  85 #define IPC_MSG_WAIT            0
  86 #define IPC_MSG_NOWAIT          1
  87
  88 /* Firmware Ready Message */
  89 #define IPC_FW_READY            (0x1 << 29)
  90 #define IPC_STATUS_MASK         (0x3 << 30)
  91
  92 #define IPC_EMPTY_LIST_SIZE     8
  93 #define IPC_MAX_STREAMS         4
  94
  95 /* Mailbox */
  96 #define IPC_MAX_MAILBOX_BYTES   256
  97
  98 #define INVALID_STREAM_HW_ID    0xffffffff
  99
 100 /* Global Message - Types and Replies */
 101 enum ipc_glb_type {
 102         IPC_GLB_GET_FW_VERSION = 0,             /* Retrieves firmware version */
 103         IPC_GLB_PERFORMANCE_MONITOR = 1,        /* Performance monitoring actions */
 104         IPC_GLB_ALLOCATE_STREAM = 3,            /* Request to allocate new stream */
 105         IPC_GLB_FREE_STREAM = 4,                /* Request to free stream */
 106         IPC_GLB_GET_FW_CAPABILITIES = 5,        /* Retrieves firmware capabilities */
 107         IPC_GLB_STREAM_MESSAGE = 6,             /* Message directed to stream or its stages */
 108         /* Request to store firmware context during D0->D3 transition */
 109         IPC_GLB_REQUEST_DUMP = 7,
 110         /* Request to restore firmware context during D3->D0 transition */
 111         IPC_GLB_RESTORE_CONTEXT = 8,
 112         IPC_GLB_GET_DEVICE_FORMATS = 9,         /* Set device format */
 113         IPC_GLB_SET_DEVICE_FORMATS = 10,        /* Get device format */
 114         IPC_GLB_SHORT_REPLY = 11,
 115         IPC_GLB_ENTER_DX_STATE = 12,
 116         IPC_GLB_GET_MIXER_STREAM_INFO = 13,     /* Request mixer stream params */
 117         IPC_GLB_DEBUG_LOG_MESSAGE = 14,         /* Message to or from the debug logger. */
 118         IPC_GLB_MODULE_OPERATION = 15,          /* Message to loadable fw module */
 119         IPC_GLB_REQUEST_TRANSFER = 16,          /* < Request Transfer for host */
 120         IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17,      /* Maximum message number */
 121 };
 122
 123 enum ipc_glb_reply {
 124         IPC_GLB_REPLY_SUCCESS = 0,              /* The operation was successful. */
 125         IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1,  /* Invalid parameter was passed. */
 126         IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
 127         IPC_GLB_REPLY_OUT_OF_RESOURCES = 3,     /* No resources to satisfy the request. */
 128         IPC_GLB_REPLY_BUSY = 4,                 /* The system or resource is busy. */
 129         IPC_GLB_REPLY_PENDING = 5,              /* The action was scheduled for processing.  */
 130         IPC_GLB_REPLY_FAILURE = 6,              /* Critical error happened. */
 131         IPC_GLB_REPLY_INVALID_REQUEST = 7,      /* Request can not be completed. */
 132         IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8,  /* Processing stage was uninitialized. */
 133         IPC_GLB_REPLY_NOT_FOUND = 9,            /* Required resource can not be found. */
 134         IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10,  /* Source was not started. */
 135 };
 136
 137 enum ipc_module_operation {
 138         IPC_MODULE_NOTIFICATION = 0,
 139         IPC_MODULE_ENABLE = 1,
 140         IPC_MODULE_DISABLE = 2,
 141         IPC_MODULE_GET_PARAMETER = 3,
 142         IPC_MODULE_SET_PARAMETER = 4,
 143         IPC_MODULE_GET_INFO = 5,
 144         IPC_MODULE_MAX_MESSAGE
 145 };
 146
 147 /* Stream Message - Types */
 148 enum ipc_str_operation {
 149         IPC_STR_RESET = 0,
 150         IPC_STR_PAUSE = 1,
 151         IPC_STR_RESUME = 2,
 152         IPC_STR_STAGE_MESSAGE = 3,
 153         IPC_STR_NOTIFICATION = 4,
 154         IPC_STR_MAX_MESSAGE
 155 };
 156
 157 /* Stream Stage Message Types */
 158 enum ipc_stg_operation {
 159         IPC_STG_GET_VOLUME = 0,
 160         IPC_STG_SET_VOLUME,
 161         IPC_STG_SET_WRITE_POSITION,
 162         IPC_STG_SET_FX_ENABLE,
 163         IPC_STG_SET_FX_DISABLE,
 164         IPC_STG_SET_FX_GET_PARAM,
 165         IPC_STG_SET_FX_SET_PARAM,
 166         IPC_STG_SET_FX_GET_INFO,
 167         IPC_STG_MUTE_LOOPBACK,
 168         IPC_STG_MAX_MESSAGE
 169 };
 170
 171 /* Stream Stage Message Types For Notification*/
 172 enum ipc_stg_operation_notify {
 173         IPC_POSITION_CHANGED = 0,
 174         IPC_STG_GLITCH,
 175         IPC_STG_MAX_NOTIFY
 176 };
 177
 178 enum ipc_glitch_type {
 179         IPC_GLITCH_UNDERRUN = 1,
 180         IPC_GLITCH_DECODER_ERROR,
 181         IPC_GLITCH_DOUBLED_WRITE_POS,
 182         IPC_GLITCH_MAX
 183 };
 184
 185 /* Debug Control */
 186 enum ipc_debug_operation {
 187         IPC_DEBUG_ENABLE_LOG = 0,
 188         IPC_DEBUG_DISABLE_LOG = 1,
 189         IPC_DEBUG_REQUEST_LOG_DUMP = 2,
 190         IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
 191         IPC_DEBUG_MAX_DEBUG_LOG
 192 };
 193
 194 /* Firmware Ready */
 195 struct sst_hsw_ipc_fw_ready {
 196         u32 inbox_offset;
 197         u32 outbox_offset;
 198         u32 inbox_size;
 199         u32 outbox_size;
 200         u32 fw_info_size;
 201         u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 202 } __attribute__((packed));
 203
 204 struct sst_hsw_stream;
 205 struct sst_hsw;
 206
 207 /* Stream infomation */
 208 struct sst_hsw_stream {
 209         /* configuration */
 210         struct sst_hsw_ipc_stream_alloc_req request;
 211         struct sst_hsw_ipc_stream_alloc_reply reply;
 212         struct sst_hsw_ipc_stream_free_req free_req;
 213
 214         /* Mixer info */
 215         u32 mute_volume[SST_HSW_NO_CHANNELS];
 216         u32 mute[SST_HSW_NO_CHANNELS];
 217
 218         /* runtime info */
 219         struct sst_hsw *hsw;
 220         int host_id;
 221         bool commited;
 222         bool running;
 223
 224         /* Notification work */
 225         struct work_struct notify_work;
 226         u32 header;
 227
 228         /* Position info from DSP */
 229         struct sst_hsw_ipc_stream_set_position wpos;
 230         struct sst_hsw_ipc_stream_get_position rpos;
 231         struct sst_hsw_ipc_stream_glitch_position glitch;
 232
 233         /* Volume info */
 234         struct sst_hsw_ipc_volume_req vol_req;
 235
 236         /* driver callback */
 237         u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
 238         void *pdata;
 239
 240         /* record the fw read position when playback */
 241         snd_pcm_uframes_t old_position;
 242         bool play_silence;
 243         struct list_head node;
 244 };
 245
 246 /* FW log ring information */
 247 struct sst_hsw_log_stream {
 248         dma_addr_t dma_addr;
 249         unsigned char *dma_area;
 250         unsigned char *ring_descr;
 251         int pages;
 252         int size;
 253
 254         /* Notification work */
 255         struct work_struct notify_work;
 256         wait_queue_head_t readers_wait_q;
 257         struct mutex rw_mutex;
 258
 259         u32 last_pos;
 260         u32 curr_pos;
 261         u32 reader_pos;
 262
 263         /* fw log config */
 264         u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
 265
 266         struct sst_hsw *hsw;
 267 };
 268
 269 /* SST Haswell IPC data */
 270 struct sst_hsw {
 271         struct device *dev;
 272         struct sst_dsp *dsp;
 273         struct platform_device *pdev_pcm;
 274
 275         /* FW config */
 276         struct sst_hsw_ipc_fw_ready fw_ready;
 277         struct sst_hsw_ipc_fw_version version;
 278         bool fw_done;
 279         struct sst_fw *sst_fw;
 280
 281         /* stream */
 282         struct list_head stream_list;
 283
 284         /* global mixer */
 285         struct sst_hsw_ipc_stream_info_reply mixer_info;
 286         enum sst_hsw_volume_curve curve_type;
 287         u32 curve_duration;
 288         u32 mute[SST_HSW_NO_CHANNELS];
 289         u32 mute_volume[SST_HSW_NO_CHANNELS];
 290
 291         /* DX */
 292         struct sst_hsw_ipc_dx_reply dx;
 293         void *dx_context;
 294         dma_addr_t dx_context_paddr;
 295         enum sst_hsw_device_id dx_dev;
 296         enum sst_hsw_device_mclk dx_mclk;
 297         enum sst_hsw_device_mode dx_mode;
 298         u32 dx_clock_divider;
 299
 300         /* boot */
 301         wait_queue_head_t boot_wait;
 302         bool boot_complete;
 303         bool shutdown;
 304
 305         /* IPC messaging */
 306         struct sst_generic_ipc ipc;
 307
 308         /* FW log stream */
 309         struct sst_hsw_log_stream log_stream;
 310
 311         /* flags bit field to track module state when resume from RTD3,
 312          * each bit represent state (enabled/disabled) of single module */
 313         u32 enabled_modules_rtd3;
 314
 315         /* buffer to store parameter lines */
 316         u32 param_idx_w;        /* write index */
 317         u32 param_idx_r;        /* read index */
 318         u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
 319 };
 320
 321 #define CREATE_TRACE_POINTS
 322 #include <trace/events/hswadsp.h>
 323
 324 static inline u32 msg_get_global_type(u32 msg)
 325 {
 326         return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
 327 }
 328
 329 static inline u32 msg_get_global_reply(u32 msg)
 330 {
 331         return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
 332 }
 333
 334 static inline u32 msg_get_stream_type(u32 msg)
 335 {
 336         return (msg & IPC_STR_TYPE_MASK) >>  IPC_STR_TYPE_SHIFT;
 337 }
 338
 339 static inline u32 msg_get_stream_id(u32 msg)
 340 {
 341         return (msg & IPC_STR_ID_MASK) >>  IPC_STR_ID_SHIFT;
 342 }
 343
 344 static inline u32 msg_get_notify_reason(u32 msg)
 345 {
 346         return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
 347 }
 348
 349 static inline u32 msg_get_module_operation(u32 msg)
 350 {
 351         return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
 352 }
 353
 354 static inline u32 msg_get_module_id(u32 msg)
 355 {
 356         return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
 357 }
 358
 359 u32 create_channel_map(enum sst_hsw_channel_config config)
 360 {
 361         switch (config) {
 362         case SST_HSW_CHANNEL_CONFIG_MONO:
 363                 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
 364         case SST_HSW_CHANNEL_CONFIG_STEREO:
 365                 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 366                         | (SST_HSW_CHANNEL_RIGHT << 4));
 367         case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
 368                 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 369                         | (SST_HSW_CHANNEL_RIGHT << 4)
 370                         | (SST_HSW_CHANNEL_LFE << 8 ));
 371         case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
 372                 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 373                         | (SST_HSW_CHANNEL_CENTER << 4)
 374                         | (SST_HSW_CHANNEL_RIGHT << 8));
 375         case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
 376                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 377                         | (SST_HSW_CHANNEL_CENTER << 4)
 378                         | (SST_HSW_CHANNEL_RIGHT << 8)
 379                         | (SST_HSW_CHANNEL_LFE << 12));
 380         case SST_HSW_CHANNEL_CONFIG_QUATRO:
 381                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 382                         | (SST_HSW_CHANNEL_RIGHT << 4)
 383                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
 384                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
 385         case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
 386                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 387                         | (SST_HSW_CHANNEL_CENTER << 4)
 388                         | (SST_HSW_CHANNEL_RIGHT << 8)
 389                         | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
 390         case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
 391                 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
 392                         | (SST_HSW_CHANNEL_CENTER << 4)
 393                         | (SST_HSW_CHANNEL_RIGHT << 8)
 394                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 395                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
 396         case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
 397                 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
 398                         | (SST_HSW_CHANNEL_LEFT << 4)
 399                         | (SST_HSW_CHANNEL_RIGHT << 8)
 400                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 401                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
 402                         | (SST_HSW_CHANNEL_LFE << 20));
 403         case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
 404                 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 405                         | (SST_HSW_CHANNEL_LEFT << 4));
 406         default:
 407                 return 0xFFFFFFFF;
 408         }
 409 }
 410
 411 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
 412         int stream_id)
 413 {
 414         struct sst_hsw_stream *stream;
 415
 416         list_for_each_entry(stream, &hsw->stream_list, node) {
 417                 if (stream->reply.stream_hw_id == stream_id)
 418                         return stream;
 419         }
 420
 421         return NULL;
 422 }
 423
 424 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
 425 {
 426         struct sst_hsw_ipc_fw_ready fw_ready;
 427         u32 offset;
 428         u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 429         char *tmp[5], *pinfo;
 430         int i = 0;
 431
 432         offset = (header & 0x1FFFFFFF) << 3;
 433
 434         dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
 435                 header, offset);
 436
 437         /* copy data from the DSP FW ready offset */
 438         sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
 439
 440         sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
 441                 fw_ready.inbox_size, fw_ready.outbox_offset,
 442                 fw_ready.outbox_size);
 443
 444         hsw->boot_complete = true;
 445         wake_up(&hsw->boot_wait);
 446
 447         dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
 448                 fw_ready.inbox_offset, fw_ready.inbox_size);
 449         dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
 450                 fw_ready.outbox_offset, fw_ready.outbox_size);
 451         if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
 452                 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
 453                 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
 454
 455                 /* log the FW version info got from the mailbox here. */
 456                 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
 457                 pinfo = &fw_info[0];
 458                 for (i = 0; i < ARRAY_SIZE(tmp); i++)
 459                         tmp[i] = strsep(&pinfo, " ");
 460                 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
 461                         "version: %s.%s, build %s, source commit id: %s\n",
 462                         tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
 463         }
 464 }
 465
 466 static void hsw_notification_work(struct work_struct *work)
 467 {
 468         struct sst_hsw_stream *stream = container_of(work,
 469                         struct sst_hsw_stream, notify_work);
 470         struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
 471         struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
 472         struct sst_hsw *hsw = stream->hsw;
 473         u32 reason;
 474
 475         reason = msg_get_notify_reason(stream->header);
 476
 477         switch (reason) {
 478         case IPC_STG_GLITCH:
 479                 trace_ipc_notification("DSP stream under/overrun",
 480                         stream->reply.stream_hw_id);
 481                 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
 482
 483                 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
 484                         glitch->glitch_type, glitch->present_pos,
 485                         glitch->write_pos);
 486                 break;
 487
 488         case IPC_POSITION_CHANGED:
 489                 trace_ipc_notification("DSP stream position changed for",
 490                         stream->reply.stream_hw_id);
 491                 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
 492
 493                 if (stream->notify_position)
 494                         stream->notify_position(stream, stream->pdata);
 495
 496                 break;
 497         default:
 498                 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
 499                         stream->header);
 500                 break;
 501         }
 502
 503         /* tell DSP that notification has been handled */
 504         sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
 505                 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 506
 507         /* unmask busy interrupt */
 508         sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
 509 }
 510
 511 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
 512 {
 513         struct sst_hsw_stream *stream;
 514         u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
 515         u32 stream_id = msg_get_stream_id(header);
 516         u32 stream_msg = msg_get_stream_type(header);
 517
 518         stream = get_stream_by_id(hsw, stream_id);
 519         if (stream == NULL)
 520                 return;
 521
 522         switch (stream_msg) {
 523         case IPC_STR_STAGE_MESSAGE:
 524         case IPC_STR_NOTIFICATION:
 525                 break;
 526         case IPC_STR_RESET:
 527                 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
 528                 break;
 529         case IPC_STR_PAUSE:
 530                 stream->running = false;
 531                 trace_ipc_notification("stream paused",
 532                         stream->reply.stream_hw_id);
 533                 break;
 534         case IPC_STR_RESUME:
 535                 stream->running = true;
 536                 trace_ipc_notification("stream running",
 537                         stream->reply.stream_hw_id);
 538                 break;
 539         }
 540 }
 541
 542 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
 543 {
 544         struct ipc_message *msg;
 545         u32 reply = msg_get_global_reply(header);
 546
 547         trace_ipc_reply("processing -->", header);
 548
 549         msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
 550         if (msg == NULL) {
 551                 trace_ipc_error("error: can't find message header", header);
 552                 return -EIO;
 553         }
 554
 555         /* first process the header */
 556         switch (reply) {
 557         case IPC_GLB_REPLY_PENDING:
 558                 trace_ipc_pending_reply("received", header);
 559                 msg->pending = true;
 560                 hsw->ipc.pending = true;
 561                 return 1;
 562         case IPC_GLB_REPLY_SUCCESS:
 563                 if (msg->pending) {
 564                         trace_ipc_pending_reply("completed", header);
 565                         sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
 566                                 msg->rx_size);
 567                         hsw->ipc.pending = false;
 568                 } else {
 569                         /* copy data from the DSP */
 570                         sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
 571                                 msg->rx_size);
 572                 }
 573                 break;
 574         /* these will be rare - but useful for debug */
 575         case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
 576                 trace_ipc_error("error: unknown message type", header);
 577                 msg->errno = -EBADMSG;
 578                 break;
 579         case IPC_GLB_REPLY_OUT_OF_RESOURCES:
 580                 trace_ipc_error("error: out of resources", header);
 581                 msg->errno = -ENOMEM;
 582                 break;
 583         case IPC_GLB_REPLY_BUSY:
 584                 trace_ipc_error("error: reply busy", header);
 585                 msg->errno = -EBUSY;
 586                 break;
 587         case IPC_GLB_REPLY_FAILURE:
 588                 trace_ipc_error("error: reply failure", header);
 589                 msg->errno = -EINVAL;
 590                 break;
 591         case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
 592                 trace_ipc_error("error: stage uninitialized", header);
 593                 msg->errno = -EINVAL;
 594                 break;
 595         case IPC_GLB_REPLY_NOT_FOUND:
 596                 trace_ipc_error("error: reply not found", header);
 597                 msg->errno = -EINVAL;
 598                 break;
 599         case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
 600                 trace_ipc_error("error: source not started", header);
 601                 msg->errno = -EINVAL;
 602                 break;
 603         case IPC_GLB_REPLY_INVALID_REQUEST:
 604                 trace_ipc_error("error: invalid request", header);
 605                 msg->errno = -EINVAL;
 606                 break;
 607         case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
 608                 trace_ipc_error("error: invalid parameter", header);
 609                 msg->errno = -EINVAL;
 610                 break;
 611         default:
 612                 trace_ipc_error("error: unknown reply", header);
 613                 msg->errno = -EINVAL;
 614                 break;
 615         }
 616
 617         /* update any stream states */
 618         if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
 619                 hsw_stream_update(hsw, msg);
 620
 621         /* wake up and return the error if we have waiters on this message ? */
 622         list_del(&msg->list);
 623         sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
 624
 625         return 1;
 626 }
 627
 628 static int hsw_module_message(struct sst_hsw *hsw, u32 header)
 629 {
 630         u32 operation, module_id;
 631         int handled = 0;
 632
 633         operation = msg_get_module_operation(header);
 634         module_id = msg_get_module_id(header);
 635         dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
 636                         header);
 637         dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
 638                         operation, module_id);
 639
 640         switch (operation) {
 641         case IPC_MODULE_NOTIFICATION:
 642                 dev_dbg(hsw->dev, "module notification received");
 643                 handled = 1;
 644                 break;
 645         default:
 646                 handled = hsw_process_reply(hsw, header);
 647                 break;
 648         }
 649
 650         return handled;
 651 }
 652
 653 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
 654 {
 655         u32 stream_msg, stream_id;
 656         struct sst_hsw_stream *stream;
 657         int handled = 0;
 658
 659         stream_msg = msg_get_stream_type(header);
 660         stream_id = msg_get_stream_id(header);
 661
 662         stream = get_stream_by_id(hsw, stream_id);
 663         if (stream == NULL)
 664                 return handled;
 665
 666         stream->header = header;
 667
 668         switch (stream_msg) {
 669         case IPC_STR_STAGE_MESSAGE:
 670                 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
 671                         header);
 672                 break;
 673         case IPC_STR_NOTIFICATION:
 674                 schedule_work(&stream->notify_work);
 675                 break;
 676         default:
 677                 /* handle pending message complete request */
 678                 handled = hsw_process_reply(hsw, header);
 679                 break;
 680         }
 681
 682         return handled;
 683 }
 684
 685 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
 686 {
 687         u32 operation = (header & IPC_LOG_OP_MASK) >>  IPC_LOG_OP_SHIFT;
 688         struct sst_hsw_log_stream *stream = &hsw->log_stream;
 689         int ret = 1;
 690
 691         if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
 692                 dev_err(hsw->dev,
 693                         "error: log msg not implemented 0x%8.8x\n", header);
 694                 return 0;
 695         }
 696
 697         mutex_lock(&stream->rw_mutex);
 698         stream->last_pos = stream->curr_pos;
 699         sst_dsp_inbox_read(
 700                 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
 701         mutex_unlock(&stream->rw_mutex);
 702
 703         schedule_work(&stream->notify_work);
 704
 705         return ret;
 706 }
 707
 708 static int hsw_process_notification(struct sst_hsw *hsw)
 709 {
 710         struct sst_dsp *sst = hsw->dsp;
 711         u32 type, header;
 712         int handled = 1;
 713
 714         header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 715         type = msg_get_global_type(header);
 716
 717         trace_ipc_request("processing -->", header);
 718
 719         /* FW Ready is a special case */
 720         if (!hsw->boot_complete && header & IPC_FW_READY) {
 721                 hsw_fw_ready(hsw, header);
 722                 return handled;
 723         }
 724
 725         switch (type) {
 726         case IPC_GLB_GET_FW_VERSION:
 727         case IPC_GLB_ALLOCATE_STREAM:
 728         case IPC_GLB_FREE_STREAM:
 729         case IPC_GLB_GET_FW_CAPABILITIES:
 730         case IPC_GLB_REQUEST_DUMP:
 731         case IPC_GLB_GET_DEVICE_FORMATS:
 732         case IPC_GLB_SET_DEVICE_FORMATS:
 733         case IPC_GLB_ENTER_DX_STATE:
 734         case IPC_GLB_GET_MIXER_STREAM_INFO:
 735         case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
 736         case IPC_GLB_RESTORE_CONTEXT:
 737         case IPC_GLB_SHORT_REPLY:
 738                 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
 739                         type, header);
 740                 break;
 741         case IPC_GLB_STREAM_MESSAGE:
 742                 handled = hsw_stream_message(hsw, header);
 743                 break;
 744         case IPC_GLB_DEBUG_LOG_MESSAGE:
 745                 handled = hsw_log_message(hsw, header);
 746                 break;
 747         case IPC_GLB_MODULE_OPERATION:
 748                 handled = hsw_module_message(hsw, header);
 749                 break;
 750         default:
 751                 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
 752                         type, header);
 753                 break;
 754         }
 755
 756         return handled;
 757 }
 758
 759 static irqreturn_t hsw_irq_thread(int irq, void *context)
 760 {
 761         struct sst_dsp *sst = (struct sst_dsp *) context;
 762         struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
 763         struct sst_generic_ipc *ipc = &hsw->ipc;
 764         u32 ipcx, ipcd;
 765         unsigned long flags;
 766
 767         spin_lock_irqsave(&sst->spinlock, flags);
 768
 769         ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
 770         ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 771
 772         /* reply message from DSP */
 773         if (ipcx & SST_IPCX_DONE) {
 774
 775                 /* Handle Immediate reply from DSP Core */
 776                 hsw_process_reply(hsw, ipcx);
 777
 778                 /* clear DONE bit - tell DSP we have completed */
 779                 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
 780                         SST_IPCX_DONE, 0);
 781
 782                 /* unmask Done interrupt */
 783                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 784                         SST_IMRX_DONE, 0);
 785         }
 786
 787         /* new message from DSP */
 788         if (ipcd & SST_IPCD_BUSY) {
 789
 790                 /* Handle Notification and Delayed reply from DSP Core */
 791                 hsw_process_notification(hsw);
 792
 793                 /* clear BUSY bit and set DONE bit - accept new messages */
 794                 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
 795                         SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 796
 797                 /* unmask busy interrupt */
 798                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 799                         SST_IMRX_BUSY, 0);
 800         }
 801
 802         spin_unlock_irqrestore(&sst->spinlock, flags);
 803
 804         /* continue to send any remaining messages... */
 805         schedule_work(&ipc->kwork);
 806
 807         return IRQ_HANDLED;
 808 }
 809
 810 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
 811         struct sst_hsw_ipc_fw_version *version)
 812 {
 813         int ret;
 814
 815         ret = sst_ipc_tx_message_wait(&hsw->ipc,
 816                 IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
 817                 NULL, 0, version, sizeof(*version));
 818         if (ret < 0)
 819                 dev_err(hsw->dev, "error: get version failed\n");
 820
 821         return ret;
 822 }
 823
 824 /* Mixer Controls */
 825 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 826         u32 stage_id, u32 channel, u32 *volume)
 827 {
 828         if (channel > 1)
 829                 return -EINVAL;
 830
 831         sst_dsp_read(hsw->dsp, volume,
 832                 stream->reply.volume_register_address[channel],
 833                 sizeof(*volume));
 834
 835         return 0;
 836 }
 837
 838 /* stream volume */
 839 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
 840         struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
 841 {
 842         struct sst_hsw_ipc_volume_req *req;
 843         u32 header;
 844         int ret;
 845
 846         trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
 847
 848         if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
 849                 return -EINVAL;
 850
 851         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
 852                 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
 853         header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
 854         header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
 855         header |= (stage_id << IPC_STG_ID_SHIFT);
 856
 857         req = &stream->vol_req;
 858         req->target_volume = volume;
 859
 860         /* set both at same time ? */
 861         if (channel == SST_HSW_CHANNELS_ALL) {
 862                 if (hsw->mute[0] && hsw->mute[1]) {
 863                         hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
 864                         return 0;
 865                 } else if (hsw->mute[0])
 866                         req->channel = 1;
 867                 else if (hsw->mute[1])
 868                         req->channel = 0;
 869                 else
 870                         req->channel = SST_HSW_CHANNELS_ALL;
 871         } else {
 872                 /* set only 1 channel */
 873                 if (hsw->mute[channel]) {
 874                         hsw->mute_volume[channel] = volume;
 875                         return 0;
 876                 }
 877                 req->channel = channel;
 878         }
 879
 880         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
 881                 sizeof(*req), NULL, 0);
 882         if (ret < 0) {
 883                 dev_err(hsw->dev, "error: set stream volume failed\n");
 884                 return ret;
 885         }
 886
 887         return 0;
 888 }
 889
 890 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 891         u32 *volume)
 892 {
 893         if (channel > 1)
 894                 return -EINVAL;
 895
 896         sst_dsp_read(hsw->dsp, volume,
 897                 hsw->mixer_info.volume_register_address[channel],
 898                 sizeof(*volume));
 899
 900         return 0;
 901 }
 902
 903 /* global mixer volume */
 904 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 905         u32 volume)
 906 {
 907         struct sst_hsw_ipc_volume_req req;
 908         u32 header;
 909         int ret;
 910
 911         trace_ipc_request("set mixer volume", volume);
 912
 913         if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
 914                 return -EINVAL;
 915
 916         /* set both at same time ? */
 917         if (channel == SST_HSW_CHANNELS_ALL) {
 918                 if (hsw->mute[0] && hsw->mute[1]) {
 919                         hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
 920                         return 0;
 921                 } else if (hsw->mute[0])
 922                         req.channel = 1;
 923                 else if (hsw->mute[1])
 924                         req.channel = 0;
 925                 else
 926                         req.channel = SST_HSW_CHANNELS_ALL;
 927         } else {
 928                 /* set only 1 channel */
 929                 if (hsw->mute[channel]) {
 930                         hsw->mute_volume[channel] = volume;
 931                         return 0;
 932                 }
 933                 req.channel = channel;
 934         }
 935
 936         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
 937                 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
 938         header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
 939         header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
 940         header |= (stage_id << IPC_STG_ID_SHIFT);
 941
 942         req.curve_duration = hsw->curve_duration;
 943         req.curve_type = hsw->curve_type;
 944         req.target_volume = volume;
 945
 946         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
 947                 sizeof(req), NULL, 0);
 948         if (ret < 0) {
 949                 dev_err(hsw->dev, "error: set mixer volume failed\n");
 950                 return ret;
 951         }
 952
 953         return 0;
 954 }
 955
 956 /* Stream API */
 957 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
 958         u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
 959         void *data)
 960 {
 961         struct sst_hsw_stream *stream;
 962         struct sst_dsp *sst = hsw->dsp;
 963         unsigned long flags;
 964
 965         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 966         if (stream == NULL)
 967                 return NULL;
 968
 969         spin_lock_irqsave(&sst->spinlock, flags);
 970         stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
 971         list_add(&stream->node, &hsw->stream_list);
 972         stream->notify_position = notify_position;
 973         stream->pdata = data;
 974         stream->hsw = hsw;
 975         stream->host_id = id;
 976
 977         /* work to process notification messages */
 978         INIT_WORK(&stream->notify_work, hsw_notification_work);
 979         spin_unlock_irqrestore(&sst->spinlock, flags);
 980
 981         return stream;
 982 }
 983
 984 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
 985 {
 986         u32 header;
 987         int ret = 0;
 988         struct sst_dsp *sst = hsw->dsp;
 989         unsigned long flags;
 990
 991         if (!stream) {
 992                 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
 993                 return 0;
 994         }
 995
 996         /* dont free DSP streams that are not commited */
 997         if (!stream->commited)
 998                 goto out;
 999
1000         trace_ipc_request("stream free", stream->host_id);
1001
1002         stream->free_req.stream_id = stream->reply.stream_hw_id;
1003         header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1004
1005         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
1006                 sizeof(stream->free_req), NULL, 0);
1007         if (ret < 0) {
1008                 dev_err(hsw->dev, "error: free stream %d failed\n",
1009                         stream->free_req.stream_id);
1010                 return -EAGAIN;
1011         }
1012
1013         trace_hsw_stream_free_req(stream, &stream->free_req);
1014
1015 out:
1016         cancel_work_sync(&stream->notify_work);
1017         spin_lock_irqsave(&sst->spinlock, flags);
1018         list_del(&stream->node);
1019         kfree(stream);
1020         spin_unlock_irqrestore(&sst->spinlock, flags);
1021
1022         return ret;
1023 }
1024
1025 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1026         struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1027 {
1028         if (stream->commited) {
1029                 dev_err(hsw->dev, "error: stream committed for set bits\n");
1030                 return -EINVAL;
1031         }
1032
1033         stream->request.format.bitdepth = bits;
1034         return 0;
1035 }
1036
1037 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1038         struct sst_hsw_stream *stream, int channels)
1039 {
1040         if (stream->commited) {
1041                 dev_err(hsw->dev, "error: stream committed for set channels\n");
1042                 return -EINVAL;
1043         }
1044
1045         stream->request.format.ch_num = channels;
1046         return 0;
1047 }
1048
1049 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1050         struct sst_hsw_stream *stream, int rate)
1051 {
1052         if (stream->commited) {
1053                 dev_err(hsw->dev, "error: stream committed for set rate\n");
1054                 return -EINVAL;
1055         }
1056
1057         stream->request.format.frequency = rate;
1058         return 0;
1059 }
1060
1061 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1062         struct sst_hsw_stream *stream, u32 map,
1063         enum sst_hsw_channel_config config)
1064 {
1065         if (stream->commited) {
1066                 dev_err(hsw->dev, "error: stream committed for set map\n");
1067                 return -EINVAL;
1068         }
1069
1070         stream->request.format.map = map;
1071         stream->request.format.config = config;
1072         return 0;
1073 }
1074
1075 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1076         struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1077 {
1078         if (stream->commited) {
1079                 dev_err(hsw->dev, "error: stream committed for set style\n");
1080                 return -EINVAL;
1081         }
1082
1083         stream->request.format.style = style;
1084         return 0;
1085 }
1086
1087 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1088         struct sst_hsw_stream *stream, u32 bits)
1089 {
1090         if (stream->commited) {
1091                 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1092                 return -EINVAL;
1093         }
1094
1095         stream->request.format.valid_bit = bits;
1096         return 0;
1097 }
1098
1099 /* Stream Configuration */
1100 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1101         enum sst_hsw_stream_path_id path_id,
1102         enum sst_hsw_stream_type stream_type,
1103         enum sst_hsw_stream_format format_id)
1104 {
1105         if (stream->commited) {
1106                 dev_err(hsw->dev, "error: stream committed for set format\n");
1107                 return -EINVAL;
1108         }
1109
1110         stream->request.path_id = path_id;
1111         stream->request.stream_type = stream_type;
1112         stream->request.format_id = format_id;
1113
1114         trace_hsw_stream_alloc_request(stream, &stream->request);
1115
1116         return 0;
1117 }
1118
1119 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1120         u32 ring_pt_address, u32 num_pages,
1121         u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1122 {
1123         if (stream->commited) {
1124                 dev_err(hsw->dev, "error: stream committed for buffer\n");
1125                 return -EINVAL;
1126         }
1127
1128         stream->request.ringinfo.ring_pt_address = ring_pt_address;
1129         stream->request.ringinfo.num_pages = num_pages;
1130         stream->request.ringinfo.ring_size = ring_size;
1131         stream->request.ringinfo.ring_offset = ring_offset;
1132         stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1133
1134         trace_hsw_stream_buffer(stream);
1135
1136         return 0;
1137 }
1138
1139 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1140         struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1141 {
1142         struct sst_hsw_module_map *map = &stream->request.map;
1143         struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1144         struct sst_module *module = runtime->module;
1145
1146         if (stream->commited) {
1147                 dev_err(hsw->dev, "error: stream committed for set module\n");
1148                 return -EINVAL;
1149         }
1150
1151         /* only support initial module atm */
1152         map->module_entries_count = 1;
1153         map->module_entries[0].module_id = module->id;
1154         map->module_entries[0].entry_point = module->entry;
1155
1156         stream->request.persistent_mem.offset =
1157                 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1158         stream->request.persistent_mem.size = module->persistent_size;
1159
1160         stream->request.scratch_mem.offset =
1161                 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1162         stream->request.scratch_mem.size = dsp->scratch_size;
1163
1164         dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1165                 runtime->id);
1166         dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1167                 stream->request.persistent_mem.offset,
1168                 stream->request.persistent_mem.size);
1169         dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1170                 stream->request.scratch_mem.offset,
1171                 stream->request.scratch_mem.size);
1172
1173         return 0;
1174 }
1175
1176 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1177 {
1178         struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1179         struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1180         u32 header;
1181         int ret;
1182
1183         if (!stream) {
1184                 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1185                 return 0;
1186         }
1187
1188         if (stream->commited) {
1189                 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1190                 return 0;
1191         }
1192
1193         trace_ipc_request("stream alloc", stream->host_id);
1194
1195         header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1196
1197         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1198                 sizeof(*str_req), reply, sizeof(*reply));
1199         if (ret < 0) {
1200                 dev_err(hsw->dev, "error: stream commit failed\n");
1201                 return ret;
1202         }
1203
1204         stream->commited = true;
1205         trace_hsw_stream_alloc_reply(stream);
1206
1207         return 0;
1208 }
1209
1210 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1211         struct sst_hsw_stream *stream)
1212 {
1213         return stream->old_position;
1214 }
1215
1216 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1217         struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1218 {
1219         stream->old_position = val;
1220 }
1221
1222 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1223         struct sst_hsw_stream *stream)
1224 {
1225         return stream->play_silence;
1226 }
1227
1228 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1229         struct sst_hsw_stream *stream, bool val)
1230 {
1231         stream->play_silence = val;
1232 }
1233
1234 /* Stream Information - these calls could be inline but we want the IPC
1235  ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1236 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1237 {
1238         struct sst_hsw_ipc_stream_info_reply *reply;
1239         u32 header;
1240         int ret;
1241
1242         reply = &hsw->mixer_info;
1243         header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1244
1245         trace_ipc_request("get global mixer info", 0);
1246
1247         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1248                 reply, sizeof(*reply));
1249         if (ret < 0) {
1250                 dev_err(hsw->dev, "error: get stream info failed\n");
1251                 return ret;
1252         }
1253
1254         trace_hsw_mixer_info_reply(reply);
1255
1256         return 0;
1257 }
1258
1259 /* Send stream command */
1260 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1261         int stream_id, int wait)
1262 {
1263         u32 header;
1264
1265         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1266         header |= (stream_id << IPC_STR_ID_SHIFT);
1267
1268         if (wait)
1269                 return sst_ipc_tx_message_wait(&hsw->ipc, header,
1270                         NULL, 0, NULL, 0);
1271         else
1272                 return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
1273 }
1274
1275 /* Stream ALSA trigger operations */
1276 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1277         int wait)
1278 {
1279         int ret;
1280
1281         if (!stream) {
1282                 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1283                 return 0;
1284         }
1285
1286         trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1287
1288         ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1289                 stream->reply.stream_hw_id, wait);
1290         if (ret < 0)
1291                 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1292                         stream->reply.stream_hw_id);
1293
1294         return ret;
1295 }
1296
1297 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1298         int wait)
1299 {
1300         int ret;
1301
1302         if (!stream) {
1303                 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1304                 return 0;
1305         }
1306
1307         trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1308
1309         ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1310                 stream->reply.stream_hw_id, wait);
1311         if (ret < 0)
1312                 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1313                         stream->reply.stream_hw_id);
1314
1315         return ret;
1316 }
1317
1318 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1319 {
1320         int ret, tries = 10;
1321
1322         if (!stream) {
1323                 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1324                 return 0;
1325         }
1326
1327         /* dont reset streams that are not commited */
1328         if (!stream->commited)
1329                 return 0;
1330
1331         /* wait for pause to complete before we reset the stream */
1332         while (stream->running && --tries)
1333                 msleep(1);
1334         if (!tries) {
1335                 dev_err(hsw->dev, "error: reset stream %d still running\n",
1336                         stream->reply.stream_hw_id);
1337                 return -EINVAL;
1338         }
1339
1340         trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1341
1342         ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1343                 stream->reply.stream_hw_id, 1);
1344         if (ret < 0)
1345                 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1346                         stream->reply.stream_hw_id);
1347         return ret;
1348 }
1349
1350 /* Stream pointer positions */
1351 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1352         struct sst_hsw_stream *stream)
1353 {
1354         u32 rpos;
1355
1356         sst_dsp_read(hsw->dsp, &rpos,
1357                 stream->reply.read_position_register_address, sizeof(rpos));
1358
1359         return rpos;
1360 }
1361
1362 /* Stream presentation (monotonic) positions */
1363 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1364         struct sst_hsw_stream *stream)
1365 {
1366         u64 ppos;
1367
1368         sst_dsp_read(hsw->dsp, &ppos,
1369                 stream->reply.presentation_position_register_address,
1370                 sizeof(ppos));
1371
1372         return ppos;
1373 }
1374
1375 /* physical BE config */
1376 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1377         enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1378         enum sst_hsw_device_mode mode, u32 clock_divider)
1379 {
1380         struct sst_hsw_ipc_device_config_req config;
1381         u32 header;
1382         int ret;
1383
1384         trace_ipc_request("set device config", dev);
1385
1386         hsw->dx_dev = config.ssp_interface = dev;
1387         hsw->dx_mclk = config.clock_frequency = mclk;
1388         hsw->dx_mode = config.mode = mode;
1389         hsw->dx_clock_divider = config.clock_divider = clock_divider;
1390         if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1391                 config.channels = 4;
1392         else
1393                 config.channels = 2;
1394
1395         trace_hsw_device_config_req(&config);
1396
1397         header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1398
1399         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1400                 sizeof(config), NULL, 0);
1401         if (ret < 0)
1402                 dev_err(hsw->dev, "error: set device formats failed\n");
1403
1404         return ret;
1405 }
1406 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1407
1408 /* DX Config */
1409 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1410         enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1411 {
1412         u32 header, state_;
1413         int ret, item;
1414
1415         header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1416         state_ = state;
1417
1418         trace_ipc_request("PM enter Dx state", state);
1419
1420         ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1421                 sizeof(state_), dx, sizeof(*dx));
1422         if (ret < 0) {
1423                 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1424                 return ret;
1425         }
1426
1427         for (item = 0; item < dx->entries_no; item++) {
1428                 dev_dbg(hsw->dev,
1429                         "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1430                         item, dx->mem_info[item].offset,
1431                         dx->mem_info[item].size,
1432                         dx->mem_info[item].source);
1433         }
1434         dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1435                 dx->entries_no, state);
1436
1437         return ret;
1438 }
1439
1440 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1441         int mod_id, int offset)
1442 {
1443         struct sst_dsp *dsp = hsw->dsp;
1444         struct sst_module *module;
1445         struct sst_module_runtime *runtime;
1446         int err;
1447
1448         module = sst_module_get_from_id(dsp, mod_id);
1449         if (module == NULL) {
1450                 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1451                         mod_id);
1452                 return NULL;
1453         }
1454
1455         runtime = sst_module_runtime_new(module, mod_id, NULL);
1456         if (runtime == NULL) {
1457                 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1458                         mod_id);
1459                 return NULL;
1460         }
1461
1462         err = sst_module_runtime_alloc_blocks(runtime, offset);
1463         if (err < 0) {
1464                 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1465                         mod_id);
1466                 sst_module_runtime_free(runtime);
1467                 return NULL;
1468         }
1469
1470         dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1471                 mod_id);
1472         return runtime;
1473 }
1474
1475 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1476 {
1477         sst_module_runtime_free_blocks(runtime);
1478         sst_module_runtime_free(runtime);
1479 }
1480
1481 #ifdef CONFIG_PM
1482 static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1483 {
1484         struct sst_dsp *sst = hsw->dsp;
1485         u32 item, offset, size;
1486         int ret = 0;
1487
1488         trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1489
1490         if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1491                 dev_err(hsw->dev,
1492                         "error: number of FW context regions greater than %d\n",
1493                         SST_HSW_MAX_DX_REGIONS);
1494                 memset(&hsw->dx, 0, sizeof(hsw->dx));
1495                 return -EINVAL;
1496         }
1497
1498         ret = sst_dsp_dma_get_channel(sst, 0);
1499         if (ret < 0) {
1500                 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1501                 return ret;
1502         }
1503
1504         /* set on-demond mode on engine 0 channel 3 */
1505         sst_dsp_shim_update_bits(sst, SST_HMDC,
1506                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1507                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1508
1509         for (item = 0; item < hsw->dx.entries_no; item++) {
1510                 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1511                         && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1512                         && hsw->dx.mem_info[item].offset <
1513                         DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1514
1515                         offset = hsw->dx.mem_info[item].offset
1516                                         - DSP_DRAM_ADDR_OFFSET;
1517                         size = (hsw->dx.mem_info[item].size + 3) & (~3);
1518
1519                         ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1520                                 sst->addr.lpe_base + offset, size);
1521                         if (ret < 0) {
1522                                 dev_err(hsw->dev,
1523                                         "error: FW context dump failed\n");
1524                                 memset(&hsw->dx, 0, sizeof(hsw->dx));
1525                                 goto out;
1526                         }
1527                 }
1528         }
1529
1530 out:
1531         sst_dsp_dma_put_channel(sst);
1532         return ret;
1533 }
1534
1535 static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1536 {
1537         struct sst_dsp *sst = hsw->dsp;
1538         u32 item, offset, size;
1539         int ret;
1540
1541         for (item = 0; item < hsw->dx.entries_no; item++) {
1542                 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1543                         && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1544                         && hsw->dx.mem_info[item].offset <
1545                         DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1546
1547                         offset = hsw->dx.mem_info[item].offset
1548                                         - DSP_DRAM_ADDR_OFFSET;
1549                         size = (hsw->dx.mem_info[item].size + 3) & (~3);
1550
1551                         ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1552                                 hsw->dx_context_paddr + offset, size);
1553                         if (ret < 0) {
1554                                 dev_err(hsw->dev,
1555                                         "error: FW context restore failed\n");
1556                                 return ret;
1557                         }
1558                 }
1559         }
1560
1561         return 0;
1562 }
1563
1564 int sst_hsw_dsp_load(struct sst_hsw *hsw)
1565 {
1566         struct sst_dsp *dsp = hsw->dsp;
1567         struct sst_fw *sst_fw, *t;
1568         int ret;
1569
1570         dev_dbg(hsw->dev, "loading audio DSP....");
1571
1572         ret = sst_dsp_wake(dsp);
1573         if (ret < 0) {
1574                 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1575                 return -ENODEV;
1576         }
1577
1578         ret = sst_dsp_dma_get_channel(dsp, 0);
1579         if (ret < 0) {
1580                 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1581                 return ret;
1582         }
1583
1584         list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1585                 ret = sst_fw_reload(sst_fw);
1586                 if (ret < 0) {
1587                         dev_err(hsw->dev, "error: SST FW reload failed\n");
1588                         sst_dsp_dma_put_channel(dsp);
1589                         return -ENOMEM;
1590                 }
1591         }
1592         ret = sst_block_alloc_scratch(hsw->dsp);
1593         if (ret < 0)
1594                 return -EINVAL;
1595
1596         sst_dsp_dma_put_channel(dsp);
1597         return 0;
1598 }
1599
1600 static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1601 {
1602         struct sst_dsp *dsp = hsw->dsp;
1603         int ret;
1604
1605         dev_dbg(hsw->dev, "restoring audio DSP....");
1606
1607         ret = sst_dsp_dma_get_channel(dsp, 0);
1608         if (ret < 0) {
1609                 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1610                 return ret;
1611         }
1612
1613         ret = sst_hsw_dx_state_restore(hsw);
1614         if (ret < 0) {
1615                 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1616                 sst_dsp_dma_put_channel(dsp);
1617                 return -ENOMEM;
1618         }
1619         sst_dsp_dma_put_channel(dsp);
1620
1621         /* wait for DSP boot completion */
1622         sst_dsp_boot(dsp);
1623
1624         return ret;
1625 }
1626
1627 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1628 {
1629         int ret;
1630
1631         dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1632
1633         ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1634         if (ret < 0)
1635                 return ret;
1636
1637         sst_dsp_stall(hsw->dsp);
1638
1639         ret = sst_hsw_dx_state_dump(hsw);
1640         if (ret < 0)
1641                 return ret;
1642
1643         sst_ipc_drop_all(&hsw->ipc);
1644
1645         return 0;
1646 }
1647
1648 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1649 {
1650         struct sst_fw *sst_fw, *t;
1651         struct sst_dsp *dsp = hsw->dsp;
1652
1653         list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1654                 sst_fw_unload(sst_fw);
1655         }
1656         sst_block_free_scratch(dsp);
1657
1658         hsw->boot_complete = false;
1659
1660         sst_dsp_sleep(dsp);
1661
1662         return 0;
1663 }
1664
1665 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1666 {
1667         struct device *dev = hsw->dev;
1668         int ret;
1669
1670         dev_dbg(dev, "audio dsp runtime resume\n");
1671
1672         if (hsw->boot_complete)
1673                 return 1; /* tell caller no action is required */
1674
1675         ret = sst_hsw_dsp_restore(hsw);
1676         if (ret < 0)
1677                 dev_err(dev, "error: audio DSP boot failure\n");
1678
1679         sst_hsw_init_module_state(hsw);
1680
1681         ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1682                 msecs_to_jiffies(IPC_BOOT_MSECS));
1683         if (ret == 0) {
1684                 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1685                         sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1686                         sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1687                 return -EIO;
1688         }
1689
1690         /* Set ADSP SSP port settings - sadly the FW does not store SSP port
1691            settings as part of the PM context. */
1692         ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1693                                         hsw->dx_mode, hsw->dx_clock_divider);
1694         if (ret < 0)
1695                 dev_err(dev, "error: SSP re-initialization failed\n");
1696
1697         return ret;
1698 }
1699 #endif
1700
1701 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1702 {
1703         return hsw->dsp;
1704 }
1705
1706 void sst_hsw_init_module_state(struct sst_hsw *hsw)
1707 {
1708         struct sst_module *module;
1709         enum sst_hsw_module_id id;
1710
1711         /* the base fw contains several modules */
1712         for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1713                 module = sst_module_get_from_id(hsw->dsp, id);
1714                 if (module) {
1715                         /* module waves is active only after being enabled */
1716                         if (id == SST_HSW_MODULE_WAVES)
1717                                 module->state = SST_MODULE_STATE_INITIALIZED;
1718                         else
1719                                 module->state = SST_MODULE_STATE_ACTIVE;
1720                 }
1721         }
1722 }
1723
1724 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1725 {
1726         struct sst_module *module;
1727
1728         module = sst_module_get_from_id(hsw->dsp, module_id);
1729         if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1730                 return false;
1731         else
1732                 return true;
1733 }
1734
1735 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1736 {
1737         struct sst_module *module;
1738
1739         module = sst_module_get_from_id(hsw->dsp, module_id);
1740         if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1741                 return true;
1742         else
1743                 return false;
1744 }
1745
1746 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1747 {
1748         hsw->enabled_modules_rtd3 |= (1 << module_id);
1749 }
1750
1751 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1752 {
1753         hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1754 }
1755
1756 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1757 {
1758         return hsw->enabled_modules_rtd3 & (1 << module_id);
1759 }
1760
1761 void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1762 {
1763         hsw->param_idx_w = 0;
1764         hsw->param_idx_r = 0;
1765         memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1766 }
1767
1768 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1769 {
1770         /* save line to the first available position of param buffer */
1771         if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1772                 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1773                 return -EPERM;
1774         }
1775         memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1776         hsw->param_idx_w++;
1777         return 0;
1778 }
1779
1780 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1781 {
1782         u8 id = 0;
1783
1784         /* read the first matching line from param buffer */
1785         while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1786                 id = hsw->param_buf[hsw->param_idx_r][0];
1787                 hsw->param_idx_r++;
1788                 if (buf[0] == id) {
1789                         memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1790                                 WAVES_PARAM_COUNT);
1791                         break;
1792                 }
1793         }
1794         if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1795                 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1796                 hsw->param_idx_r = 0;
1797                 return 0;
1798         }
1799         return 0;
1800 }
1801
1802 int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1803 {
1804         int ret, idx;
1805
1806         if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1807                 dev_dbg(hsw->dev, "module waves is not active\n");
1808                 return 0;
1809         }
1810
1811         /* put all param lines to DSP through ipc */
1812         for (idx = 0; idx < hsw->param_idx_w; idx++) {
1813                 ret = sst_hsw_module_set_param(hsw,
1814                         SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1815                         WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1816                 if (ret < 0)
1817                         return ret;
1818         }
1819         return 0;
1820 }
1821
1822 int sst_hsw_module_load(struct sst_hsw *hsw,
1823         u32 module_id, u32 instance_id, char *name)
1824 {
1825         int ret = 0;
1826         const struct firmware *fw = NULL;
1827         struct sst_fw *hsw_sst_fw;
1828         struct sst_module *module;
1829         struct device *dev = hsw->dev;
1830         struct sst_dsp *dsp = hsw->dsp;
1831
1832         dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1833
1834         module = sst_module_get_from_id(dsp, module_id);
1835         if (module == NULL) {
1836                 /* loading for the first time */
1837                 if (module_id == SST_HSW_MODULE_BASE_FW) {
1838                         /* for base module: use fw requested in acpi probe */
1839                         fw = dsp->pdata->fw;
1840                         if (!fw) {
1841                                 dev_err(dev, "request Base fw failed\n");
1842                                 return -ENODEV;
1843                         }
1844                 } else {
1845                         /* try and load any other optional modules if they are
1846                          * available. Use dev_info instead of dev_err in case
1847                          * request firmware failed */
1848                         ret = reject_firmware(&fw, name, dev);
1849                         if (ret) {
1850                                 dev_info(dev, "fw image %s not available(%d)\n",
1851                                                 name, ret);
1852                                 return ret;
1853                         }
1854                 }
1855                 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1856                 if (hsw_sst_fw  == NULL) {
1857                         dev_err(dev, "error: failed to load firmware\n");
1858                         ret = -ENOMEM;
1859                         goto out;
1860                 }
1861                 module = sst_module_get_from_id(dsp, module_id);
1862                 if (module == NULL) {
1863                         dev_err(dev, "error: no module %d in firmware %s\n",
1864                                         module_id, name);
1865                 }
1866         } else
1867                 dev_info(dev, "module %d (%s) already loaded\n",
1868                                 module_id, name);
1869 out:
1870         /* release fw, but base fw should be released by acpi driver */
1871         if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1872                 release_firmware(fw);
1873
1874         return ret;
1875 }
1876
1877 int sst_hsw_module_enable(struct sst_hsw *hsw,
1878         u32 module_id, u32 instance_id)
1879 {
1880         int ret;
1881         u32 header = 0;
1882         struct sst_hsw_ipc_module_config config;
1883         struct sst_module *module;
1884         struct sst_module_runtime *runtime;
1885         struct device *dev = hsw->dev;
1886         struct sst_dsp *dsp = hsw->dsp;
1887
1888         if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1889                 dev_dbg(dev, "module %d not loaded\n", module_id);
1890                 return 0;
1891         }
1892
1893         if (sst_hsw_is_module_active(hsw, module_id)) {
1894                 dev_info(dev, "module %d already enabled\n", module_id);
1895                 return 0;
1896         }
1897
1898         module = sst_module_get_from_id(dsp, module_id);
1899         if (module == NULL) {
1900                 dev_err(dev, "module %d not valid\n", module_id);
1901                 return -ENXIO;
1902         }
1903
1904         runtime = sst_module_runtime_get_from_id(module, module_id);
1905         if (runtime == NULL) {
1906                 dev_err(dev, "runtime %d not valid", module_id);
1907                 return -ENXIO;
1908         }
1909
1910         header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1911                         IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1912                         IPC_MODULE_ID(module_id);
1913         dev_dbg(dev, "module enable header: %x\n", header);
1914
1915         config.map.module_entries_count = 1;
1916         config.map.module_entries[0].module_id = module->id;
1917         config.map.module_entries[0].entry_point = module->entry;
1918
1919         config.persistent_mem.offset =
1920                 sst_dsp_get_offset(dsp,
1921                         runtime->persistent_offset, SST_MEM_DRAM);
1922         config.persistent_mem.size = module->persistent_size;
1923
1924         config.scratch_mem.offset =
1925                 sst_dsp_get_offset(dsp,
1926                         dsp->scratch_offset, SST_MEM_DRAM);
1927         config.scratch_mem.size = module->scratch_size;
1928         dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1929                 config.map.module_entries[0].module_id,
1930                 config.persistent_mem.size,
1931                 config.persistent_mem.offset,
1932                 config.scratch_mem.size, config.scratch_mem.offset,
1933                 config.map.module_entries[0].entry_point);
1934
1935         ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
1936                         &config, sizeof(config), NULL, 0);
1937         if (ret < 0)
1938                 dev_err(dev, "ipc: module enable failed - %d\n", ret);
1939         else
1940                 module->state = SST_MODULE_STATE_ACTIVE;
1941
1942         return ret;
1943 }
1944
1945 int sst_hsw_module_disable(struct sst_hsw *hsw,
1946         u32 module_id, u32 instance_id)
1947 {
1948         int ret;
1949         u32 header;
1950         struct sst_module *module;
1951         struct device *dev = hsw->dev;
1952         struct sst_dsp *dsp = hsw->dsp;
1953
1954         if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1955                 dev_dbg(dev, "module %d not loaded\n", module_id);
1956                 return 0;
1957         }
1958
1959         if (!sst_hsw_is_module_active(hsw, module_id)) {
1960                 dev_info(dev, "module %d already disabled\n", module_id);
1961                 return 0;
1962         }
1963
1964         module = sst_module_get_from_id(dsp, module_id);
1965         if (module == NULL) {
1966                 dev_err(dev, "module %d not valid\n", module_id);
1967                 return -ENXIO;
1968         }
1969
1970         header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1971                         IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1972                         IPC_MODULE_ID(module_id);
1973
1974         ret = sst_ipc_tx_message_wait(&hsw->ipc, header,  NULL, 0, NULL, 0);
1975         if (ret < 0)
1976                 dev_err(dev, "module disable failed - %d\n", ret);
1977         else
1978                 module->state = SST_MODULE_STATE_INITIALIZED;
1979
1980         return ret;
1981 }
1982
1983 int sst_hsw_module_set_param(struct sst_hsw *hsw,
1984         u32 module_id, u32 instance_id, u32 parameter_id,
1985         u32 param_size, char *param)
1986 {
1987         int ret;
1988         u32 header = 0;
1989         u32 payload_size = 0, transfer_parameter_size = 0;
1990         struct sst_hsw_transfer_parameter *parameter;
1991         struct device *dev = hsw->dev;
1992
1993         header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1994                         IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
1995                         IPC_MODULE_ID(module_id);
1996         dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
1997
1998         payload_size = param_size +
1999                 sizeof(struct sst_hsw_transfer_parameter) -
2000                 sizeof(struct sst_hsw_transfer_list);
2001         dev_dbg(dev, "parameter size : %d\n", param_size);
2002         dev_dbg(dev, "payload size   : %d\n", payload_size);
2003
2004         if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2005                 /* short parameter, mailbox can contain data */
2006                 dev_dbg(dev, "transfer parameter size : %d\n",
2007                         transfer_parameter_size);
2008
2009                 transfer_parameter_size = ALIGN(payload_size, 4);
2010                 dev_dbg(dev, "transfer parameter aligned size : %d\n",
2011                         transfer_parameter_size);
2012
2013                 parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2014                 if (parameter == NULL)
2015                         return -ENOMEM;
2016
2017                 memcpy(parameter->data, param, param_size);
2018         } else {
2019                 dev_warn(dev, "transfer parameter size too large!");
2020                 return 0;
2021         }
2022
2023         parameter->parameter_id = parameter_id;
2024         parameter->data_size = param_size;
2025
2026         ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
2027                 parameter, transfer_parameter_size , NULL, 0);
2028         if (ret < 0)
2029                 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2030
2031         kfree(parameter);
2032
2033         return ret;
2034 }
2035
2036 static struct sst_dsp_device hsw_dev = {
2037         .thread = hsw_irq_thread,
2038         .ops = &haswell_ops,
2039 };
2040
2041 static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2042 {
2043         /* send the message */
2044         sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2045         sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2046 }
2047
2048 static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2049 {
2050         struct sst_dsp *sst = ipc->dsp;
2051         u32 isr, ipcd, imrx, ipcx;
2052
2053         ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2054         isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2055         ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2056         imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2057
2058         dev_err(ipc->dev,
2059                 "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2060                 text, ipcx, isr, ipcd, imrx);
2061 }
2062
2063 static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2064         size_t tx_size)
2065 {
2066         memcpy(msg->tx_data, tx_data, tx_size);
2067 }
2068
2069 static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2070 {
2071         /* clear reply bits & status bits */
2072         header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2073         *mask = (u64)-1;
2074
2075         return header;
2076 }
2077
2078 static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2079 {
2080         u64 ipcx;
2081
2082         ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2083         return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2084 }
2085
2086 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2087 {
2088         struct sst_hsw_ipc_fw_version version;
2089         struct sst_hsw *hsw;
2090         struct sst_generic_ipc *ipc;
2091         int ret;
2092
2093         dev_dbg(dev, "initialising Audio DSP IPC\n");
2094
2095         hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2096         if (hsw == NULL)
2097                 return -ENOMEM;
2098
2099         hsw->dev = dev;
2100
2101         ipc = &hsw->ipc;
2102         ipc->dev = dev;
2103         ipc->ops.tx_msg = hsw_tx_msg;
2104         ipc->ops.shim_dbg = hsw_shim_dbg;
2105         ipc->ops.tx_data_copy = hsw_tx_data_copy;
2106         ipc->ops.reply_msg_match = hsw_reply_msg_match;
2107         ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
2108
2109         ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2110         ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2111
2112         ret = sst_ipc_init(ipc);
2113         if (ret != 0)
2114                 goto ipc_init_err;
2115
2116         INIT_LIST_HEAD(&hsw->stream_list);
2117         init_waitqueue_head(&hsw->boot_wait);
2118         hsw_dev.thread_context = hsw;
2119
2120         /* init SST shim */
2121         hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2122         if (hsw->dsp == NULL) {
2123                 ret = -ENODEV;
2124                 goto dsp_new_err;
2125         }
2126
2127         ipc->dsp = hsw->dsp;
2128
2129         /* allocate DMA buffer for context storage */
2130         hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2131                 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2132         if (hsw->dx_context == NULL) {
2133                 ret = -ENOMEM;
2134                 goto dma_err;
2135         }
2136
2137         /* keep the DSP in reset state for base FW loading */
2138         sst_dsp_reset(hsw->dsp);
2139
2140         /* load base module and other modules in base firmware image */
2141         ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2142         if (ret < 0)
2143                 goto fw_err;
2144
2145         /* try to load module waves */
2146         sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "/*(DEBLOBBED)*/");
2147
2148         /* allocate scratch mem regions */
2149         ret = sst_block_alloc_scratch(hsw->dsp);
2150         if (ret < 0)
2151                 goto boot_err;
2152
2153         /* init param buffer */
2154         sst_hsw_reset_param_buf(hsw);
2155
2156         /* wait for DSP boot completion */
2157         sst_dsp_boot(hsw->dsp);
2158         ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2159                 msecs_to_jiffies(IPC_BOOT_MSECS));
2160         if (ret == 0) {
2161                 ret = -EIO;
2162                 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2163                         sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2164                         sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2165                 goto boot_err;
2166         }
2167
2168         /* init module state after boot */
2169         sst_hsw_init_module_state(hsw);
2170
2171         /* get the FW version */
2172         sst_hsw_fw_get_version(hsw, &version);
2173
2174         /* get the globalmixer */
2175         ret = sst_hsw_mixer_get_info(hsw);
2176         if (ret < 0) {
2177                 dev_err(hsw->dev, "error: failed to get stream info\n");
2178                 goto boot_err;
2179         }
2180
2181         pdata->dsp = hsw;
2182         return 0;
2183
2184 boot_err:
2185         sst_dsp_reset(hsw->dsp);
2186         sst_fw_free_all(hsw->dsp);
2187 fw_err:
2188         dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2189                         hsw->dx_context, hsw->dx_context_paddr);
2190 dma_err:
2191         sst_dsp_free(hsw->dsp);
2192 dsp_new_err:
2193         sst_ipc_fini(ipc);
2194 ipc_init_err:
2195         return ret;
2196 }
2197 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2198
2199 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2200 {
2201         struct sst_hsw *hsw = pdata->dsp;
2202
2203         sst_dsp_reset(hsw->dsp);
2204         sst_fw_free_all(hsw->dsp);
2205         dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2206                         hsw->dx_context, hsw->dx_context_paddr);
2207         sst_dsp_free(hsw->dsp);
2208         sst_ipc_fini(&hsw->ipc);
2209 }
2210 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);