1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
8 #include <linux/dmaengine.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_platform.h>
12 #include <linux/pm_runtime.h>
13 #include <sound/dmaengine_pcm.h>
14 #include <sound/pcm_params.h>
19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
20 SNDRV_PCM_FMTBIT_S16_LE | \
21 SNDRV_PCM_FMTBIT_S20_3LE | \
22 SNDRV_PCM_FMTBIT_S24_LE)
25 * fsl_esai: ESAI private data
27 * @dma_params_rx: DMA parameters for receive channel
28 * @dma_params_tx: DMA parameters for transmit channel
29 * @pdev: platform device pointer
30 * @regmap: regmap handler
31 * @coreclk: clock source to access register
32 * @extalclk: esai clock source to derive HCK, SCK and FS
33 * @fsysclk: system clock source to derive HCK, SCK and FS
34 * @spbaclk: SPBA clock (optional, depending on SoC design)
35 * @fifo_depth: depth of tx/rx FIFO
36 * @slot_width: width of each DAI slot
37 * @slots: number of slots
38 * @hck_rate: clock rate of desired HCKx clock
39 * @sck_rate: clock rate of desired SCKx clock
40 * @hck_dir: the direction of HCKx pads
41 * @sck_div: if using PSR/PM dividers for SCKx clock
42 * @slave_mode: if fully using DAI slave mode
43 * @synchronous: if using tx/rx synchronous mode
47 struct snd_dmaengine_dai_dma_data dma_params_rx;
48 struct snd_dmaengine_dai_dma_data dma_params_tx;
49 struct platform_device *pdev;
50 struct regmap *regmap;
69 static irqreturn_t esai_isr(int irq, void *devid)
71 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
72 struct platform_device *pdev = esai_priv->pdev;
75 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
77 if (esr & ESAI_ESR_TINIT_MASK)
78 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
80 if (esr & ESAI_ESR_RFF_MASK)
81 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
83 if (esr & ESAI_ESR_TFE_MASK)
84 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
86 if (esr & ESAI_ESR_TLS_MASK)
87 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
89 if (esr & ESAI_ESR_TDE_MASK)
90 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
92 if (esr & ESAI_ESR_TED_MASK)
93 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
95 if (esr & ESAI_ESR_TD_MASK)
96 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
98 if (esr & ESAI_ESR_RLS_MASK)
99 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
101 if (esr & ESAI_ESR_RDE_MASK)
102 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
104 if (esr & ESAI_ESR_RED_MASK)
105 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
107 if (esr & ESAI_ESR_RD_MASK)
108 dev_dbg(&pdev->dev, "isr: Receiving data\n");
114 * This function is used to calculate the divisors of psr, pm, fp and it is
115 * supposed to be called in set_dai_sysclk() and set_bclk().
117 * @ratio: desired overall ratio for the paticipating dividers
118 * @usefp: for HCK setting, there is no need to set fp divider
119 * @fp: bypass other dividers by setting fp directly if fp != 0
120 * @tx: current setting is for playback or capture
122 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
125 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
126 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
128 maxfp = usefp ? 16 : 1;
133 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
134 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
135 2 * 8 * 256 * maxfp);
137 } else if (ratio % 2) {
138 dev_err(dai->dev, "the raio must be even if using upper divider\n");
144 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
146 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
153 /* Set the max fluctuation -- 0.1% of the max devisor */
154 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
156 /* Find the best value for PM */
157 for (i = 1; i <= 256; i++) {
158 for (j = 1; j <= maxfp; j++) {
159 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
160 prod = (psr ? 1 : 8) * i * j;
164 else if (prod / ratio == 1)
166 else if (ratio / prod == 1)
171 /* Calculate the fraction */
172 sub = sub * 1000 / ratio;
186 dev_err(dai->dev, "failed to calculate proper divisors\n");
191 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
192 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
193 psr | ESAI_xCCR_xPM(pm));
196 /* Bypass fp if not being required */
200 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
201 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
207 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
210 * clk_id: The clock source of HCKT/HCKR
211 * (Input from outside; output from inside, FSYS or EXTAL)
212 * freq: The required clock rate of HCKT/HCKR
213 * dir: The clock direction of HCKT/HCKR
215 * Note: If the direction is input, we do not care about clk_id.
217 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
218 unsigned int freq, int dir)
220 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
221 struct clk *clksrc = esai_priv->extalclk;
222 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
223 bool in = dir == SND_SOC_CLOCK_IN;
225 unsigned long clk_rate;
229 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
230 in ? "in" : "out", tx ? 'T' : 'R');
234 /* Bypass divider settings if the requirement doesn't change */
235 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
238 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
239 esai_priv->sck_div[tx] = true;
241 /* Set the direction of HCKT/HCKR pins */
242 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
243 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
251 clksrc = esai_priv->fsysclk;
253 case ESAI_HCKT_EXTAL:
256 case ESAI_HCKR_EXTAL:
257 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
263 if (IS_ERR(clksrc)) {
264 dev_err(dai->dev, "no assigned %s clock\n",
265 clk_id % 2 ? "extal" : "fsys");
266 return PTR_ERR(clksrc);
268 clk_rate = clk_get_rate(clksrc);
270 ratio = clk_rate / freq;
271 if (ratio * freq > clk_rate)
272 ret = ratio * freq - clk_rate;
273 else if (ratio * freq < clk_rate)
274 ret = clk_rate - ratio * freq;
278 /* Block if clock source can not be divided into the required rate */
279 if (ret != 0 && clk_rate / ret < 1000) {
280 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
285 /* Only EXTAL source can be output directly without using PSR and PM */
286 if (ratio == 1 && clksrc == esai_priv->extalclk) {
287 /* Bypass all the dividers if not being needed */
288 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
290 } else if (ratio < 2) {
291 /* The ratio should be no less than 2 if using other sources */
292 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
297 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
301 esai_priv->sck_div[tx] = false;
304 esai_priv->hck_dir[tx] = dir;
305 esai_priv->hck_rate[tx] = freq;
307 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
308 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
309 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
315 * This function configures the related dividers according to the bclk rate
317 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
319 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
320 u32 hck_rate = esai_priv->hck_rate[tx];
321 u32 sub, ratio = hck_rate / freq;
324 /* Don't apply for fully slave mode or unchanged bclk */
325 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
328 if (ratio * freq > hck_rate)
329 sub = ratio * freq - hck_rate;
330 else if (ratio * freq < hck_rate)
331 sub = hck_rate - ratio * freq;
335 /* Block if clock source can not be divided into the required rate */
336 if (sub != 0 && hck_rate / sub < 1000) {
337 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
342 /* The ratio should be contented by FP alone if bypassing PM and PSR */
343 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
344 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
348 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
349 esai_priv->sck_div[tx] ? 0 : ratio);
353 /* Save current bclk rate */
354 esai_priv->sck_rate[tx] = freq;
359 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
360 u32 rx_mask, int slots, int slot_width)
362 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
364 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
365 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
367 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
368 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
370 esai_priv->slot_width = slot_width;
371 esai_priv->slots = slots;
372 esai_priv->tx_mask = tx_mask;
373 esai_priv->rx_mask = rx_mask;
378 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
380 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
381 u32 xcr = 0, xccr = 0, mask;
384 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
385 case SND_SOC_DAIFMT_I2S:
386 /* Data on rising edge of bclk, frame low, 1clk before data */
387 xcr |= ESAI_xCR_xFSR;
388 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
390 case SND_SOC_DAIFMT_LEFT_J:
391 /* Data on rising edge of bclk, frame high */
392 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
394 case SND_SOC_DAIFMT_RIGHT_J:
395 /* Data on rising edge of bclk, frame high, right aligned */
396 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
399 case SND_SOC_DAIFMT_DSP_A:
400 /* Data on rising edge of bclk, frame high, 1clk before data */
401 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
402 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
404 case SND_SOC_DAIFMT_DSP_B:
405 /* Data on rising edge of bclk, frame high */
406 xcr |= ESAI_xCR_xFSL;
407 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
413 /* DAI clock inversion */
414 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
415 case SND_SOC_DAIFMT_NB_NF:
416 /* Nothing to do for both normal cases */
418 case SND_SOC_DAIFMT_IB_NF:
419 /* Invert bit clock */
420 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
422 case SND_SOC_DAIFMT_NB_IF:
423 /* Invert frame clock */
424 xccr ^= ESAI_xCCR_xFSP;
426 case SND_SOC_DAIFMT_IB_IF:
427 /* Invert both clocks */
428 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
434 esai_priv->slave_mode = false;
436 /* DAI clock master masks */
437 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
438 case SND_SOC_DAIFMT_CBM_CFM:
439 esai_priv->slave_mode = true;
441 case SND_SOC_DAIFMT_CBS_CFM:
442 xccr |= ESAI_xCCR_xCKD;
444 case SND_SOC_DAIFMT_CBM_CFS:
445 xccr |= ESAI_xCCR_xFSD;
447 case SND_SOC_DAIFMT_CBS_CFS:
448 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
454 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
455 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
456 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
458 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
459 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
460 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
461 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
466 static int fsl_esai_startup(struct snd_pcm_substream *substream,
467 struct snd_soc_dai *dai)
469 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
472 /* Set synchronous mode */
473 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
474 ESAI_SAICR_SYNC, esai_priv->synchronous ?
475 ESAI_SAICR_SYNC : 0);
477 /* Set a default slot number -- 2 */
478 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
479 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
480 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
481 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
488 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
489 struct snd_pcm_hw_params *params,
490 struct snd_soc_dai *dai)
492 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
493 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
494 u32 width = params_width(params);
495 u32 channels = params_channels(params);
496 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
497 u32 slot_width = width;
501 /* Override slot_width if being specifically set */
502 if (esai_priv->slot_width)
503 slot_width = esai_priv->slot_width;
505 bclk = params_rate(params) * slot_width * esai_priv->slots;
507 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
511 mask = ESAI_xCR_xSWS_MASK;
512 val = ESAI_xCR_xSWS(slot_width, width);
514 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
515 /* Recording in synchronous mode needs to set TCR also */
516 if (!tx && esai_priv->synchronous)
517 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
519 /* Use Normal mode to support monaural audio */
520 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
521 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
522 ESAI_xCR_xMOD_NETWORK : 0);
524 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
525 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
527 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
528 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
529 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
530 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
532 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
535 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
536 ESAI_xCR_PADC, ESAI_xCR_PADC);
538 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
539 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
540 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
541 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
542 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
546 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
547 struct snd_soc_dai *dai)
549 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
550 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
551 u8 i, channels = substream->runtime->channels;
552 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
556 case SNDRV_PCM_TRIGGER_START:
557 case SNDRV_PCM_TRIGGER_RESUME:
558 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
559 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
560 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
562 /* Write initial words reqiured by ESAI as normal procedure */
563 for (i = 0; tx && i < channels; i++)
564 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
567 * When set the TE/RE in the end of enablement flow, there
568 * will be channel swap issue for multi data line case.
569 * In order to workaround this issue, we switch the bit
570 * enablement sequence to below sequence
571 * 1) clear the xSMB & xSMA: which is done in probe and
575 * 4) set xSMA: xSMA is the last one in this flow, which
576 * will trigger esai to start.
578 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
579 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
580 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
581 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
583 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
584 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
585 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
586 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
589 case SNDRV_PCM_TRIGGER_SUSPEND:
590 case SNDRV_PCM_TRIGGER_STOP:
591 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
592 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
593 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
594 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
595 ESAI_xSMA_xS_MASK, 0);
596 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
597 ESAI_xSMB_xS_MASK, 0);
599 /* Disable and reset FIFO */
600 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
601 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
602 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
612 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
613 .startup = fsl_esai_startup,
614 .trigger = fsl_esai_trigger,
615 .hw_params = fsl_esai_hw_params,
616 .set_sysclk = fsl_esai_set_dai_sysclk,
617 .set_fmt = fsl_esai_set_dai_fmt,
618 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
621 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
623 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
625 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
626 &esai_priv->dma_params_rx);
631 static struct snd_soc_dai_driver fsl_esai_dai = {
632 .probe = fsl_esai_dai_probe,
634 .stream_name = "CPU-Playback",
637 .rates = SNDRV_PCM_RATE_8000_192000,
638 .formats = FSL_ESAI_FORMATS,
641 .stream_name = "CPU-Capture",
644 .rates = SNDRV_PCM_RATE_8000_192000,
645 .formats = FSL_ESAI_FORMATS,
647 .ops = &fsl_esai_dai_ops,
650 static const struct snd_soc_component_driver fsl_esai_component = {
654 static const struct reg_default fsl_esai_reg_defaults[] = {
655 {REG_ESAI_ETDR, 0x00000000},
656 {REG_ESAI_ECR, 0x00000000},
657 {REG_ESAI_TFCR, 0x00000000},
658 {REG_ESAI_RFCR, 0x00000000},
659 {REG_ESAI_TX0, 0x00000000},
660 {REG_ESAI_TX1, 0x00000000},
661 {REG_ESAI_TX2, 0x00000000},
662 {REG_ESAI_TX3, 0x00000000},
663 {REG_ESAI_TX4, 0x00000000},
664 {REG_ESAI_TX5, 0x00000000},
665 {REG_ESAI_TSR, 0x00000000},
666 {REG_ESAI_SAICR, 0x00000000},
667 {REG_ESAI_TCR, 0x00000000},
668 {REG_ESAI_TCCR, 0x00000000},
669 {REG_ESAI_RCR, 0x00000000},
670 {REG_ESAI_RCCR, 0x00000000},
671 {REG_ESAI_TSMA, 0x0000ffff},
672 {REG_ESAI_TSMB, 0x0000ffff},
673 {REG_ESAI_RSMA, 0x0000ffff},
674 {REG_ESAI_RSMB, 0x0000ffff},
675 {REG_ESAI_PRRC, 0x00000000},
676 {REG_ESAI_PCRC, 0x00000000},
679 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
711 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
729 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
760 static const struct regmap_config fsl_esai_regmap_config = {
765 .max_register = REG_ESAI_PCRC,
766 .reg_defaults = fsl_esai_reg_defaults,
767 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
768 .readable_reg = fsl_esai_readable_reg,
769 .volatile_reg = fsl_esai_volatile_reg,
770 .writeable_reg = fsl_esai_writeable_reg,
771 .cache_type = REGCACHE_FLAT,
774 static int fsl_esai_probe(struct platform_device *pdev)
776 struct device_node *np = pdev->dev.of_node;
777 struct fsl_esai *esai_priv;
778 struct resource *res;
783 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
787 esai_priv->pdev = pdev;
788 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
790 /* Get the addresses and IRQ */
791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
792 regs = devm_ioremap_resource(&pdev->dev, res);
794 return PTR_ERR(regs);
796 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
797 "core", regs, &fsl_esai_regmap_config);
798 if (IS_ERR(esai_priv->regmap)) {
799 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
800 PTR_ERR(esai_priv->regmap));
801 return PTR_ERR(esai_priv->regmap);
804 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
805 if (IS_ERR(esai_priv->coreclk)) {
806 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
807 PTR_ERR(esai_priv->coreclk));
808 return PTR_ERR(esai_priv->coreclk);
811 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
812 if (IS_ERR(esai_priv->extalclk))
813 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
814 PTR_ERR(esai_priv->extalclk));
816 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
817 if (IS_ERR(esai_priv->fsysclk))
818 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
819 PTR_ERR(esai_priv->fsysclk));
821 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
822 if (IS_ERR(esai_priv->spbaclk))
823 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
824 PTR_ERR(esai_priv->spbaclk));
826 irq = platform_get_irq(pdev, 0);
828 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
832 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
833 esai_priv->name, esai_priv);
835 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
839 /* Set a default slot number */
840 esai_priv->slots = 2;
842 /* Set a default master/slave state */
843 esai_priv->slave_mode = true;
845 /* Determine the FIFO depth */
846 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
848 esai_priv->fifo_depth = be32_to_cpup(iprop);
850 esai_priv->fifo_depth = 64;
852 esai_priv->dma_params_tx.maxburst = 16;
853 esai_priv->dma_params_rx.maxburst = 16;
854 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
855 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
857 esai_priv->synchronous =
858 of_property_read_bool(np, "fsl,esai-synchronous");
860 /* Implement full symmetry for synchronous mode */
861 if (esai_priv->synchronous) {
862 fsl_esai_dai.symmetric_rates = 1;
863 fsl_esai_dai.symmetric_channels = 1;
864 fsl_esai_dai.symmetric_samplebits = 1;
867 dev_set_drvdata(&pdev->dev, esai_priv);
869 /* Reset ESAI unit */
870 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
872 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
877 * We need to enable ESAI so as to access some of its registers.
878 * Otherwise, we would fail to dump regmap from user space.
880 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
882 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
886 esai_priv->tx_mask = 0xFFFFFFFF;
887 esai_priv->rx_mask = 0xFFFFFFFF;
889 /* Clear the TSMA, TSMB, RSMA, RSMB */
890 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
891 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
892 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
893 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
895 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
898 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
902 pm_runtime_enable(&pdev->dev);
904 regcache_cache_only(esai_priv->regmap, true);
906 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
908 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
913 static int fsl_esai_remove(struct platform_device *pdev)
915 pm_runtime_disable(&pdev->dev);
920 static const struct of_device_id fsl_esai_dt_ids[] = {
921 { .compatible = "fsl,imx35-esai", },
922 { .compatible = "fsl,vf610-esai", },
925 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
928 static int fsl_esai_runtime_resume(struct device *dev)
930 struct fsl_esai *esai = dev_get_drvdata(dev);
934 * Some platforms might use the same bit to gate all three or two of
935 * clocks, so keep all clocks open/close at the same time for safety
937 ret = clk_prepare_enable(esai->coreclk);
940 if (!IS_ERR(esai->spbaclk)) {
941 ret = clk_prepare_enable(esai->spbaclk);
945 if (!IS_ERR(esai->extalclk)) {
946 ret = clk_prepare_enable(esai->extalclk);
950 if (!IS_ERR(esai->fsysclk)) {
951 ret = clk_prepare_enable(esai->fsysclk);
956 regcache_cache_only(esai->regmap, false);
958 /* FIFO reset for safety */
959 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
960 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
961 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
962 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
964 ret = regcache_sync(esai->regmap);
966 goto err_regcache_sync;
968 /* FIFO reset done */
969 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
970 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
975 if (!IS_ERR(esai->fsysclk))
976 clk_disable_unprepare(esai->fsysclk);
978 if (!IS_ERR(esai->extalclk))
979 clk_disable_unprepare(esai->extalclk);
981 if (!IS_ERR(esai->spbaclk))
982 clk_disable_unprepare(esai->spbaclk);
984 clk_disable_unprepare(esai->coreclk);
989 static int fsl_esai_runtime_suspend(struct device *dev)
991 struct fsl_esai *esai = dev_get_drvdata(dev);
993 regcache_cache_only(esai->regmap, true);
994 regcache_mark_dirty(esai->regmap);
996 if (!IS_ERR(esai->fsysclk))
997 clk_disable_unprepare(esai->fsysclk);
998 if (!IS_ERR(esai->extalclk))
999 clk_disable_unprepare(esai->extalclk);
1000 if (!IS_ERR(esai->spbaclk))
1001 clk_disable_unprepare(esai->spbaclk);
1002 clk_disable_unprepare(esai->coreclk);
1006 #endif /* CONFIG_PM */
1008 static const struct dev_pm_ops fsl_esai_pm_ops = {
1009 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend,
1010 fsl_esai_runtime_resume,
1012 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1013 pm_runtime_force_resume)
1016 static struct platform_driver fsl_esai_driver = {
1017 .probe = fsl_esai_probe,
1018 .remove = fsl_esai_remove,
1020 .name = "fsl-esai-dai",
1021 .pm = &fsl_esai_pm_ops,
1022 .of_match_table = fsl_esai_dt_ids,
1026 module_platform_driver(fsl_esai_driver);
1028 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1029 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_ALIAS("platform:fsl-esai-dai");