sound/soc/codecs/adav80x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ADAV80X Audio Codec driver supporting ADAV801, ADAV803
   4  *
   5  * Copyright 2011 Analog Devices Inc.
   6  * Author: Yi Li <yi.li@analog.com>
   7  * Author: Lars-Peter Clausen <lars@metafoo.de>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/regmap.h>
  13 #include <linux/slab.h>
  14
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include <sound/soc.h>
  18 #include <sound/tlv.h>
  19
  20 #include "adav80x.h"
  21
  22 #define ADAV80X_PLAYBACK_CTRL   0x04
  23 #define ADAV80X_AUX_IN_CTRL     0x05
  24 #define ADAV80X_REC_CTRL        0x06
  25 #define ADAV80X_AUX_OUT_CTRL    0x07
  26 #define ADAV80X_DPATH_CTRL1     0x62
  27 #define ADAV80X_DPATH_CTRL2     0x63
  28 #define ADAV80X_DAC_CTRL1       0x64
  29 #define ADAV80X_DAC_CTRL2       0x65
  30 #define ADAV80X_DAC_CTRL3       0x66
  31 #define ADAV80X_DAC_L_VOL       0x68
  32 #define ADAV80X_DAC_R_VOL       0x69
  33 #define ADAV80X_PGA_L_VOL       0x6c
  34 #define ADAV80X_PGA_R_VOL       0x6d
  35 #define ADAV80X_ADC_CTRL1       0x6e
  36 #define ADAV80X_ADC_CTRL2       0x6f
  37 #define ADAV80X_ADC_L_VOL       0x70
  38 #define ADAV80X_ADC_R_VOL       0x71
  39 #define ADAV80X_PLL_CTRL1       0x74
  40 #define ADAV80X_PLL_CTRL2       0x75
  41 #define ADAV80X_ICLK_CTRL1      0x76
  42 #define ADAV80X_ICLK_CTRL2      0x77
  43 #define ADAV80X_PLL_CLK_SRC     0x78
  44 #define ADAV80X_PLL_OUTE        0x7a
  45
  46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll)        0x00
  47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll)      (0x40 << (pll))
  48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll)       (0x40 << (pll))
  49
  50 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src)         ((src) << 5)
  51 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src)         ((src) << 2)
  52 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src)       (src)
  53 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src)       ((src) << 3)
  54
  55 #define ADAV80X_PLL_CTRL1_PLLDIV                0x10
  56 #define ADAV80X_PLL_CTRL1_PLLPD(pll)            (0x04 << (pll))
  57 #define ADAV80X_PLL_CTRL1_XTLPD                 0x02
  58
  59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x)         ((x) << ((pll) * 4))
  60
  61 #define ADAV80X_PLL_CTRL2_FS_48(pll)    ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
  62 #define ADAV80X_PLL_CTRL2_FS_32(pll)    ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
  63 #define ADAV80X_PLL_CTRL2_FS_44(pll)    ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
  64
  65 #define ADAV80X_PLL_CTRL2_SEL(pll)      ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
  66 #define ADAV80X_PLL_CTRL2_DOUB(pll)     ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
  67 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
  68
  69 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK        0x80
  70 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS       0x00
  71 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS        0x80
  72
  73 #define ADAV80X_DAC_CTRL1_PD                    0x80
  74
  75 #define ADAV80X_DAC_CTRL2_DIV1                  0x00
  76 #define ADAV80X_DAC_CTRL2_DIV1_5                0x10
  77 #define ADAV80X_DAC_CTRL2_DIV2                  0x20
  78 #define ADAV80X_DAC_CTRL2_DIV3                  0x30
  79 #define ADAV80X_DAC_CTRL2_DIV_MASK              0x30
  80
  81 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS        0x00
  82 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS        0x40
  83 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS         0x80
  84 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK         0xc0
  85
  86 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE           0x00
  87 #define ADAV80X_DAC_CTRL2_DEEMPH_44             0x01
  88 #define ADAV80X_DAC_CTRL2_DEEMPH_32             0x02
  89 #define ADAV80X_DAC_CTRL2_DEEMPH_48             0x03
  90 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK           0x01
  91
  92 #define ADAV80X_CAPTURE_MODE_MASTER             0x20
  93 #define ADAV80X_CAPTURE_WORD_LEN24              0x00
  94 #define ADAV80X_CAPTURE_WORD_LEN20              0x04
  95 #define ADAV80X_CAPTRUE_WORD_LEN18              0x08
  96 #define ADAV80X_CAPTURE_WORD_LEN16              0x0c
  97 #define ADAV80X_CAPTURE_WORD_LEN_MASK           0x0c
  98
  99 #define ADAV80X_CAPTURE_MODE_LEFT_J             0x00
 100 #define ADAV80X_CAPTURE_MODE_I2S                0x01
 101 #define ADAV80X_CAPTURE_MODE_RIGHT_J            0x03
 102 #define ADAV80X_CAPTURE_MODE_MASK               0x03
 103
 104 #define ADAV80X_PLAYBACK_MODE_MASTER            0x10
 105 #define ADAV80X_PLAYBACK_MODE_LEFT_J            0x00
 106 #define ADAV80X_PLAYBACK_MODE_I2S               0x01
 107 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24        0x04
 108 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20        0x05
 109 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18        0x06
 110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16        0x07
 111 #define ADAV80X_PLAYBACK_MODE_MASK              0x07
 112
 113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x)            BIT(2 - (x))
 114
 115 static const struct reg_default adav80x_reg_defaults[] = {
 116         { ADAV80X_PLAYBACK_CTRL,        0x01 },
 117         { ADAV80X_AUX_IN_CTRL,          0x01 },
 118         { ADAV80X_REC_CTRL,             0x02 },
 119         { ADAV80X_AUX_OUT_CTRL,         0x01 },
 120         { ADAV80X_DPATH_CTRL1,          0xc0 },
 121         { ADAV80X_DPATH_CTRL2,          0x11 },
 122         { ADAV80X_DAC_CTRL1,            0x00 },
 123         { ADAV80X_DAC_CTRL2,            0x00 },
 124         { ADAV80X_DAC_CTRL3,            0x00 },
 125         { ADAV80X_DAC_L_VOL,            0xff },
 126         { ADAV80X_DAC_R_VOL,            0xff },
 127         { ADAV80X_PGA_L_VOL,            0x00 },
 128         { ADAV80X_PGA_R_VOL,            0x00 },
 129         { ADAV80X_ADC_CTRL1,            0x00 },
 130         { ADAV80X_ADC_CTRL2,            0x00 },
 131         { ADAV80X_ADC_L_VOL,            0xff },
 132         { ADAV80X_ADC_R_VOL,            0xff },
 133         { ADAV80X_PLL_CTRL1,            0x00 },
 134         { ADAV80X_PLL_CTRL2,            0x00 },
 135         { ADAV80X_ICLK_CTRL1,           0x00 },
 136         { ADAV80X_ICLK_CTRL2,           0x00 },
 137         { ADAV80X_PLL_CLK_SRC,          0x00 },
 138         { ADAV80X_PLL_OUTE,             0x00 },
 139 };
 140
 141 struct adav80x {
 142         struct regmap *regmap;
 143
 144         enum adav80x_clk_src clk_src;
 145         unsigned int sysclk;
 146         enum adav80x_pll_src pll_src;
 147
 148         unsigned int dai_fmt[2];
 149         unsigned int rate;
 150         bool deemph;
 151         bool sysclk_pd[3];
 152 };
 153
 154 static const char *adav80x_mux_text[] = {
 155         "ADC",
 156         "Playback",
 157         "Aux Playback",
 158 };
 159
 160 static const unsigned int adav80x_mux_values[] = {
 161         0, 2, 3,
 162 };
 163
 164 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \
 165         SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \
 166                 ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \
 167                 adav80x_mux_values)
 168
 169 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0);
 170 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
 171 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
 172
 173 static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
 174         SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
 175 static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
 176         SOC_DAPM_ENUM("Route", adav80x_capture_enum);
 177 static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
 178         SOC_DAPM_ENUM("Route", adav80x_dac_enum);
 179
 180 #define ADAV80X_MUX(name, ctrl) \
 181         SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
 182
 183 static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
 184         SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
 185         SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1),
 186
 187         SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0),
 188         SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0),
 189
 190         SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
 191         SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
 192
 193         SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0),
 194         SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0),
 195
 196         ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
 197         ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
 198         ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
 199
 200         SND_SOC_DAPM_INPUT("VINR"),
 201         SND_SOC_DAPM_INPUT("VINL"),
 202         SND_SOC_DAPM_OUTPUT("VOUTR"),
 203         SND_SOC_DAPM_OUTPUT("VOUTL"),
 204
 205         SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
 206         SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
 207         SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
 208         SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0),
 209 };
 210
 211 static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source,
 212                          struct snd_soc_dapm_widget *sink)
 213 {
 214         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 215         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 216         const char *clk;
 217
 218         switch (adav80x->clk_src) {
 219         case ADAV80X_CLK_PLL1:
 220                 clk = "PLL1";
 221                 break;
 222         case ADAV80X_CLK_PLL2:
 223                 clk = "PLL2";
 224                 break;
 225         case ADAV80X_CLK_XTAL:
 226                 clk = "OSC";
 227                 break;
 228         default:
 229                 return 0;
 230         }
 231
 232         return strcmp(source->name, clk) == 0;
 233 }
 234
 235 static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source,
 236                          struct snd_soc_dapm_widget *sink)
 237 {
 238         struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 239         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 240
 241         return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL;
 242 }
 243
 244
 245 static const struct snd_soc_dapm_route adav80x_dapm_routes[] = {
 246         { "DAC Select", "ADC", "ADC" },
 247         { "DAC Select", "Playback", "AIFIN" },
 248         { "DAC Select", "Aux Playback", "AIFAUXIN" },
 249         { "DAC", NULL,  "DAC Select" },
 250
 251         { "Capture Select", "ADC", "ADC" },
 252         { "Capture Select", "Playback", "AIFIN" },
 253         { "Capture Select", "Aux Playback", "AIFAUXIN" },
 254         { "AIFOUT", NULL,  "Capture Select" },
 255
 256         { "Aux Capture Select", "ADC", "ADC" },
 257         { "Aux Capture Select", "Playback", "AIFIN" },
 258         { "Aux Capture Select", "Aux Playback", "AIFAUXIN" },
 259         { "AIFAUXOUT", NULL,  "Aux Capture Select" },
 260
 261         { "VOUTR",  NULL, "DAC" },
 262         { "VOUTL",  NULL, "DAC" },
 263
 264         { "Left PGA", NULL, "VINL" },
 265         { "Right PGA", NULL, "VINR" },
 266         { "ADC", NULL, "Left PGA" },
 267         { "ADC", NULL, "Right PGA" },
 268
 269         { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
 270         { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
 271         { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check },
 272         { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
 273         { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
 274
 275         { "ADC", NULL, "SYSCLK" },
 276         { "DAC", NULL, "SYSCLK" },
 277         { "AIFOUT", NULL, "SYSCLK" },
 278         { "AIFAUXOUT", NULL, "SYSCLK" },
 279         { "AIFIN", NULL, "SYSCLK" },
 280         { "AIFAUXIN", NULL, "SYSCLK" },
 281 };
 282
 283 static int adav80x_set_deemph(struct snd_soc_component *component)
 284 {
 285         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 286         unsigned int val;
 287
 288         if (adav80x->deemph) {
 289                 switch (adav80x->rate) {
 290                 case 32000:
 291                         val = ADAV80X_DAC_CTRL2_DEEMPH_32;
 292                         break;
 293                 case 44100:
 294                         val = ADAV80X_DAC_CTRL2_DEEMPH_44;
 295                         break;
 296                 case 48000:
 297                 case 64000:
 298                 case 88200:
 299                 case 96000:
 300                         val = ADAV80X_DAC_CTRL2_DEEMPH_48;
 301                         break;
 302                 default:
 303                         val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
 304                         break;
 305                 }
 306         } else {
 307                 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
 308         }
 309
 310         return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
 311                 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
 312 }
 313
 314 static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
 315                 struct snd_ctl_elem_value *ucontrol)
 316 {
 317         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 318         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 319         unsigned int deemph = ucontrol->value.integer.value[0];
 320
 321         if (deemph > 1)
 322                 return -EINVAL;
 323
 324         adav80x->deemph = deemph;
 325
 326         return adav80x_set_deemph(component);
 327 }
 328
 329 static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
 330                                 struct snd_ctl_elem_value *ucontrol)
 331 {
 332         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 333         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 334
 335         ucontrol->value.integer.value[0] = adav80x->deemph;
 336         return 0;
 337 };
 338
 339 static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0);
 340 static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0);
 341
 342 static const struct snd_kcontrol_new adav80x_controls[] = {
 343         SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL,
 344                 ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
 345         SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL,
 346                         ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
 347
 348         SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL,
 349                         ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv),
 350
 351         SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0),
 352         SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1),
 353
 354         SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0),
 355
 356         SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0,
 357                         adav80x_get_deemph, adav80x_put_deemph),
 358 };
 359
 360 static unsigned int adav80x_port_ctrl_regs[2][2] = {
 361         { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, },
 362         { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL },
 363 };
 364
 365 static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 366 {
 367         struct snd_soc_component *component = dai->component;
 368         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 369         unsigned int capture = 0x00;
 370         unsigned int playback = 0x00;
 371
 372         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 373         case SND_SOC_DAIFMT_CBM_CFM:
 374                 capture |= ADAV80X_CAPTURE_MODE_MASTER;
 375                 playback |= ADAV80X_PLAYBACK_MODE_MASTER;
 376         case SND_SOC_DAIFMT_CBS_CFS:
 377                 break;
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 383         case SND_SOC_DAIFMT_I2S:
 384                 capture |= ADAV80X_CAPTURE_MODE_I2S;
 385                 playback |= ADAV80X_PLAYBACK_MODE_I2S;
 386                 break;
 387         case SND_SOC_DAIFMT_LEFT_J:
 388                 capture |= ADAV80X_CAPTURE_MODE_LEFT_J;
 389                 playback |= ADAV80X_PLAYBACK_MODE_LEFT_J;
 390                 break;
 391         case SND_SOC_DAIFMT_RIGHT_J:
 392                 capture |= ADAV80X_CAPTURE_MODE_RIGHT_J;
 393                 playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
 394                 break;
 395         default:
 396                 return -EINVAL;
 397         }
 398
 399         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 400         case SND_SOC_DAIFMT_NB_NF:
 401                 break;
 402         default:
 403                 return -EINVAL;
 404         }
 405
 406         regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
 407                 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
 408                 capture);
 409         regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
 410                 playback);
 411
 412         adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 413
 414         return 0;
 415 }
 416
 417 static int adav80x_set_adc_clock(struct snd_soc_component *component,
 418                 unsigned int sample_rate)
 419 {
 420         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 421         unsigned int val;
 422
 423         if (sample_rate <= 48000)
 424                 val = ADAV80X_ADC_CTRL1_MODULATOR_128FS;
 425         else
 426                 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
 427
 428         regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
 429                 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
 430
 431         return 0;
 432 }
 433
 434 static int adav80x_set_dac_clock(struct snd_soc_component *component,
 435                 unsigned int sample_rate)
 436 {
 437         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 438         unsigned int val;
 439
 440         if (sample_rate <= 48000)
 441                 val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS;
 442         else
 443                 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
 444
 445         regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
 446                 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
 447                 val);
 448
 449         return 0;
 450 }
 451
 452 static int adav80x_set_capture_pcm_format(struct snd_soc_component *component,
 453                 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
 454 {
 455         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 456         unsigned int val;
 457
 458         switch (params_width(params)) {
 459         case 16:
 460                 val = ADAV80X_CAPTURE_WORD_LEN16;
 461                 break;
 462         case 18:
 463                 val = ADAV80X_CAPTRUE_WORD_LEN18;
 464                 break;
 465         case 20:
 466                 val = ADAV80X_CAPTURE_WORD_LEN20;
 467                 break;
 468         case 24:
 469                 val = ADAV80X_CAPTURE_WORD_LEN24;
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
 476                 ADAV80X_CAPTURE_WORD_LEN_MASK, val);
 477
 478         return 0;
 479 }
 480
 481 static int adav80x_set_playback_pcm_format(struct snd_soc_component *component,
 482                 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
 483 {
 484         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 485         unsigned int val;
 486
 487         if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J)
 488                 return 0;
 489
 490         switch (params_width(params)) {
 491         case 16:
 492                 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16;
 493                 break;
 494         case 18:
 495                 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18;
 496                 break;
 497         case 20:
 498                 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20;
 499                 break;
 500         case 24:
 501                 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
 502                 break;
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
 508                 ADAV80X_PLAYBACK_MODE_MASK, val);
 509
 510         return 0;
 511 }
 512
 513 static int adav80x_hw_params(struct snd_pcm_substream *substream,
 514                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 515 {
 516         struct snd_soc_component *component = dai->component;
 517         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 518         unsigned int rate = params_rate(params);
 519
 520         if (rate * 256 != adav80x->sysclk)
 521                 return -EINVAL;
 522
 523         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 524                 adav80x_set_playback_pcm_format(component, dai, params);
 525                 adav80x_set_dac_clock(component, rate);
 526         } else {
 527                 adav80x_set_capture_pcm_format(component, dai, params);
 528                 adav80x_set_adc_clock(component, rate);
 529         }
 530         adav80x->rate = rate;
 531         adav80x_set_deemph(component);
 532
 533         return 0;
 534 }
 535
 536 static int adav80x_set_sysclk(struct snd_soc_component *component,
 537                               int clk_id, int source,
 538                               unsigned int freq, int dir)
 539 {
 540         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 541         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 542
 543         if (dir == SND_SOC_CLOCK_IN) {
 544                 switch (clk_id) {
 545                 case ADAV80X_CLK_XIN:
 546                 case ADAV80X_CLK_XTAL:
 547                 case ADAV80X_CLK_MCLKI:
 548                 case ADAV80X_CLK_PLL1:
 549                 case ADAV80X_CLK_PLL2:
 550                         break;
 551                 default:
 552                         return -EINVAL;
 553                 }
 554
 555                 adav80x->sysclk = freq;
 556
 557                 if (adav80x->clk_src != clk_id) {
 558                         unsigned int iclk_ctrl1, iclk_ctrl2;
 559
 560                         adav80x->clk_src = clk_id;
 561                         if (clk_id == ADAV80X_CLK_XTAL)
 562                                 clk_id = ADAV80X_CLK_XIN;
 563
 564                         iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) |
 565                                         ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) |
 566                                         ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
 567                         iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
 568
 569                         regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
 570                                 iclk_ctrl1);
 571                         regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
 572                                 iclk_ctrl2);
 573
 574                         snd_soc_dapm_sync(dapm);
 575                 }
 576         } else {
 577                 unsigned int mask;
 578
 579                 switch (clk_id) {
 580                 case ADAV80X_CLK_SYSCLK1:
 581                 case ADAV80X_CLK_SYSCLK2:
 582                 case ADAV80X_CLK_SYSCLK3:
 583                         break;
 584                 default:
 585                         return -EINVAL;
 586                 }
 587
 588                 clk_id -= ADAV80X_CLK_SYSCLK1;
 589                 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
 590
 591                 if (freq == 0) {
 592                         regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
 593                                 mask, mask);
 594                         adav80x->sysclk_pd[clk_id] = true;
 595                 } else {
 596                         regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
 597                                 mask, 0);
 598                         adav80x->sysclk_pd[clk_id] = false;
 599                 }
 600
 601                 snd_soc_dapm_mutex_lock(dapm);
 602
 603                 if (adav80x->sysclk_pd[0])
 604                         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1");
 605                 else
 606                         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1");
 607
 608                 if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2])
 609                         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2");
 610                 else
 611                         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2");
 612
 613                 snd_soc_dapm_sync_unlocked(dapm);
 614
 615                 snd_soc_dapm_mutex_unlock(dapm);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int adav80x_set_pll(struct snd_soc_component *component, int pll_id,
 622                 int source, unsigned int freq_in, unsigned int freq_out)
 623 {
 624         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 625         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 626         unsigned int pll_ctrl1 = 0;
 627         unsigned int pll_ctrl2 = 0;
 628         unsigned int pll_src;
 629
 630         switch (source) {
 631         case ADAV80X_PLL_SRC_XTAL:
 632         case ADAV80X_PLL_SRC_XIN:
 633         case ADAV80X_PLL_SRC_MCLKI:
 634                 break;
 635         default:
 636                 return -EINVAL;
 637         }
 638
 639         if (!freq_out)
 640                 return 0;
 641
 642         switch (freq_in) {
 643         case 27000000:
 644                 break;
 645         case 54000000:
 646                 if (source == ADAV80X_PLL_SRC_XIN) {
 647                         pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV;
 648                         break;
 649                 }
 650                 /* fall through */
 651         default:
 652                 return -EINVAL;
 653         }
 654
 655         if (freq_out > 12288000) {
 656                 pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id);
 657                 freq_out /= 2;
 658         }
 659
 660         /* freq_out = sample_rate * 256 */
 661         switch (freq_out) {
 662         case 8192000:
 663                 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id);
 664                 break;
 665         case 11289600:
 666                 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id);
 667                 break;
 668         case 12288000:
 669                 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id);
 670                 break;
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
 676                         ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
 677         regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
 678                         ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
 679
 680         if (source != adav80x->pll_src) {
 681                 if (source == ADAV80X_PLL_SRC_MCLKI)
 682                         pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id);
 683                 else
 684                         pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
 685
 686                 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
 687                                 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
 688
 689                 adav80x->pll_src = source;
 690
 691                 snd_soc_dapm_sync(dapm);
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int adav80x_set_bias_level(struct snd_soc_component *component,
 698                 enum snd_soc_bias_level level)
 699 {
 700         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 701         unsigned int mask = ADAV80X_DAC_CTRL1_PD;
 702
 703         switch (level) {
 704         case SND_SOC_BIAS_ON:
 705                 break;
 706         case SND_SOC_BIAS_PREPARE:
 707                 break;
 708         case SND_SOC_BIAS_STANDBY:
 709                 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
 710                         0x00);
 711                 break;
 712         case SND_SOC_BIAS_OFF:
 713                 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
 714                         mask);
 715                 break;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /* Enforce the same sample rate on all audio interfaces */
 722 static int adav80x_dai_startup(struct snd_pcm_substream *substream,
 723         struct snd_soc_dai *dai)
 724 {
 725         struct snd_soc_component *component = dai->component;
 726         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 727
 728         if (!snd_soc_component_is_active(component) || !adav80x->rate)
 729                 return 0;
 730
 731         return snd_pcm_hw_constraint_single(substream->runtime,
 732                         SNDRV_PCM_HW_PARAM_RATE, adav80x->rate);
 733 }
 734
 735 static void adav80x_dai_shutdown(struct snd_pcm_substream *substream,
 736                 struct snd_soc_dai *dai)
 737 {
 738         struct snd_soc_component *component = dai->component;
 739         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 740
 741         if (!snd_soc_component_is_active(component))
 742                 adav80x->rate = 0;
 743 }
 744
 745 static const struct snd_soc_dai_ops adav80x_dai_ops = {
 746         .set_fmt = adav80x_set_dai_fmt,
 747         .hw_params = adav80x_hw_params,
 748         .startup = adav80x_dai_startup,
 749         .shutdown = adav80x_dai_shutdown,
 750 };
 751
 752 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 753         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \
 754         SNDRV_PCM_RATE_96000)
 755
 756 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
 757
 758 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
 759         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 760
 761 static struct snd_soc_dai_driver adav80x_dais[] = {
 762         {
 763                 .name = "adav80x-hifi",
 764                 .id = 0,
 765                 .playback = {
 766                         .stream_name = "HiFi Playback",
 767                         .channels_min = 2,
 768                         .channels_max = 2,
 769                         .rates = ADAV80X_PLAYBACK_RATES,
 770                         .formats = ADAV80X_FORMATS,
 771         },
 772                 .capture = {
 773                         .stream_name = "HiFi Capture",
 774                         .channels_min = 2,
 775                         .channels_max = 2,
 776                         .rates = ADAV80X_CAPTURE_RATES,
 777                         .formats = ADAV80X_FORMATS,
 778                 },
 779                 .ops = &adav80x_dai_ops,
 780         },
 781         {
 782                 .name = "adav80x-aux",
 783                 .id = 1,
 784                 .playback = {
 785                         .stream_name = "Aux Playback",
 786                         .channels_min = 2,
 787                         .channels_max = 2,
 788                         .rates = ADAV80X_PLAYBACK_RATES,
 789                         .formats = ADAV80X_FORMATS,
 790                 },
 791                 .capture = {
 792                         .stream_name = "Aux Capture",
 793                         .channels_min = 2,
 794                         .channels_max = 2,
 795                         .rates = ADAV80X_CAPTURE_RATES,
 796                         .formats = ADAV80X_FORMATS,
 797                 },
 798                 .ops = &adav80x_dai_ops,
 799         },
 800 };
 801
 802 static int adav80x_probe(struct snd_soc_component *component)
 803 {
 804         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 805         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 806
 807         /* Force PLLs on for SYSCLK output */
 808         snd_soc_dapm_force_enable_pin(dapm, "PLL1");
 809         snd_soc_dapm_force_enable_pin(dapm, "PLL2");
 810
 811         /* Power down S/PDIF receiver, since it is currently not supported */
 812         regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
 813         /* Disable DAC zero flag */
 814         regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
 815
 816         return 0;
 817 }
 818
 819 static int adav80x_resume(struct snd_soc_component *component)
 820 {
 821         struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
 822
 823         regcache_sync(adav80x->regmap);
 824
 825         return 0;
 826 }
 827
 828 static const struct snd_soc_component_driver adav80x_component_driver = {
 829         .probe                  = adav80x_probe,
 830         .resume                 = adav80x_resume,
 831         .set_bias_level         = adav80x_set_bias_level,
 832         .set_pll                = adav80x_set_pll,
 833         .set_sysclk             = adav80x_set_sysclk,
 834         .controls               = adav80x_controls,
 835         .num_controls           = ARRAY_SIZE(adav80x_controls),
 836         .dapm_widgets           = adav80x_dapm_widgets,
 837         .num_dapm_widgets       = ARRAY_SIZE(adav80x_dapm_widgets),
 838         .dapm_routes            = adav80x_dapm_routes,
 839         .num_dapm_routes        = ARRAY_SIZE(adav80x_dapm_routes),
 840         .suspend_bias_off       = 1,
 841         .idle_bias_on           = 1,
 842         .use_pmdown_time        = 1,
 843         .endianness             = 1,
 844         .non_legacy_dai_naming  = 1,
 845 };
 846
 847 int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
 848 {
 849         struct adav80x *adav80x;
 850
 851         if (IS_ERR(regmap))
 852                 return PTR_ERR(regmap);
 853
 854         adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL);
 855         if (!adav80x)
 856                 return -ENOMEM;
 857
 858         dev_set_drvdata(dev, adav80x);
 859         adav80x->regmap = regmap;
 860
 861         return devm_snd_soc_register_component(dev, &adav80x_component_driver,
 862                 adav80x_dais, ARRAY_SIZE(adav80x_dais));
 863 }
 864 EXPORT_SYMBOL_GPL(adav80x_bus_probe);
 865
 866 const struct regmap_config adav80x_regmap_config = {
 867         .val_bits = 8,
 868         .pad_bits = 1,
 869         .reg_bits = 7,
 870
 871         .max_register = ADAV80X_PLL_OUTE,
 872
 873         .cache_type = REGCACHE_RBTREE,
 874         .reg_defaults = adav80x_reg_defaults,
 875         .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
 876 };
 877 EXPORT_SYMBOL_GPL(adav80x_regmap_config);
 878
 879 MODULE_DESCRIPTION("ASoC ADAV80x driver");
 880 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 881 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>");
 882 MODULE_LICENSE("GPL");