2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include <sound/tlv.h>
20 #include <linux/gcd.h>
21 #include <linux/i2c.h>
22 #include <linux/spi/spi.h>
23 #include <linux/regmap.h>
27 #include "adau-utils.h"
29 static const char * const adau17x1_capture_mixer_boost_text[] = {
30 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
33 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
34 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
36 static const char * const adau17x1_mic_bias_mode_text[] = {
37 "Normal operation", "High performance",
40 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
41 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
43 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
45 static const struct snd_kcontrol_new adau17x1_controls[] = {
46 SOC_DOUBLE_R_TLV("Digital Capture Volume",
47 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
48 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
49 0, 0xff, 1, adau17x1_digital_tlv),
50 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
51 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
53 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
55 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
58 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
60 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
63 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
64 struct snd_kcontrol *kcontrol, int event)
66 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
67 struct adau *adau = snd_soc_codec_get_drvdata(codec);
69 if (SND_SOC_DAPM_EVENT_ON(event)) {
70 adau->pll_regs[5] = 1;
72 adau->pll_regs[5] = 0;
73 /* Bypass the PLL when disabled, otherwise registers will become
75 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
76 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
79 /* The PLL register is 6 bytes long and can only be written at once. */
80 regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
81 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
83 if (SND_SOC_DAPM_EVENT_ON(event)) {
85 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
87 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
93 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
94 struct snd_kcontrol *kcontrol, int event)
96 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
97 struct adau *adau = snd_soc_codec_get_drvdata(codec);
100 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to
101 * avoid losing SNR (workaround from ADI). This must be done after
102 * the ADC(s) have been enabled. According to the data sheet, it is
103 * normally illegal to set this bit when the sampling rate is 96 kHz,
104 * but according to ADI it is acceptable for this workaround.
106 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
107 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
108 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
109 ADAU17X1_CONVERTER0_ADOSR, 0);
114 static const char * const adau17x1_mono_stereo_text[] = {
116 "Mono Left Channel (L+R)",
117 "Mono Right Channel (L+R)",
121 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
122 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
124 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
125 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
127 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
128 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
129 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
131 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
133 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
135 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
137 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
140 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
141 &adau17x1_dac_mode_mux),
142 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
143 &adau17x1_dac_mode_mux),
145 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
146 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
147 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
148 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
149 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
152 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
153 { "Left Decimator", NULL, "SYSCLK" },
154 { "Right Decimator", NULL, "SYSCLK" },
155 { "Left DAC", NULL, "SYSCLK" },
156 { "Right DAC", NULL, "SYSCLK" },
157 { "Capture", NULL, "SYSCLK" },
158 { "Playback", NULL, "SYSCLK" },
160 { "Left DAC", NULL, "Left DAC Mode Mux" },
161 { "Right DAC", NULL, "Right DAC Mode Mux" },
163 { "Capture", NULL, "AIFCLK" },
164 { "Playback", NULL, "AIFCLK" },
167 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
168 "SYSCLK", NULL, "PLL",
172 * The MUX register for the Capture and Playback MUXs selects either DSP as
173 * source/destination or one of the TDM slots. The TDM slot is selected via
174 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
175 * directly to the DAI interface with this control.
177 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
178 struct snd_ctl_elem_value *ucontrol)
180 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
181 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
182 struct adau *adau = snd_soc_codec_get_drvdata(codec);
183 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
184 struct snd_soc_dapm_update update = { 0 };
185 unsigned int stream = e->shift_l;
186 unsigned int val, change;
189 if (ucontrol->value.enumerated.item[0] >= e->items)
192 switch (ucontrol->value.enumerated.item[0]) {
195 adau->dsp_bypass[stream] = false;
198 val = (adau->tdm_slot[stream] * 2) + 1;
199 adau->dsp_bypass[stream] = true;
203 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
204 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
206 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
208 change = snd_soc_test_bits(codec, reg, 0xff, val);
210 update.kcontrol = kcontrol;
215 snd_soc_dapm_mux_update_power(dapm, kcontrol,
216 ucontrol->value.enumerated.item[0], e, &update);
222 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol)
225 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
226 struct adau *adau = snd_soc_codec_get_drvdata(codec);
227 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
228 unsigned int stream = e->shift_l;
229 unsigned int reg, val;
232 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
233 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
235 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
237 ret = regmap_read(adau->regmap, reg, &val);
243 ucontrol->value.enumerated.item[0] = val;
248 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
249 const struct snd_kcontrol_new _name = \
250 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
251 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
252 ARRAY_SIZE(_text), _text), \
253 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
255 static const char * const adau17x1_dac_mux_text[] = {
260 static const char * const adau17x1_capture_mux_text[] = {
265 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
266 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
268 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
269 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
271 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
272 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
273 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
275 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
277 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
278 &adau17x1_capture_mux),
281 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
282 { "DAC Playback Mux", "DSP", "DSP" },
283 { "DAC Playback Mux", "AIFIN", "Playback" },
285 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
286 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
287 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
288 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
289 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
290 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
292 { "Capture Mux", "DSP", "DSP" },
293 { "Capture Mux", "Decimator", "Left Decimator" },
294 { "Capture Mux", "Decimator", "Right Decimator" },
296 { "Capture", NULL, "Capture Mux" },
298 { "DSP", NULL, "DSP Siggen" },
300 { "DSP", NULL, "Left Decimator" },
301 { "DSP", NULL, "Right Decimator" },
304 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
305 { "Left DAC Mode Mux", "Stereo", "Playback" },
306 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
307 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
308 { "Right DAC Mode Mux", "Stereo", "Playback" },
309 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
310 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
311 { "Capture", NULL, "Left Decimator" },
312 { "Capture", NULL, "Right Decimator" },
315 bool adau17x1_has_dsp(struct adau *adau)
317 switch (adau->type) {
326 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
328 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
329 int source, unsigned int freq_in, unsigned int freq_out)
331 struct snd_soc_codec *codec = dai->codec;
332 struct adau *adau = snd_soc_codec_get_drvdata(codec);
335 if (freq_in < 8000000 || freq_in > 27000000)
338 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
342 /* The PLL register is 6 bytes long and can only be written at once. */
343 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
344 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
348 adau->pll_freq = freq_out;
353 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
354 int clk_id, unsigned int freq, int dir)
356 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec);
357 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
362 case ADAU17X1_CLK_SRC_MCLK:
365 case ADAU17X1_CLK_SRC_PLL_AUTO:
369 case ADAU17X1_CLK_SRC_PLL:
376 switch (adau->clk_src) {
377 case ADAU17X1_CLK_SRC_MCLK:
380 case ADAU17X1_CLK_SRC_PLL:
381 case ADAU17X1_CLK_SRC_PLL_AUTO:
390 if (is_pll != was_pll) {
392 snd_soc_dapm_add_routes(dapm,
393 &adau17x1_dapm_pll_route, 1);
395 snd_soc_dapm_del_routes(dapm,
396 &adau17x1_dapm_pll_route, 1);
400 adau->clk_src = clk_id;
405 static int adau17x1_auto_pll(struct snd_soc_dai *dai,
406 struct snd_pcm_hw_params *params)
408 struct adau *adau = snd_soc_dai_get_drvdata(dai);
409 unsigned int pll_rate;
411 switch (params_rate(params)) {
419 pll_rate = 48000 * 1024;
428 pll_rate = 44100 * 1024;
434 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
435 clk_get_rate(adau->mclk), pll_rate);
438 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
439 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
441 struct snd_soc_codec *codec = dai->codec;
442 struct adau *adau = snd_soc_codec_get_drvdata(codec);
443 unsigned int val, div, dsp_div;
447 switch (adau->clk_src) {
448 case ADAU17X1_CLK_SRC_PLL_AUTO:
449 ret = adau17x1_auto_pll(dai, params);
453 case ADAU17X1_CLK_SRC_PLL:
454 freq = adau->pll_freq;
461 if (freq % params_rate(params) != 0)
464 switch (freq / params_rate(params)) {
469 case 6144: /* fs / 6 */
473 case 4096: /* fs / 4 */
477 case 3072: /* fs / 3 */
481 case 2048: /* fs / 2 */
485 case 1536: /* fs / 1.5 */
489 case 512: /* fs / 0.5 */
497 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
498 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
499 if (adau17x1_has_dsp(adau)) {
500 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
501 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
504 if (adau->sigmadsp) {
505 ret = adau17x1_setup_firmware(adau, params_rate(params));
510 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
513 switch (params_width(params)) {
515 val = ADAU17X1_SERIAL_PORT1_DELAY16;
518 val = ADAU17X1_SERIAL_PORT1_DELAY8;
521 val = ADAU17X1_SERIAL_PORT1_DELAY0;
527 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
528 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
531 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
534 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
535 unsigned int ctrl0, ctrl1;
538 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
539 case SND_SOC_DAIFMT_CBM_CFM:
540 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
543 case SND_SOC_DAIFMT_CBS_CFS:
545 adau->master = false;
551 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
552 case SND_SOC_DAIFMT_I2S:
554 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
556 case SND_SOC_DAIFMT_LEFT_J:
557 case SND_SOC_DAIFMT_RIGHT_J:
559 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
561 case SND_SOC_DAIFMT_DSP_A:
563 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
564 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
566 case SND_SOC_DAIFMT_DSP_B:
568 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
569 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
575 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
576 case SND_SOC_DAIFMT_NB_NF:
578 case SND_SOC_DAIFMT_IB_NF:
579 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
581 case SND_SOC_DAIFMT_NB_IF:
582 lrclk_pol = !lrclk_pol;
584 case SND_SOC_DAIFMT_IB_IF:
585 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
586 lrclk_pol = !lrclk_pol;
593 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
595 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
596 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
598 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
603 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
604 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
606 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
607 unsigned int ser_ctrl0, ser_ctrl1;
608 unsigned int conv_ctrl0, conv_ctrl1;
620 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
623 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
626 if (adau->type == ADAU1361)
629 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
635 switch (slot_width * slots) {
637 if (adau->type == ADAU1761)
640 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
643 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
646 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
649 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
652 if (adau->type == ADAU1361)
655 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
663 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
664 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
667 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
668 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
671 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
672 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
675 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
676 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
684 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
685 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
688 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
689 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
692 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
693 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
696 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
697 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
703 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
704 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
705 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
706 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
707 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
708 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
709 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
710 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
712 if (!adau17x1_has_dsp(adau))
715 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
716 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
717 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
720 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
721 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
722 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
728 static int adau17x1_startup(struct snd_pcm_substream *substream,
729 struct snd_soc_dai *dai)
731 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
734 return sigmadsp_restrict_params(adau->sigmadsp, substream);
739 const struct snd_soc_dai_ops adau17x1_dai_ops = {
740 .hw_params = adau17x1_hw_params,
741 .set_sysclk = adau17x1_set_dai_sysclk,
742 .set_fmt = adau17x1_set_dai_fmt,
743 .set_pll = adau17x1_set_dai_pll,
744 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
745 .startup = adau17x1_startup,
747 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
749 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
750 enum adau17x1_micbias_voltage micbias)
752 struct adau *adau = snd_soc_codec_get_drvdata(codec);
755 case ADAU17X1_MICBIAS_0_90_AVDD:
756 case ADAU17X1_MICBIAS_0_65_AVDD:
762 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
764 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
766 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
768 /* SigmaDSP parameter memory */
774 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
776 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
778 /* SigmaDSP parameter memory */
783 case ADAU17X1_CLOCK_CONTROL:
784 case ADAU17X1_PLL_CONTROL:
785 case ADAU17X1_REC_POWER_MGMT:
786 case ADAU17X1_MICBIAS:
787 case ADAU17X1_SERIAL_PORT0:
788 case ADAU17X1_SERIAL_PORT1:
789 case ADAU17X1_CONVERTER0:
790 case ADAU17X1_CONVERTER1:
791 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
792 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
793 case ADAU17X1_ADC_CONTROL:
794 case ADAU17X1_PLAY_POWER_MGMT:
795 case ADAU17X1_DAC_CONTROL0:
796 case ADAU17X1_DAC_CONTROL1:
797 case ADAU17X1_DAC_CONTROL2:
798 case ADAU17X1_SERIAL_PORT_PAD:
799 case ADAU17X1_CONTROL_PORT_PAD0:
800 case ADAU17X1_CONTROL_PORT_PAD1:
801 case ADAU17X1_DSP_SAMPLING_RATE:
802 case ADAU17X1_SERIAL_INPUT_ROUTE:
803 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
804 case ADAU17X1_DSP_ENABLE:
805 case ADAU17X1_DSP_RUN:
806 case ADAU17X1_SERIAL_SAMPLING_RATE:
813 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
815 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
817 /* SigmaDSP parameter and program memory */
822 /* The PLL register is 6 bytes long */
823 case ADAU17X1_PLL_CONTROL:
824 case ADAU17X1_PLL_CONTROL + 1:
825 case ADAU17X1_PLL_CONTROL + 2:
826 case ADAU17X1_PLL_CONTROL + 3:
827 case ADAU17X1_PLL_CONTROL + 4:
828 case ADAU17X1_PLL_CONTROL + 5:
836 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
838 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
843 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
847 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
848 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
850 ret = sigmadsp_setup(adau->sigmadsp, rate);
852 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
855 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
859 EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);
861 int adau17x1_add_widgets(struct snd_soc_codec *codec)
863 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
864 struct adau *adau = snd_soc_codec_get_drvdata(codec);
867 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
868 ARRAY_SIZE(adau17x1_controls));
871 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
872 ARRAY_SIZE(adau17x1_dapm_widgets));
876 if (adau17x1_has_dsp(adau)) {
877 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
878 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
885 ret = sigmadsp_attach(adau->sigmadsp, &codec->component);
887 dev_err(codec->dev, "Failed to attach firmware: %d\n",
895 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
897 int adau17x1_add_routes(struct snd_soc_codec *codec)
899 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
900 struct adau *adau = snd_soc_codec_get_drvdata(codec);
903 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
904 ARRAY_SIZE(adau17x1_dapm_routes));
908 if (adau17x1_has_dsp(adau)) {
909 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
910 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
912 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
913 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
916 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
917 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
921 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
923 int adau17x1_resume(struct snd_soc_codec *codec)
925 struct adau *adau = snd_soc_codec_get_drvdata(codec);
927 if (adau->switch_mode)
928 adau->switch_mode(codec->dev);
930 regcache_sync(adau->regmap);
934 EXPORT_SYMBOL_GPL(adau17x1_resume);
936 int adau17x1_probe(struct device *dev, struct regmap *regmap,
937 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
938 const char *firmware_name)
944 return PTR_ERR(regmap);
946 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
950 adau->mclk = devm_clk_get(dev, "mclk");
951 if (IS_ERR(adau->mclk)) {
952 if (PTR_ERR(adau->mclk) != -ENOENT)
953 return PTR_ERR(adau->mclk);
954 /* Clock is optional (for the driver) */
956 } else if (adau->mclk) {
957 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
960 * Any valid PLL output rate will work at this point, use one
961 * that is likely to be chosen later as well. The register will
962 * be written when the PLL is powered up for the first time.
964 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
969 ret = clk_prepare_enable(adau->mclk);
974 adau->regmap = regmap;
975 adau->switch_mode = switch_mode;
978 dev_set_drvdata(dev, adau);
981 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL,
983 if (IS_ERR(adau->sigmadsp)) {
984 dev_warn(dev, "Could not find firmware file: %ld\n",
985 PTR_ERR(adau->sigmadsp));
986 adau->sigmadsp = NULL;
995 EXPORT_SYMBOL_GPL(adau17x1_probe);
997 void adau17x1_remove(struct device *dev)
999 struct adau *adau = dev_get_drvdata(dev);
1001 snd_soc_unregister_codec(dev);
1003 clk_disable_unprepare(adau->mclk);
1005 EXPORT_SYMBOL_GPL(adau17x1_remove);
1007 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
1008 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1009 MODULE_LICENSE("GPL");