sound/pci/rme9652/hdsp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   4  *
   5  *      Copyright (c) 2002  Paul Davis
   6  *                          Marcus Andersson
   7  *                          Thomas Charbonnel
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/pci.h>
  14 #include <linux/firmware.h>
  15 #include <linux/module.h>
  16 #include <linux/math64.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/io.h>
  19 #include <linux/nospec.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/control.h>
  23 #include <sound/pcm.h>
  24 #include <sound/info.h>
  25 #include <sound/asoundef.h>
  26 #include <sound/rawmidi.h>
  27 #include <sound/hwdep.h>
  28 #include <sound/initval.h>
  29 #include <sound/hdsp.h>
  30
  31 #include <asm/byteorder.h>
  32 #include <asm/current.h>
  33
  34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  37
  38 module_param_array(index, int, NULL, 0444);
  39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  40 module_param_array(id, charp, NULL, 0444);
  41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  42 module_param_array(enable, bool, NULL, 0444);
  43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  45 MODULE_DESCRIPTION("RME Hammerfall DSP");
  46 MODULE_LICENSE("GPL");
  47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  48                 "{RME HDSP-9652},"
  49                 "{RME HDSP-9632}}");
  50 /*(DEBLOBBED)*/
  51
  52 #define HDSP_MAX_CHANNELS        26
  53 #define HDSP_MAX_DS_CHANNELS     14
  54 #define HDSP_MAX_QS_CHANNELS     8
  55 #define DIGIFACE_SS_CHANNELS     26
  56 #define DIGIFACE_DS_CHANNELS     14
  57 #define MULTIFACE_SS_CHANNELS    18
  58 #define MULTIFACE_DS_CHANNELS    14
  59 #define H9652_SS_CHANNELS        26
  60 #define H9652_DS_CHANNELS        14
  61 /* This does not include possible Analog Extension Boards
  62    AEBs are detected at card initialization
  63 */
  64 #define H9632_SS_CHANNELS        12
  65 #define H9632_DS_CHANNELS        8
  66 #define H9632_QS_CHANNELS        4
  67 #define RPM_CHANNELS             6
  68
  69 /* Write registers. These are defined as byte-offsets from the iobase value.
  70  */
  71 #define HDSP_resetPointer               0
  72 #define HDSP_freqReg                    0
  73 #define HDSP_outputBufferAddress        32
  74 #define HDSP_inputBufferAddress         36
  75 #define HDSP_controlRegister            64
  76 #define HDSP_interruptConfirmation      96
  77 #define HDSP_outputEnable               128
  78 #define HDSP_control2Reg                256
  79 #define HDSP_midiDataOut0               352
  80 #define HDSP_midiDataOut1               356
  81 #define HDSP_fifoData                   368
  82 #define HDSP_inputEnable                384
  83
  84 /* Read registers. These are defined as byte-offsets from the iobase value
  85  */
  86
  87 #define HDSP_statusRegister    0
  88 #define HDSP_timecode        128
  89 #define HDSP_status2Register 192
  90 #define HDSP_midiDataIn0     360
  91 #define HDSP_midiDataIn1     364
  92 #define HDSP_midiStatusOut0  384
  93 #define HDSP_midiStatusOut1  388
  94 #define HDSP_midiStatusIn0   392
  95 #define HDSP_midiStatusIn1   396
  96 #define HDSP_fifoStatus      400
  97
  98 /* the meters are regular i/o-mapped registers, but offset
  99    considerably from the rest. the peak registers are reset
 100    when read; the least-significant 4 bits are full-scale counters;
 101    the actual peak value is in the most-significant 24 bits.
 102 */
 103
 104 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 105 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 106 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 107 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 108 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 109
 110
 111 /* This is for H9652 cards
 112    Peak values are read downward from the base
 113    Rms values are read upward
 114    There are rms values for the outputs too
 115    26*3 values are read in ss mode
 116    14*3 in ds mode, with no gap between values
 117 */
 118 #define HDSP_9652_peakBase      7164
 119 #define HDSP_9652_rmsBase       4096
 120
 121 /* c.f. the hdsp_9632_meters_t struct */
 122 #define HDSP_9632_metersBase    4096
 123
 124 #define HDSP_IO_EXTENT     7168
 125
 126 /* control2 register bits */
 127
 128 #define HDSP_TMS                0x01
 129 #define HDSP_TCK                0x02
 130 #define HDSP_TDI                0x04
 131 #define HDSP_JTAG               0x08
 132 #define HDSP_PWDN               0x10
 133 #define HDSP_PROGRAM            0x020
 134 #define HDSP_CONFIG_MODE_0      0x040
 135 #define HDSP_CONFIG_MODE_1      0x080
 136 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 137 #define HDSP_BIGENDIAN_MODE     0x200
 138 #define HDSP_RD_MULTIPLE        0x400
 139 #define HDSP_9652_ENABLE_MIXER  0x800
 140 #define HDSP_S200               0x800
 141 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 142 #define HDSP_CYCLIC_MODE        0x1000
 143 #define HDSP_TDO                0x10000000
 144
 145 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 146 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 147
 148 /* Control Register bits */
 149
 150 #define HDSP_Start                (1<<0)  /* start engine */
 151 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 152 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 153 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 154 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 155 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 156 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 157 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 158 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 159 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 160 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 161 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 162 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 163 #define HDSP_SyncRef2             (1<<13)
 164 #define HDSP_SPDIFInputSelect0    (1<<14)
 165 #define HDSP_SPDIFInputSelect1    (1<<15)
 166 #define HDSP_SyncRef0             (1<<16)
 167 #define HDSP_SyncRef1             (1<<17)
 168 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 169 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 170 #define HDSP_Midi0InterruptEnable (1<<22)
 171 #define HDSP_Midi1InterruptEnable (1<<23)
 172 #define HDSP_LineOut              (1<<24)
 173 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 174 #define HDSP_ADGain1              (1<<26)
 175 #define HDSP_DAGain0              (1<<27)
 176 #define HDSP_DAGain1              (1<<28)
 177 #define HDSP_PhoneGain0           (1<<29)
 178 #define HDSP_PhoneGain1           (1<<30)
 179 #define HDSP_QuadSpeed            (1<<31)
 180
 181 /* RPM uses some of the registers for special purposes */
 182 #define HDSP_RPM_Inp12            0x04A00
 183 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 184 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 185 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 186 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 187 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 188
 189 #define HDSP_RPM_Inp34            0x32000
 190 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 191 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 192 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 193 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 194 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 195
 196 #define HDSP_RPM_Bypass           0x01000
 197
 198 #define HDSP_RPM_Disconnect       0x00001
 199
 200 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 201 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 202 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 203 #define HDSP_ADGainLowGain     0
 204
 205 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 206 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 207 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 208 #define HDSP_DAGainMinus10dBV    0
 209
 210 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 211 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 212 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 213 #define HDSP_PhoneGainMinus12dB  0
 214
 215 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 216 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 217
 218 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 219 #define HDSP_SPDIFInputADAT1    0
 220 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 221 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 222 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 223
 224 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 225 #define HDSP_SyncRef_ADAT1       0
 226 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 227 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 228 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 229 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 230 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 231
 232 /* Sample Clock Sources */
 233
 234 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 235 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 236 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 240 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 241 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 242 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 243 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 244
 245 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 246
 247 #define HDSP_SYNC_FROM_WORD      0
 248 #define HDSP_SYNC_FROM_SPDIF     1
 249 #define HDSP_SYNC_FROM_ADAT1     2
 250 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 251 #define HDSP_SYNC_FROM_ADAT2     4
 252 #define HDSP_SYNC_FROM_ADAT3     5
 253
 254 /* SyncCheck status */
 255
 256 #define HDSP_SYNC_CHECK_NO_LOCK 0
 257 #define HDSP_SYNC_CHECK_LOCK    1
 258 #define HDSP_SYNC_CHECK_SYNC    2
 259
 260 /* AutoSync references - used by "autosync_ref" control switch */
 261
 262 #define HDSP_AUTOSYNC_FROM_WORD      0
 263 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 264 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 265 #define HDSP_AUTOSYNC_FROM_NONE      3
 266 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 267 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 268 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 269
 270 /* Possible sources of S/PDIF input */
 271
 272 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 273 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 274 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 275 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 276
 277 #define HDSP_Frequency32KHz    HDSP_Frequency0
 278 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 279 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 280 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 281 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 282 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 283 /* For H9632 cards */
 284 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 285 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 286 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 287 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 288         return 104857600000000 / rate; // 100 MHz
 289         return 110100480000000 / rate; // 105 MHz
 290 */
 291 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 292
 293 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 294 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 295
 296 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 297 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 298
 299 /* Status Register bits */
 300
 301 #define HDSP_audioIRQPending    (1<<0)
 302 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 303 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 304 #define HDSP_Lock1              (1<<2)
 305 #define HDSP_Lock0              (1<<3)
 306 #define HDSP_SPDIFSync          (1<<4)
 307 #define HDSP_TimecodeLock       (1<<5)
 308 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 309 #define HDSP_Sync2              (1<<16)
 310 #define HDSP_Sync1              (1<<17)
 311 #define HDSP_Sync0              (1<<18)
 312 #define HDSP_DoubleSpeedStatus  (1<<19)
 313 #define HDSP_ConfigError        (1<<20)
 314 #define HDSP_DllError           (1<<21)
 315 #define HDSP_spdifFrequency0    (1<<22)
 316 #define HDSP_spdifFrequency1    (1<<23)
 317 #define HDSP_spdifFrequency2    (1<<24)
 318 #define HDSP_SPDIFErrorFlag     (1<<25)
 319 #define HDSP_BufferID           (1<<26)
 320 #define HDSP_TimecodeSync       (1<<27)
 321 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 322 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 323 #define HDSP_midi0IRQPending    (1<<30)
 324 #define HDSP_midi1IRQPending    (1<<31)
 325
 326 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 327 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 328                                       HDSP_spdifFrequency1|\
 329                                       HDSP_spdifFrequency2|\
 330                                       HDSP_spdifFrequency3)
 331
 332 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 333 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 334 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 335
 336 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 337 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 338 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 339
 340 /* This is for H9632 cards */
 341 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 342                                      HDSP_spdifFrequency1|\
 343                                      HDSP_spdifFrequency2)
 344 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 345 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 346
 347 /* Status2 Register bits */
 348
 349 #define HDSP_version0     (1<<0)
 350 #define HDSP_version1     (1<<1)
 351 #define HDSP_version2     (1<<2)
 352 #define HDSP_wc_lock      (1<<3)
 353 #define HDSP_wc_sync      (1<<4)
 354 #define HDSP_inp_freq0    (1<<5)
 355 #define HDSP_inp_freq1    (1<<6)
 356 #define HDSP_inp_freq2    (1<<7)
 357 #define HDSP_SelSyncRef0  (1<<8)
 358 #define HDSP_SelSyncRef1  (1<<9)
 359 #define HDSP_SelSyncRef2  (1<<10)
 360
 361 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 362
 363 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 364 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 365 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 366 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 367 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 368 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 369 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 370 /* FIXME : more values for 9632 cards ? */
 371
 372 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 373 #define HDSP_SelSyncRef_ADAT1      0
 374 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 375 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 376 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 377 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 378 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 379
 380 /* Card state flags */
 381
 382 #define HDSP_InitializationComplete  (1<<0)
 383 #define HDSP_FirmwareLoaded          (1<<1)
 384 #define HDSP_FirmwareCached          (1<<2)
 385
 386 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 387
 388 #define HDSP_LONG_WAIT   5000
 389 #define HDSP_SHORT_WAIT  30
 390
 391 #define UNITY_GAIN                       32768
 392 #define MINUS_INFINITY_GAIN              0
 393
 394 /* the size of a substream (1 mono data stream) */
 395
 396 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 397 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 398
 399 /* the size of the area we need to allocate for DMA transfers. the
 400    size is the same regardless of the number of channels - the
 401    Multiface still uses the same memory area.
 402
 403    Note that we allocate 1 more channel than is apparently needed
 404    because the h/w seems to write 1 byte beyond the end of the last
 405    page. Sigh.
 406 */
 407
 408 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 409 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 410
 411 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 412
 413 struct hdsp_9632_meters {
 414     u32 input_peak[16];
 415     u32 playback_peak[16];
 416     u32 output_peak[16];
 417     u32 xxx_peak[16];
 418     u32 padding[64];
 419     u32 input_rms_low[16];
 420     u32 playback_rms_low[16];
 421     u32 output_rms_low[16];
 422     u32 xxx_rms_low[16];
 423     u32 input_rms_high[16];
 424     u32 playback_rms_high[16];
 425     u32 output_rms_high[16];
 426     u32 xxx_rms_high[16];
 427 };
 428
 429 struct hdsp_midi {
 430     struct hdsp             *hdsp;
 431     int                      id;
 432     struct snd_rawmidi           *rmidi;
 433     struct snd_rawmidi_substream *input;
 434     struct snd_rawmidi_substream *output;
 435     char                     istimer; /* timer in use */
 436     struct timer_list        timer;
 437     spinlock_t               lock;
 438     int                      pending;
 439 };
 440
 441 struct hdsp {
 442         spinlock_t            lock;
 443         struct snd_pcm_substream *capture_substream;
 444         struct snd_pcm_substream *playback_substream;
 445         struct hdsp_midi      midi[2];
 446         struct tasklet_struct midi_tasklet;
 447         int                   use_midi_tasklet;
 448         int                   precise_ptr;
 449         u32                   control_register;      /* cached value */
 450         u32                   control2_register;     /* cached value */
 451         u32                   creg_spdif;
 452         u32                   creg_spdif_stream;
 453         int                   clock_source_locked;
 454         char                 *card_name;         /* digiface/multiface/rpm */
 455         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 456         unsigned short        firmware_rev;
 457         unsigned short        state;                 /* stores state bits */
 458         const struct firmware *firmware;
 459         u32                  *fw_uploaded;
 460         size_t                period_bytes;          /* guess what this is */
 461         unsigned char         max_channels;
 462         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 463         unsigned char         ds_in_channels;
 464         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 465         unsigned char         qs_out_channels;
 466         unsigned char         ds_out_channels;
 467         unsigned char         ss_out_channels;
 468
 469         struct snd_dma_buffer capture_dma_buf;
 470         struct snd_dma_buffer playback_dma_buf;
 471         unsigned char        *capture_buffer;       /* suitably aligned address */
 472         unsigned char        *playback_buffer;      /* suitably aligned address */
 473
 474         pid_t                 capture_pid;
 475         pid_t                 playback_pid;
 476         int                   running;
 477         int                   system_sample_rate;
 478         char                 *channel_map;
 479         int                   dev;
 480         int                   irq;
 481         unsigned long         port;
 482         void __iomem         *iobase;
 483         struct snd_card *card;
 484         struct snd_pcm *pcm;
 485         struct snd_hwdep          *hwdep;
 486         struct pci_dev       *pci;
 487         struct snd_kcontrol *spdif_ctl;
 488         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 489         unsigned int          dds_value; /* last value written to freq register */
 490 };
 491
 492 /* These tables map the ALSA channels 1..N to the channels that we
 493    need to use in order to find the relevant channel buffer. RME
 494    refer to this kind of mapping as between "the ADAT channel and
 495    the DMA channel." We index it using the logical audio channel,
 496    and the value is the DMA channel (i.e. channel buffer number)
 497    where the data for that channel can be read/written from/to.
 498 */
 499
 500 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 501         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 502         18, 19, 20, 21, 22, 23, 24, 25
 503 };
 504
 505 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 506         /* Analog */
 507         0, 1, 2, 3, 4, 5, 6, 7,
 508         /* ADAT 2 */
 509         16, 17, 18, 19, 20, 21, 22, 23,
 510         /* SPDIF */
 511         24, 25,
 512         -1, -1, -1, -1, -1, -1, -1, -1
 513 };
 514
 515 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 516         /* ADAT channels are remapped */
 517         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 518         /* channels 12 and 13 are S/PDIF */
 519         24, 25,
 520         /* others don't exist */
 521         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 522 };
 523
 524 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 525         /* ADAT channels */
 526         0, 1, 2, 3, 4, 5, 6, 7,
 527         /* SPDIF */
 528         8, 9,
 529         /* Analog */
 530         10, 11,
 531         /* AO4S-192 and AI4S-192 extension boards */
 532         12, 13, 14, 15,
 533         /* others don't exist */
 534         -1, -1, -1, -1, -1, -1, -1, -1,
 535         -1, -1
 536 };
 537
 538 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 539         /* ADAT */
 540         1, 3, 5, 7,
 541         /* SPDIF */
 542         8, 9,
 543         /* Analog */
 544         10, 11,
 545         /* AO4S-192 and AI4S-192 extension boards */
 546         12, 13, 14, 15,
 547         /* others don't exist */
 548         -1, -1, -1, -1, -1, -1, -1, -1,
 549         -1, -1, -1, -1, -1, -1
 550 };
 551
 552 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 553         /* ADAT is disabled in this mode */
 554         /* SPDIF */
 555         8, 9,
 556         /* Analog */
 557         10, 11,
 558         /* AO4S-192 and AI4S-192 extension boards */
 559         12, 13, 14, 15,
 560         /* others don't exist */
 561         -1, -1, -1, -1, -1, -1, -1, -1,
 562         -1, -1, -1, -1, -1, -1, -1, -1,
 563         -1, -1
 564 };
 565
 566 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 567 {
 568         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 569         dmab->dev.dev = snd_dma_pci_data(pci);
 570         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 571                                 size, dmab) < 0)
 572                 return -ENOMEM;
 573         return 0;
 574 }
 575
 576 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 577 {
 578         if (dmab->area)
 579                 snd_dma_free_pages(dmab);
 580 }
 581
 582
 583 static const struct pci_device_id snd_hdsp_ids[] = {
 584         {
 585                 .vendor = PCI_VENDOR_ID_XILINX,
 586                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 587                 .subvendor = PCI_ANY_ID,
 588                 .subdevice = PCI_ANY_ID,
 589         }, /* RME Hammerfall-DSP */
 590         { 0, },
 591 };
 592
 593 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 594
 595 /* prototypes */
 596 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 597 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 598 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 599 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 600 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 601 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 602 static int hdsp_autosync_ref(struct hdsp *hdsp);
 603 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 604 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 605
 606 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 607 {
 608         switch (hdsp->io_type) {
 609         case Multiface:
 610         case Digiface:
 611         case RPM:
 612         default:
 613                 if (hdsp->firmware_rev == 0xa)
 614                         return (64 * out) + (32 + (in));
 615                 else
 616                         return (52 * out) + (26 + (in));
 617         case H9632:
 618                 return (32 * out) + (16 + (in));
 619         case H9652:
 620                 return (52 * out) + (26 + (in));
 621         }
 622 }
 623
 624 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 625 {
 626         switch (hdsp->io_type) {
 627         case Multiface:
 628         case Digiface:
 629         case RPM:
 630         default:
 631                 if (hdsp->firmware_rev == 0xa)
 632                         return (64 * out) + in;
 633                 else
 634                         return (52 * out) + in;
 635         case H9632:
 636                 return (32 * out) + in;
 637         case H9652:
 638                 return (52 * out) + in;
 639         }
 640 }
 641
 642 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 643 {
 644         writel(val, hdsp->iobase + reg);
 645 }
 646
 647 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 648 {
 649         return readl (hdsp->iobase + reg);
 650 }
 651
 652 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 653 {
 654         int i;
 655
 656         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 657         for (i = 0; i < 500; i++) {
 658                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 659                                         HDSP_ConfigError)) {
 660                         if (i) {
 661                                 dev_dbg(hdsp->card->dev,
 662                                         "IO box found after %d ms\n",
 663                                                 (20 * i));
 664                         }
 665                         return 0;
 666                 }
 667                 msleep(20);
 668         }
 669         dev_err(hdsp->card->dev, "no IO box connected!\n");
 670         hdsp->state &= ~HDSP_FirmwareLoaded;
 671         return -EIO;
 672 }
 673
 674 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 675                                unsigned int delay)
 676 {
 677         unsigned int i;
 678
 679         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 680                 return 0;
 681
 682         for (i = 0; i != loops; ++i) {
 683                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 684                         msleep(delay);
 685                 else {
 686                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 687                                    i * delay);
 688                         return 0;
 689                 }
 690         }
 691
 692         dev_info(hdsp->card->dev, "no IO box connected!\n");
 693         hdsp->state &= ~HDSP_FirmwareLoaded;
 694         return -EIO;
 695 }
 696
 697 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 698
 699         int i;
 700         unsigned long flags;
 701         const u32 *cache;
 702
 703         if (hdsp->fw_uploaded)
 704                 cache = hdsp->fw_uploaded;
 705         else {
 706                 if (!hdsp->firmware)
 707                         return -ENODEV;
 708                 cache = (u32 *)hdsp->firmware->data;
 709                 if (!cache)
 710                         return -ENODEV;
 711         }
 712
 713         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 714
 715                 dev_info(hdsp->card->dev, "loading firmware\n");
 716
 717                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 718                 hdsp_write (hdsp, HDSP_fifoData, 0);
 719
 720                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 721                         dev_info(hdsp->card->dev,
 722                                  "timeout waiting for download preparation\n");
 723                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 724                         return -EIO;
 725                 }
 726
 727                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 728
 729                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 730                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 731                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 732                                 dev_info(hdsp->card->dev,
 733                                          "timeout during firmware loading\n");
 734                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 735                                 return -EIO;
 736                         }
 737                 }
 738
 739                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 740                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 741
 742                 ssleep(3);
 743 #ifdef SNDRV_BIG_ENDIAN
 744                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 745 #else
 746                 hdsp->control2_register = 0;
 747 #endif
 748                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 749                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 750
 751         }
 752         if (hdsp->state & HDSP_InitializationComplete) {
 753                 dev_info(hdsp->card->dev,
 754                          "firmware loaded from cache, restoring defaults\n");
 755                 spin_lock_irqsave(&hdsp->lock, flags);
 756                 snd_hdsp_set_defaults(hdsp);
 757                 spin_unlock_irqrestore(&hdsp->lock, flags);
 758         }
 759
 760         hdsp->state |= HDSP_FirmwareLoaded;
 761
 762         return 0;
 763 }
 764
 765 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 766 {
 767         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 768
 769                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 770                 hdsp_write(hdsp, HDSP_fifoData, 0);
 771
 772                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 773                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 774                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 775                 }
 776
 777                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 778                 hdsp_write (hdsp, HDSP_fifoData, 0);
 779                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 780                         goto set_multi;
 781
 782                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 783                 hdsp_write(hdsp, HDSP_fifoData, 0);
 784                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 785                         hdsp->io_type = Digiface;
 786                         dev_info(hdsp->card->dev, "Digiface found\n");
 787                         return 0;
 788                 }
 789
 790                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 791                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 792                 hdsp_write(hdsp, HDSP_fifoData, 0);
 793                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 794                         goto set_multi;
 795
 796                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 797                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 798                 hdsp_write(hdsp, HDSP_fifoData, 0);
 799                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 800                         goto set_multi;
 801
 802                 hdsp->io_type = RPM;
 803                 dev_info(hdsp->card->dev, "RPM found\n");
 804                 return 0;
 805         } else {
 806                 /* firmware was already loaded, get iobox type */
 807                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 808                         hdsp->io_type = RPM;
 809                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 810                         hdsp->io_type = Multiface;
 811                 else
 812                         hdsp->io_type = Digiface;
 813         }
 814         return 0;
 815
 816 set_multi:
 817         hdsp->io_type = Multiface;
 818         dev_info(hdsp->card->dev, "Multiface found\n");
 819         return 0;
 820 }
 821
 822
 823 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 824
 825 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 826 {
 827         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 828                 return 0;
 829         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 830                 hdsp->state &= ~HDSP_FirmwareLoaded;
 831                 if (! load_on_demand)
 832                         return -EIO;
 833                 dev_err(hdsp->card->dev, "firmware not present.\n");
 834                 /* try to load firmware */
 835                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 836                         if (! hdsp_request_fw_loader(hdsp))
 837                                 return 0;
 838                         dev_err(hdsp->card->dev,
 839                                    "No firmware loaded nor cached, please upload firmware.\n");
 840                         return -EIO;
 841                 }
 842                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 843                         dev_err(hdsp->card->dev,
 844                                    "Firmware loading from cache failed, please upload manually.\n");
 845                         return -EIO;
 846                 }
 847         }
 848         return 0;
 849 }
 850
 851
 852 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 853 {
 854         int i;
 855
 856         /* the fifoStatus registers reports on how many words
 857            are available in the command FIFO.
 858         */
 859
 860         for (i = 0; i < timeout; i++) {
 861
 862                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 863                         return 0;
 864
 865                 /* not very friendly, but we only do this during a firmware
 866                    load and changing the mixer, so we just put up with it.
 867                 */
 868
 869                 udelay (100);
 870         }
 871
 872         dev_warn(hdsp->card->dev,
 873                  "wait for FIFO status <= %d failed after %d iterations\n",
 874                     count, timeout);
 875         return -1;
 876 }
 877
 878 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 879 {
 880         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 881                 return 0;
 882
 883         return hdsp->mixer_matrix[addr];
 884 }
 885
 886 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 887 {
 888         unsigned int ad;
 889
 890         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 891                 return -1;
 892
 893         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 894
 895                 /* from martin bjornsen:
 896
 897                    "You can only write dwords to the
 898                    mixer memory which contain two
 899                    mixer values in the low and high
 900                    word. So if you want to change
 901                    value 0 you have to read value 1
 902                    from the cache and write both to
 903                    the first dword in the mixer
 904                    memory."
 905                 */
 906
 907                 if (hdsp->io_type == H9632 && addr >= 512)
 908                         return 0;
 909
 910                 if (hdsp->io_type == H9652 && addr >= 1352)
 911                         return 0;
 912
 913                 hdsp->mixer_matrix[addr] = data;
 914
 915
 916                 /* `addr' addresses a 16-bit wide address, but
 917                    the address space accessed via hdsp_write
 918                    uses byte offsets. put another way, addr
 919                    varies from 0 to 1351, but to access the
 920                    corresponding memory location, we need
 921                    to access 0 to 2703 ...
 922                 */
 923                 ad = addr/2;
 924
 925                 hdsp_write (hdsp, 4096 + (ad*4),
 926                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 927                             hdsp->mixer_matrix[addr&0x7fe]);
 928
 929                 return 0;
 930
 931         } else {
 932
 933                 ad = (addr << 16) + data;
 934
 935                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 936                         return -1;
 937
 938                 hdsp_write (hdsp, HDSP_fifoData, ad);
 939                 hdsp->mixer_matrix[addr] = data;
 940
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 947 {
 948         unsigned long flags;
 949         int ret = 1;
 950
 951         spin_lock_irqsave(&hdsp->lock, flags);
 952         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 953             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 954                 ret = 0;
 955         spin_unlock_irqrestore(&hdsp->lock, flags);
 956         return ret;
 957 }
 958
 959 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 960 {
 961         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 962         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 963
 964         /* For the 9632, the mask is different */
 965         if (hdsp->io_type == H9632)
 966                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 967
 968         if (status & HDSP_SPDIFErrorFlag)
 969                 return 0;
 970
 971         switch (rate_bits) {
 972         case HDSP_spdifFrequency32KHz: return 32000;
 973         case HDSP_spdifFrequency44_1KHz: return 44100;
 974         case HDSP_spdifFrequency48KHz: return 48000;
 975         case HDSP_spdifFrequency64KHz: return 64000;
 976         case HDSP_spdifFrequency88_2KHz: return 88200;
 977         case HDSP_spdifFrequency96KHz: return 96000;
 978         case HDSP_spdifFrequency128KHz:
 979                 if (hdsp->io_type == H9632) return 128000;
 980                 break;
 981         case HDSP_spdifFrequency176_4KHz:
 982                 if (hdsp->io_type == H9632) return 176400;
 983                 break;
 984         case HDSP_spdifFrequency192KHz:
 985                 if (hdsp->io_type == H9632) return 192000;
 986                 break;
 987         default:
 988                 break;
 989         }
 990         dev_warn(hdsp->card->dev,
 991                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
 992                  rate_bits, status);
 993         return 0;
 994 }
 995
 996 static int hdsp_external_sample_rate(struct hdsp *hdsp)
 997 {
 998         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 999         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1000
1001         /* For the 9632 card, there seems to be no bit for indicating external
1002          * sample rate greater than 96kHz. The card reports the corresponding
1003          * single speed. So the best means seems to get spdif rate when
1004          * autosync reference is spdif */
1005         if (hdsp->io_type == H9632 &&
1006             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1007                  return hdsp_spdif_sample_rate(hdsp);
1008
1009         switch (rate_bits) {
1010         case HDSP_systemFrequency32:   return 32000;
1011         case HDSP_systemFrequency44_1: return 44100;
1012         case HDSP_systemFrequency48:   return 48000;
1013         case HDSP_systemFrequency64:   return 64000;
1014         case HDSP_systemFrequency88_2: return 88200;
1015         case HDSP_systemFrequency96:   return 96000;
1016         default:
1017                 return 0;
1018         }
1019 }
1020
1021 static void hdsp_compute_period_size(struct hdsp *hdsp)
1022 {
1023         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1024 }
1025
1026 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1027 {
1028         int position;
1029
1030         position = hdsp_read(hdsp, HDSP_statusRegister);
1031
1032         if (!hdsp->precise_ptr)
1033                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1034
1035         position &= HDSP_BufferPositionMask;
1036         position /= 4;
1037         position &= (hdsp->period_bytes/2) - 1;
1038         return position;
1039 }
1040
1041 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1042 {
1043         hdsp_write (hdsp, HDSP_resetPointer, 0);
1044         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1045                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1046                  * requires (?) to write again DDS value after a reset pointer
1047                  * (at least, it works like this) */
1048                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1049 }
1050
1051 static void hdsp_start_audio(struct hdsp *s)
1052 {
1053         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1054         hdsp_write(s, HDSP_controlRegister, s->control_register);
1055 }
1056
1057 static void hdsp_stop_audio(struct hdsp *s)
1058 {
1059         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1060         hdsp_write(s, HDSP_controlRegister, s->control_register);
1061 }
1062
1063 static void hdsp_silence_playback(struct hdsp *hdsp)
1064 {
1065         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1066 }
1067
1068 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1069 {
1070         int n;
1071
1072         spin_lock_irq(&s->lock);
1073
1074         frames >>= 7;
1075         n = 0;
1076         while (frames) {
1077                 n++;
1078                 frames >>= 1;
1079         }
1080
1081         s->control_register &= ~HDSP_LatencyMask;
1082         s->control_register |= hdsp_encode_latency(n);
1083
1084         hdsp_write(s, HDSP_controlRegister, s->control_register);
1085
1086         hdsp_compute_period_size(s);
1087
1088         spin_unlock_irq(&s->lock);
1089
1090         return 0;
1091 }
1092
1093 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1094 {
1095         u64 n;
1096
1097         if (rate >= 112000)
1098                 rate /= 4;
1099         else if (rate >= 56000)
1100                 rate /= 2;
1101
1102         n = DDS_NUMERATOR;
1103         n = div_u64(n, rate);
1104         /* n should be less than 2^32 for being written to FREQ register */
1105         snd_BUG_ON(n >> 32);
1106         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1107            value to write it after a reset */
1108         hdsp->dds_value = n;
1109         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1110 }
1111
1112 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1113 {
1114         int reject_if_open = 0;
1115         int current_rate;
1116         int rate_bits;
1117
1118         /* ASSUMPTION: hdsp->lock is either held, or
1119            there is no need for it (e.g. during module
1120            initialization).
1121         */
1122
1123         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1124                 if (called_internally) {
1125                         /* request from ctl or card initialization */
1126                         dev_err(hdsp->card->dev,
1127                                 "device is not running as a clock master: cannot set sample rate.\n");
1128                         return -1;
1129                 } else {
1130                         /* hw_param request while in AutoSync mode */
1131                         int external_freq = hdsp_external_sample_rate(hdsp);
1132                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1133
1134                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1135                                 dev_info(hdsp->card->dev,
1136                                          "Detected ADAT in double speed mode\n");
1137                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1138                                 dev_info(hdsp->card->dev,
1139                                          "Detected ADAT in quad speed mode\n");
1140                         else if (rate != external_freq) {
1141                                 dev_info(hdsp->card->dev,
1142                                          "No AutoSync source for requested rate\n");
1143                                 return -1;
1144                         }
1145                 }
1146         }
1147
1148         current_rate = hdsp->system_sample_rate;
1149
1150         /* Changing from a "single speed" to a "double speed" rate is
1151            not allowed if any substreams are open. This is because
1152            such a change causes a shift in the location of
1153            the DMA buffers and a reduction in the number of available
1154            buffers.
1155
1156            Note that a similar but essentially insoluble problem
1157            exists for externally-driven rate changes. All we can do
1158            is to flag rate changes in the read/write routines.  */
1159
1160         if (rate > 96000 && hdsp->io_type != H9632)
1161                 return -EINVAL;
1162
1163         switch (rate) {
1164         case 32000:
1165                 if (current_rate > 48000)
1166                         reject_if_open = 1;
1167                 rate_bits = HDSP_Frequency32KHz;
1168                 break;
1169         case 44100:
1170                 if (current_rate > 48000)
1171                         reject_if_open = 1;
1172                 rate_bits = HDSP_Frequency44_1KHz;
1173                 break;
1174         case 48000:
1175                 if (current_rate > 48000)
1176                         reject_if_open = 1;
1177                 rate_bits = HDSP_Frequency48KHz;
1178                 break;
1179         case 64000:
1180                 if (current_rate <= 48000 || current_rate > 96000)
1181                         reject_if_open = 1;
1182                 rate_bits = HDSP_Frequency64KHz;
1183                 break;
1184         case 88200:
1185                 if (current_rate <= 48000 || current_rate > 96000)
1186                         reject_if_open = 1;
1187                 rate_bits = HDSP_Frequency88_2KHz;
1188                 break;
1189         case 96000:
1190                 if (current_rate <= 48000 || current_rate > 96000)
1191                         reject_if_open = 1;
1192                 rate_bits = HDSP_Frequency96KHz;
1193                 break;
1194         case 128000:
1195                 if (current_rate < 128000)
1196                         reject_if_open = 1;
1197                 rate_bits = HDSP_Frequency128KHz;
1198                 break;
1199         case 176400:
1200                 if (current_rate < 128000)
1201                         reject_if_open = 1;
1202                 rate_bits = HDSP_Frequency176_4KHz;
1203                 break;
1204         case 192000:
1205                 if (current_rate < 128000)
1206                         reject_if_open = 1;
1207                 rate_bits = HDSP_Frequency192KHz;
1208                 break;
1209         default:
1210                 return -EINVAL;
1211         }
1212
1213         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1214                 dev_warn(hdsp->card->dev,
1215                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1216                             hdsp->capture_pid,
1217                             hdsp->playback_pid);
1218                 return -EBUSY;
1219         }
1220
1221         hdsp->control_register &= ~HDSP_FrequencyMask;
1222         hdsp->control_register |= rate_bits;
1223         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1224
1225         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1226         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1227                 hdsp_set_dds_value(hdsp, rate);
1228
1229         if (rate >= 128000) {
1230                 hdsp->channel_map = channel_map_H9632_qs;
1231         } else if (rate > 48000) {
1232                 if (hdsp->io_type == H9632)
1233                         hdsp->channel_map = channel_map_H9632_ds;
1234                 else
1235                         hdsp->channel_map = channel_map_ds;
1236         } else {
1237                 switch (hdsp->io_type) {
1238                 case RPM:
1239                 case Multiface:
1240                         hdsp->channel_map = channel_map_mf_ss;
1241                         break;
1242                 case Digiface:
1243                 case H9652:
1244                         hdsp->channel_map = channel_map_df_ss;
1245                         break;
1246                 case H9632:
1247                         hdsp->channel_map = channel_map_H9632_ss;
1248                         break;
1249                 default:
1250                         /* should never happen */
1251                         break;
1252                 }
1253         }
1254
1255         hdsp->system_sample_rate = rate;
1256
1257         return 0;
1258 }
1259
1260 /*----------------------------------------------------------------------------
1261    MIDI
1262   ----------------------------------------------------------------------------*/
1263
1264 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1265 {
1266         /* the hardware already does the relevant bit-mask with 0xff */
1267         if (id)
1268                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1269         else
1270                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1271 }
1272
1273 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1274 {
1275         /* the hardware already does the relevant bit-mask with 0xff */
1276         if (id)
1277                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1278         else
1279                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1280 }
1281
1282 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1283 {
1284         if (id)
1285                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1286         else
1287                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1288 }
1289
1290 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1291 {
1292         int fifo_bytes_used;
1293
1294         if (id)
1295                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1296         else
1297                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1298
1299         if (fifo_bytes_used < 128)
1300                 return  128 - fifo_bytes_used;
1301         else
1302                 return 0;
1303 }
1304
1305 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1306 {
1307         while (snd_hdsp_midi_input_available (hdsp, id))
1308                 snd_hdsp_midi_read_byte (hdsp, id);
1309 }
1310
1311 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1312 {
1313         unsigned long flags;
1314         int n_pending;
1315         int to_write;
1316         int i;
1317         unsigned char buf[128];
1318
1319         /* Output is not interrupt driven */
1320
1321         spin_lock_irqsave (&hmidi->lock, flags);
1322         if (hmidi->output) {
1323                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1324                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1325                                 if (n_pending > (int)sizeof (buf))
1326                                         n_pending = sizeof (buf);
1327
1328                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1329                                         for (i = 0; i < to_write; ++i)
1330                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1331                                 }
1332                         }
1333                 }
1334         }
1335         spin_unlock_irqrestore (&hmidi->lock, flags);
1336         return 0;
1337 }
1338
1339 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1340 {
1341         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1342         unsigned long flags;
1343         int n_pending;
1344         int i;
1345
1346         spin_lock_irqsave (&hmidi->lock, flags);
1347         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1348                 if (hmidi->input) {
1349                         if (n_pending > (int)sizeof (buf))
1350                                 n_pending = sizeof (buf);
1351                         for (i = 0; i < n_pending; ++i)
1352                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1353                         if (n_pending)
1354                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1355                 } else {
1356                         /* flush the MIDI input FIFO */
1357                         while (--n_pending)
1358                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1359                 }
1360         }
1361         hmidi->pending = 0;
1362         if (hmidi->id)
1363                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1364         else
1365                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1366         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1367         spin_unlock_irqrestore (&hmidi->lock, flags);
1368         return snd_hdsp_midi_output_write (hmidi);
1369 }
1370
1371 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1372 {
1373         struct hdsp *hdsp;
1374         struct hdsp_midi *hmidi;
1375         unsigned long flags;
1376         u32 ie;
1377
1378         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1379         hdsp = hmidi->hdsp;
1380         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1381         spin_lock_irqsave (&hdsp->lock, flags);
1382         if (up) {
1383                 if (!(hdsp->control_register & ie)) {
1384                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1385                         hdsp->control_register |= ie;
1386                 }
1387         } else {
1388                 hdsp->control_register &= ~ie;
1389                 tasklet_kill(&hdsp->midi_tasklet);
1390         }
1391
1392         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1393         spin_unlock_irqrestore (&hdsp->lock, flags);
1394 }
1395
1396 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1397 {
1398         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1399         unsigned long flags;
1400
1401         snd_hdsp_midi_output_write(hmidi);
1402         spin_lock_irqsave (&hmidi->lock, flags);
1403
1404         /* this does not bump hmidi->istimer, because the
1405            kernel automatically removed the timer when it
1406            expired, and we are now adding it back, thus
1407            leaving istimer wherever it was set before.
1408         */
1409
1410         if (hmidi->istimer)
1411                 mod_timer(&hmidi->timer, 1 + jiffies);
1412
1413         spin_unlock_irqrestore (&hmidi->lock, flags);
1414 }
1415
1416 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1417 {
1418         struct hdsp_midi *hmidi;
1419         unsigned long flags;
1420
1421         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1422         spin_lock_irqsave (&hmidi->lock, flags);
1423         if (up) {
1424                 if (!hmidi->istimer) {
1425                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1426                                     0);
1427                         mod_timer(&hmidi->timer, 1 + jiffies);
1428                         hmidi->istimer++;
1429                 }
1430         } else {
1431                 if (hmidi->istimer && --hmidi->istimer <= 0)
1432                         del_timer (&hmidi->timer);
1433         }
1434         spin_unlock_irqrestore (&hmidi->lock, flags);
1435         if (up)
1436                 snd_hdsp_midi_output_write(hmidi);
1437 }
1438
1439 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1440 {
1441         struct hdsp_midi *hmidi;
1442
1443         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1444         spin_lock_irq (&hmidi->lock);
1445         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1446         hmidi->input = substream;
1447         spin_unlock_irq (&hmidi->lock);
1448
1449         return 0;
1450 }
1451
1452 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1453 {
1454         struct hdsp_midi *hmidi;
1455
1456         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1457         spin_lock_irq (&hmidi->lock);
1458         hmidi->output = substream;
1459         spin_unlock_irq (&hmidi->lock);
1460
1461         return 0;
1462 }
1463
1464 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1465 {
1466         struct hdsp_midi *hmidi;
1467
1468         snd_hdsp_midi_input_trigger (substream, 0);
1469
1470         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1471         spin_lock_irq (&hmidi->lock);
1472         hmidi->input = NULL;
1473         spin_unlock_irq (&hmidi->lock);
1474
1475         return 0;
1476 }
1477
1478 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1479 {
1480         struct hdsp_midi *hmidi;
1481
1482         snd_hdsp_midi_output_trigger (substream, 0);
1483
1484         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1485         spin_lock_irq (&hmidi->lock);
1486         hmidi->output = NULL;
1487         spin_unlock_irq (&hmidi->lock);
1488
1489         return 0;
1490 }
1491
1492 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1493 {
1494         .open =         snd_hdsp_midi_output_open,
1495         .close =        snd_hdsp_midi_output_close,
1496         .trigger =      snd_hdsp_midi_output_trigger,
1497 };
1498
1499 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1500 {
1501         .open =         snd_hdsp_midi_input_open,
1502         .close =        snd_hdsp_midi_input_close,
1503         .trigger =      snd_hdsp_midi_input_trigger,
1504 };
1505
1506 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1507 {
1508         char buf[40];
1509
1510         hdsp->midi[id].id = id;
1511         hdsp->midi[id].rmidi = NULL;
1512         hdsp->midi[id].input = NULL;
1513         hdsp->midi[id].output = NULL;
1514         hdsp->midi[id].hdsp = hdsp;
1515         hdsp->midi[id].istimer = 0;
1516         hdsp->midi[id].pending = 0;
1517         spin_lock_init (&hdsp->midi[id].lock);
1518
1519         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1520         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1521                 return -1;
1522
1523         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1524         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1525
1526         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1527         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1528
1529         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1530                 SNDRV_RAWMIDI_INFO_INPUT |
1531                 SNDRV_RAWMIDI_INFO_DUPLEX;
1532
1533         return 0;
1534 }
1535
1536 /*-----------------------------------------------------------------------------
1537   Control Interface
1538   ----------------------------------------------------------------------------*/
1539
1540 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1541 {
1542         u32 val = 0;
1543         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1544         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1545         if (val & HDSP_SPDIFProfessional)
1546                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1547         else
1548                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1549         return val;
1550 }
1551
1552 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1553 {
1554         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1555                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1556         if (val & HDSP_SPDIFProfessional)
1557                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1558         else
1559                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1560 }
1561
1562 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1563 {
1564         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1565         uinfo->count = 1;
1566         return 0;
1567 }
1568
1569 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1570 {
1571         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1572
1573         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1574         return 0;
1575 }
1576
1577 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1578 {
1579         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1580         int change;
1581         u32 val;
1582
1583         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1584         spin_lock_irq(&hdsp->lock);
1585         change = val != hdsp->creg_spdif;
1586         hdsp->creg_spdif = val;
1587         spin_unlock_irq(&hdsp->lock);
1588         return change;
1589 }
1590
1591 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1592 {
1593         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1594         uinfo->count = 1;
1595         return 0;
1596 }
1597
1598 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1599 {
1600         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601
1602         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1603         return 0;
1604 }
1605
1606 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1607 {
1608         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1609         int change;
1610         u32 val;
1611
1612         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1613         spin_lock_irq(&hdsp->lock);
1614         change = val != hdsp->creg_spdif_stream;
1615         hdsp->creg_spdif_stream = val;
1616         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1617         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1618         spin_unlock_irq(&hdsp->lock);
1619         return change;
1620 }
1621
1622 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1623 {
1624         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1625         uinfo->count = 1;
1626         return 0;
1627 }
1628
1629 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1630 {
1631         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1632         return 0;
1633 }
1634
1635 #define HDSP_SPDIF_IN(xname, xindex) \
1636 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1637   .name = xname, \
1638   .index = xindex, \
1639   .info = snd_hdsp_info_spdif_in, \
1640   .get = snd_hdsp_get_spdif_in, \
1641   .put = snd_hdsp_put_spdif_in }
1642
1643 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1644 {
1645         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1646 }
1647
1648 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1649 {
1650         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1651         hdsp->control_register |= hdsp_encode_spdif_in(in);
1652         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1653         return 0;
1654 }
1655
1656 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1657 {
1658         static const char * const texts[4] = {
1659                 "Optical", "Coaxial", "Internal", "AES"
1660         };
1661         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1662
1663         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1664                                  texts);
1665 }
1666
1667 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1668 {
1669         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1670
1671         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1672         return 0;
1673 }
1674
1675 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1676 {
1677         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1678         int change;
1679         unsigned int val;
1680
1681         if (!snd_hdsp_use_is_exclusive(hdsp))
1682                 return -EBUSY;
1683         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1684         spin_lock_irq(&hdsp->lock);
1685         change = val != hdsp_spdif_in(hdsp);
1686         if (change)
1687                 hdsp_set_spdif_input(hdsp, val);
1688         spin_unlock_irq(&hdsp->lock);
1689         return change;
1690 }
1691
1692 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1693 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1694         .name = xname, \
1695         .private_value = xindex, \
1696         .info = snd_hdsp_info_toggle_setting, \
1697         .get = snd_hdsp_get_toggle_setting, \
1698         .put = snd_hdsp_put_toggle_setting \
1699 }
1700
1701 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1702 {
1703         return (hdsp->control_register & regmask) ? 1 : 0;
1704 }
1705
1706 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1707 {
1708         if (out)
1709                 hdsp->control_register |= regmask;
1710         else
1711                 hdsp->control_register &= ~regmask;
1712         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1713
1714         return 0;
1715 }
1716
1717 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1718
1719 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1720                 struct snd_ctl_elem_value *ucontrol)
1721 {
1722         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1723         u32 regmask = kcontrol->private_value;
1724
1725         spin_lock_irq(&hdsp->lock);
1726         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1727         spin_unlock_irq(&hdsp->lock);
1728         return 0;
1729 }
1730
1731 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1732                 struct snd_ctl_elem_value *ucontrol)
1733 {
1734         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1735         u32 regmask = kcontrol->private_value;
1736         int change;
1737         unsigned int val;
1738
1739         if (!snd_hdsp_use_is_exclusive(hdsp))
1740                 return -EBUSY;
1741         val = ucontrol->value.integer.value[0] & 1;
1742         spin_lock_irq(&hdsp->lock);
1743         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1744         if (change)
1745                 hdsp_set_toggle_setting(hdsp, regmask, val);
1746         spin_unlock_irq(&hdsp->lock);
1747         return change;
1748 }
1749
1750 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1751 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1752   .name = xname, \
1753   .index = xindex, \
1754   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1755   .info = snd_hdsp_info_spdif_sample_rate, \
1756   .get = snd_hdsp_get_spdif_sample_rate \
1757 }
1758
1759 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1760 {
1761         static const char * const texts[] = {
1762                 "32000", "44100", "48000", "64000", "88200", "96000",
1763                 "None", "128000", "176400", "192000"
1764         };
1765         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1766
1767         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1768                                  texts);
1769 }
1770
1771 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1772 {
1773         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1774
1775         switch (hdsp_spdif_sample_rate(hdsp)) {
1776         case 32000:
1777                 ucontrol->value.enumerated.item[0] = 0;
1778                 break;
1779         case 44100:
1780                 ucontrol->value.enumerated.item[0] = 1;
1781                 break;
1782         case 48000:
1783                 ucontrol->value.enumerated.item[0] = 2;
1784                 break;
1785         case 64000:
1786                 ucontrol->value.enumerated.item[0] = 3;
1787                 break;
1788         case 88200:
1789                 ucontrol->value.enumerated.item[0] = 4;
1790                 break;
1791         case 96000:
1792                 ucontrol->value.enumerated.item[0] = 5;
1793                 break;
1794         case 128000:
1795                 ucontrol->value.enumerated.item[0] = 7;
1796                 break;
1797         case 176400:
1798                 ucontrol->value.enumerated.item[0] = 8;
1799                 break;
1800         case 192000:
1801                 ucontrol->value.enumerated.item[0] = 9;
1802                 break;
1803         default:
1804                 ucontrol->value.enumerated.item[0] = 6;
1805         }
1806         return 0;
1807 }
1808
1809 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1811   .name = xname, \
1812   .index = xindex, \
1813   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1814   .info = snd_hdsp_info_system_sample_rate, \
1815   .get = snd_hdsp_get_system_sample_rate \
1816 }
1817
1818 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1819 {
1820         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1821         uinfo->count = 1;
1822         return 0;
1823 }
1824
1825 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1826 {
1827         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1828
1829         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1830         return 0;
1831 }
1832
1833 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1834 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1835   .name = xname, \
1836   .index = xindex, \
1837   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1838   .info = snd_hdsp_info_autosync_sample_rate, \
1839   .get = snd_hdsp_get_autosync_sample_rate \
1840 }
1841
1842 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1843 {
1844         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1845         static const char * const texts[] = {
1846                 "32000", "44100", "48000", "64000", "88200", "96000",
1847                 "None", "128000", "176400", "192000"
1848         };
1849
1850         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1851                                  texts);
1852 }
1853
1854 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1855 {
1856         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1857
1858         switch (hdsp_external_sample_rate(hdsp)) {
1859         case 32000:
1860                 ucontrol->value.enumerated.item[0] = 0;
1861                 break;
1862         case 44100:
1863                 ucontrol->value.enumerated.item[0] = 1;
1864                 break;
1865         case 48000:
1866                 ucontrol->value.enumerated.item[0] = 2;
1867                 break;
1868         case 64000:
1869                 ucontrol->value.enumerated.item[0] = 3;
1870                 break;
1871         case 88200:
1872                 ucontrol->value.enumerated.item[0] = 4;
1873                 break;
1874         case 96000:
1875                 ucontrol->value.enumerated.item[0] = 5;
1876                 break;
1877         case 128000:
1878                 ucontrol->value.enumerated.item[0] = 7;
1879                 break;
1880         case 176400:
1881                 ucontrol->value.enumerated.item[0] = 8;
1882                 break;
1883         case 192000:
1884                 ucontrol->value.enumerated.item[0] = 9;
1885                 break;
1886         default:
1887                 ucontrol->value.enumerated.item[0] = 6;
1888         }
1889         return 0;
1890 }
1891
1892 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1893 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1894   .name = xname, \
1895   .index = xindex, \
1896   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1897   .info = snd_hdsp_info_system_clock_mode, \
1898   .get = snd_hdsp_get_system_clock_mode \
1899 }
1900
1901 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1902 {
1903         if (hdsp->control_register & HDSP_ClockModeMaster)
1904                 return 0;
1905         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1906                         return 0;
1907         return 1;
1908 }
1909
1910 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1911 {
1912         static const char * const texts[] = {"Master", "Slave" };
1913
1914         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1915 }
1916
1917 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1918 {
1919         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1920
1921         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1922         return 0;
1923 }
1924
1925 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1926 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1927   .name = xname, \
1928   .index = xindex, \
1929   .info = snd_hdsp_info_clock_source, \
1930   .get = snd_hdsp_get_clock_source, \
1931   .put = snd_hdsp_put_clock_source \
1932 }
1933
1934 static int hdsp_clock_source(struct hdsp *hdsp)
1935 {
1936         if (hdsp->control_register & HDSP_ClockModeMaster) {
1937                 switch (hdsp->system_sample_rate) {
1938                 case 32000:
1939                         return 1;
1940                 case 44100:
1941                         return 2;
1942                 case 48000:
1943                         return 3;
1944                 case 64000:
1945                         return 4;
1946                 case 88200:
1947                         return 5;
1948                 case 96000:
1949                         return 6;
1950                 case 128000:
1951                         return 7;
1952                 case 176400:
1953                         return 8;
1954                 case 192000:
1955                         return 9;
1956                 default:
1957                         return 3;
1958                 }
1959         } else {
1960                 return 0;
1961         }
1962 }
1963
1964 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1965 {
1966         int rate;
1967         switch (mode) {
1968         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1969                 if (hdsp_external_sample_rate(hdsp) != 0) {
1970                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1971                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1972                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1973                         return 0;
1974                     }
1975                 }
1976                 return -1;
1977         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1978                 rate = 32000;
1979                 break;
1980         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1981                 rate = 44100;
1982                 break;
1983         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1984                 rate = 48000;
1985                 break;
1986         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1987                 rate = 64000;
1988                 break;
1989         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1990                 rate = 88200;
1991                 break;
1992         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1993                 rate = 96000;
1994                 break;
1995         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1996                 rate = 128000;
1997                 break;
1998         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1999                 rate = 176400;
2000                 break;
2001         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2002                 rate = 192000;
2003                 break;
2004         default:
2005                 rate = 48000;
2006         }
2007         hdsp->control_register |= HDSP_ClockModeMaster;
2008         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2009         hdsp_set_rate(hdsp, rate, 1);
2010         return 0;
2011 }
2012
2013 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2014 {
2015         static const char * const texts[] = {
2016                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2017                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2018                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2019                 "Internal 192.0 KHz"
2020         };
2021         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2022
2023         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2024                                  texts);
2025 }
2026
2027 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2028 {
2029         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2030
2031         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2032         return 0;
2033 }
2034
2035 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2036 {
2037         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2038         int change;
2039         int val;
2040
2041         if (!snd_hdsp_use_is_exclusive(hdsp))
2042                 return -EBUSY;
2043         val = ucontrol->value.enumerated.item[0];
2044         if (val < 0) val = 0;
2045         if (hdsp->io_type == H9632) {
2046                 if (val > 9)
2047                         val = 9;
2048         } else {
2049                 if (val > 6)
2050                         val = 6;
2051         }
2052         spin_lock_irq(&hdsp->lock);
2053         if (val != hdsp_clock_source(hdsp))
2054                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2055         else
2056                 change = 0;
2057         spin_unlock_irq(&hdsp->lock);
2058         return change;
2059 }
2060
2061 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2062
2063 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2064 {
2065         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2066
2067         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2068         return 0;
2069 }
2070
2071 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2072 {
2073         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2074         int change;
2075
2076         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2077         if (change)
2078                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2079         return change;
2080 }
2081
2082 #define HDSP_DA_GAIN(xname, xindex) \
2083 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2084   .name = xname, \
2085   .index = xindex, \
2086   .info = snd_hdsp_info_da_gain, \
2087   .get = snd_hdsp_get_da_gain, \
2088   .put = snd_hdsp_put_da_gain \
2089 }
2090
2091 static int hdsp_da_gain(struct hdsp *hdsp)
2092 {
2093         switch (hdsp->control_register & HDSP_DAGainMask) {
2094         case HDSP_DAGainHighGain:
2095                 return 0;
2096         case HDSP_DAGainPlus4dBu:
2097                 return 1;
2098         case HDSP_DAGainMinus10dBV:
2099                 return 2;
2100         default:
2101                 return 1;
2102         }
2103 }
2104
2105 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2106 {
2107         hdsp->control_register &= ~HDSP_DAGainMask;
2108         switch (mode) {
2109         case 0:
2110                 hdsp->control_register |= HDSP_DAGainHighGain;
2111                 break;
2112         case 1:
2113                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2114                 break;
2115         case 2:
2116                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2117                 break;
2118         default:
2119                 return -1;
2120
2121         }
2122         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2123         return 0;
2124 }
2125
2126 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2127 {
2128         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2129
2130         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2131 }
2132
2133 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2134 {
2135         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2136
2137         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2138         return 0;
2139 }
2140
2141 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2142 {
2143         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2144         int change;
2145         int val;
2146
2147         if (!snd_hdsp_use_is_exclusive(hdsp))
2148                 return -EBUSY;
2149         val = ucontrol->value.enumerated.item[0];
2150         if (val < 0) val = 0;
2151         if (val > 2) val = 2;
2152         spin_lock_irq(&hdsp->lock);
2153         if (val != hdsp_da_gain(hdsp))
2154                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2155         else
2156                 change = 0;
2157         spin_unlock_irq(&hdsp->lock);
2158         return change;
2159 }
2160
2161 #define HDSP_AD_GAIN(xname, xindex) \
2162 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2163   .name = xname, \
2164   .index = xindex, \
2165   .info = snd_hdsp_info_ad_gain, \
2166   .get = snd_hdsp_get_ad_gain, \
2167   .put = snd_hdsp_put_ad_gain \
2168 }
2169
2170 static int hdsp_ad_gain(struct hdsp *hdsp)
2171 {
2172         switch (hdsp->control_register & HDSP_ADGainMask) {
2173         case HDSP_ADGainMinus10dBV:
2174                 return 0;
2175         case HDSP_ADGainPlus4dBu:
2176                 return 1;
2177         case HDSP_ADGainLowGain:
2178                 return 2;
2179         default:
2180                 return 1;
2181         }
2182 }
2183
2184 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2185 {
2186         hdsp->control_register &= ~HDSP_ADGainMask;
2187         switch (mode) {
2188         case 0:
2189                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2190                 break;
2191         case 1:
2192                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2193                 break;
2194         case 2:
2195                 hdsp->control_register |= HDSP_ADGainLowGain;
2196                 break;
2197         default:
2198                 return -1;
2199
2200         }
2201         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2202         return 0;
2203 }
2204
2205 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2206 {
2207         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2208
2209         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2210 }
2211
2212 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2213 {
2214         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2215
2216         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2217         return 0;
2218 }
2219
2220 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2221 {
2222         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2223         int change;
2224         int val;
2225
2226         if (!snd_hdsp_use_is_exclusive(hdsp))
2227                 return -EBUSY;
2228         val = ucontrol->value.enumerated.item[0];
2229         if (val < 0) val = 0;
2230         if (val > 2) val = 2;
2231         spin_lock_irq(&hdsp->lock);
2232         if (val != hdsp_ad_gain(hdsp))
2233                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2234         else
2235                 change = 0;
2236         spin_unlock_irq(&hdsp->lock);
2237         return change;
2238 }
2239
2240 #define HDSP_PHONE_GAIN(xname, xindex) \
2241 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2242   .name = xname, \
2243   .index = xindex, \
2244   .info = snd_hdsp_info_phone_gain, \
2245   .get = snd_hdsp_get_phone_gain, \
2246   .put = snd_hdsp_put_phone_gain \
2247 }
2248
2249 static int hdsp_phone_gain(struct hdsp *hdsp)
2250 {
2251         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2252         case HDSP_PhoneGain0dB:
2253                 return 0;
2254         case HDSP_PhoneGainMinus6dB:
2255                 return 1;
2256         case HDSP_PhoneGainMinus12dB:
2257                 return 2;
2258         default:
2259                 return 0;
2260         }
2261 }
2262
2263 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2264 {
2265         hdsp->control_register &= ~HDSP_PhoneGainMask;
2266         switch (mode) {
2267         case 0:
2268                 hdsp->control_register |= HDSP_PhoneGain0dB;
2269                 break;
2270         case 1:
2271                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2272                 break;
2273         case 2:
2274                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2275                 break;
2276         default:
2277                 return -1;
2278
2279         }
2280         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2281         return 0;
2282 }
2283
2284 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2285 {
2286         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2287
2288         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2289 }
2290
2291 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2292 {
2293         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2294
2295         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2296         return 0;
2297 }
2298
2299 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2300 {
2301         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2302         int change;
2303         int val;
2304
2305         if (!snd_hdsp_use_is_exclusive(hdsp))
2306                 return -EBUSY;
2307         val = ucontrol->value.enumerated.item[0];
2308         if (val < 0) val = 0;
2309         if (val > 2) val = 2;
2310         spin_lock_irq(&hdsp->lock);
2311         if (val != hdsp_phone_gain(hdsp))
2312                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2313         else
2314                 change = 0;
2315         spin_unlock_irq(&hdsp->lock);
2316         return change;
2317 }
2318
2319 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2320 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2321   .name = xname, \
2322   .index = xindex, \
2323   .info = snd_hdsp_info_pref_sync_ref, \
2324   .get = snd_hdsp_get_pref_sync_ref, \
2325   .put = snd_hdsp_put_pref_sync_ref \
2326 }
2327
2328 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2329 {
2330         /* Notice that this looks at the requested sync source,
2331            not the one actually in use.
2332         */
2333
2334         switch (hdsp->control_register & HDSP_SyncRefMask) {
2335         case HDSP_SyncRef_ADAT1:
2336                 return HDSP_SYNC_FROM_ADAT1;
2337         case HDSP_SyncRef_ADAT2:
2338                 return HDSP_SYNC_FROM_ADAT2;
2339         case HDSP_SyncRef_ADAT3:
2340                 return HDSP_SYNC_FROM_ADAT3;
2341         case HDSP_SyncRef_SPDIF:
2342                 return HDSP_SYNC_FROM_SPDIF;
2343         case HDSP_SyncRef_WORD:
2344                 return HDSP_SYNC_FROM_WORD;
2345         case HDSP_SyncRef_ADAT_SYNC:
2346                 return HDSP_SYNC_FROM_ADAT_SYNC;
2347         default:
2348                 return HDSP_SYNC_FROM_WORD;
2349         }
2350         return 0;
2351 }
2352
2353 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2354 {
2355         hdsp->control_register &= ~HDSP_SyncRefMask;
2356         switch (pref) {
2357         case HDSP_SYNC_FROM_ADAT1:
2358                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2359                 break;
2360         case HDSP_SYNC_FROM_ADAT2:
2361                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2362                 break;
2363         case HDSP_SYNC_FROM_ADAT3:
2364                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2365                 break;
2366         case HDSP_SYNC_FROM_SPDIF:
2367                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2368                 break;
2369         case HDSP_SYNC_FROM_WORD:
2370                 hdsp->control_register |= HDSP_SyncRef_WORD;
2371                 break;
2372         case HDSP_SYNC_FROM_ADAT_SYNC:
2373                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2374                 break;
2375         default:
2376                 return -1;
2377         }
2378         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2379         return 0;
2380 }
2381
2382 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2383 {
2384         static const char * const texts[] = {
2385                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2386         };
2387         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2388         int num_items;
2389
2390         switch (hdsp->io_type) {
2391         case Digiface:
2392         case H9652:
2393                 num_items = 6;
2394                 break;
2395         case Multiface:
2396                 num_items = 4;
2397                 break;
2398         case H9632:
2399                 num_items = 3;
2400                 break;
2401         default:
2402                 return -EINVAL;
2403         }
2404
2405         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2406 }
2407
2408 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2409 {
2410         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2411
2412         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2413         return 0;
2414 }
2415
2416 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2417 {
2418         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2419         int change, max;
2420         unsigned int val;
2421
2422         if (!snd_hdsp_use_is_exclusive(hdsp))
2423                 return -EBUSY;
2424
2425         switch (hdsp->io_type) {
2426         case Digiface:
2427         case H9652:
2428                 max = 6;
2429                 break;
2430         case Multiface:
2431                 max = 4;
2432                 break;
2433         case H9632:
2434                 max = 3;
2435                 break;
2436         default:
2437                 return -EIO;
2438         }
2439
2440         val = ucontrol->value.enumerated.item[0] % max;
2441         spin_lock_irq(&hdsp->lock);
2442         change = (int)val != hdsp_pref_sync_ref(hdsp);
2443         hdsp_set_pref_sync_ref(hdsp, val);
2444         spin_unlock_irq(&hdsp->lock);
2445         return change;
2446 }
2447
2448 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2449 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2450   .name = xname, \
2451   .index = xindex, \
2452   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2453   .info = snd_hdsp_info_autosync_ref, \
2454   .get = snd_hdsp_get_autosync_ref, \
2455 }
2456
2457 static int hdsp_autosync_ref(struct hdsp *hdsp)
2458 {
2459         /* This looks at the autosync selected sync reference */
2460         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2461
2462         switch (status2 & HDSP_SelSyncRefMask) {
2463         case HDSP_SelSyncRef_WORD:
2464                 return HDSP_AUTOSYNC_FROM_WORD;
2465         case HDSP_SelSyncRef_ADAT_SYNC:
2466                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2467         case HDSP_SelSyncRef_SPDIF:
2468                 return HDSP_AUTOSYNC_FROM_SPDIF;
2469         case HDSP_SelSyncRefMask:
2470                 return HDSP_AUTOSYNC_FROM_NONE;
2471         case HDSP_SelSyncRef_ADAT1:
2472                 return HDSP_AUTOSYNC_FROM_ADAT1;
2473         case HDSP_SelSyncRef_ADAT2:
2474                 return HDSP_AUTOSYNC_FROM_ADAT2;
2475         case HDSP_SelSyncRef_ADAT3:
2476                 return HDSP_AUTOSYNC_FROM_ADAT3;
2477         default:
2478                 return HDSP_AUTOSYNC_FROM_WORD;
2479         }
2480         return 0;
2481 }
2482
2483 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2484 {
2485         static const char * const texts[] = {
2486                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2487         };
2488
2489         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2490 }
2491
2492 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2493 {
2494         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2495
2496         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2497         return 0;
2498 }
2499
2500 #define HDSP_PRECISE_POINTER(xname, xindex) \
2501 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2502   .name = xname, \
2503   .index = xindex, \
2504   .info = snd_hdsp_info_precise_pointer, \
2505   .get = snd_hdsp_get_precise_pointer, \
2506   .put = snd_hdsp_put_precise_pointer \
2507 }
2508
2509 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2510 {
2511         if (precise)
2512                 hdsp->precise_ptr = 1;
2513         else
2514                 hdsp->precise_ptr = 0;
2515         return 0;
2516 }
2517
2518 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2519
2520 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2521 {
2522         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2523
2524         spin_lock_irq(&hdsp->lock);
2525         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2526         spin_unlock_irq(&hdsp->lock);
2527         return 0;
2528 }
2529
2530 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2531 {
2532         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2533         int change;
2534         unsigned int val;
2535
2536         if (!snd_hdsp_use_is_exclusive(hdsp))
2537                 return -EBUSY;
2538         val = ucontrol->value.integer.value[0] & 1;
2539         spin_lock_irq(&hdsp->lock);
2540         change = (int)val != hdsp->precise_ptr;
2541         hdsp_set_precise_pointer(hdsp, val);
2542         spin_unlock_irq(&hdsp->lock);
2543         return change;
2544 }
2545
2546 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2547 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2548   .name = xname, \
2549   .index = xindex, \
2550   .info = snd_hdsp_info_use_midi_tasklet, \
2551   .get = snd_hdsp_get_use_midi_tasklet, \
2552   .put = snd_hdsp_put_use_midi_tasklet \
2553 }
2554
2555 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2556 {
2557         if (use_tasklet)
2558                 hdsp->use_midi_tasklet = 1;
2559         else
2560                 hdsp->use_midi_tasklet = 0;
2561         return 0;
2562 }
2563
2564 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2565
2566 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2567 {
2568         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2569
2570         spin_lock_irq(&hdsp->lock);
2571         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2572         spin_unlock_irq(&hdsp->lock);
2573         return 0;
2574 }
2575
2576 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2577 {
2578         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2579         int change;
2580         unsigned int val;
2581
2582         if (!snd_hdsp_use_is_exclusive(hdsp))
2583                 return -EBUSY;
2584         val = ucontrol->value.integer.value[0] & 1;
2585         spin_lock_irq(&hdsp->lock);
2586         change = (int)val != hdsp->use_midi_tasklet;
2587         hdsp_set_use_midi_tasklet(hdsp, val);
2588         spin_unlock_irq(&hdsp->lock);
2589         return change;
2590 }
2591
2592 #define HDSP_MIXER(xname, xindex) \
2593 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2594   .name = xname, \
2595   .index = xindex, \
2596   .device = 0, \
2597   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2598                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2599   .info = snd_hdsp_info_mixer, \
2600   .get = snd_hdsp_get_mixer, \
2601   .put = snd_hdsp_put_mixer \
2602 }
2603
2604 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2605 {
2606         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2607         uinfo->count = 3;
2608         uinfo->value.integer.min = 0;
2609         uinfo->value.integer.max = 65536;
2610         uinfo->value.integer.step = 1;
2611         return 0;
2612 }
2613
2614 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2615 {
2616         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2617         int source;
2618         int destination;
2619         int addr;
2620
2621         source = ucontrol->value.integer.value[0];
2622         destination = ucontrol->value.integer.value[1];
2623
2624         if (source >= hdsp->max_channels)
2625                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2626         else
2627                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2628
2629         spin_lock_irq(&hdsp->lock);
2630         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2631         spin_unlock_irq(&hdsp->lock);
2632         return 0;
2633 }
2634
2635 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2636 {
2637         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2638         int change;
2639         int source;
2640         int destination;
2641         int gain;
2642         int addr;
2643
2644         if (!snd_hdsp_use_is_exclusive(hdsp))
2645                 return -EBUSY;
2646
2647         source = ucontrol->value.integer.value[0];
2648         destination = ucontrol->value.integer.value[1];
2649
2650         if (source >= hdsp->max_channels)
2651                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2652         else
2653                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2654
2655         gain = ucontrol->value.integer.value[2];
2656
2657         spin_lock_irq(&hdsp->lock);
2658         change = gain != hdsp_read_gain(hdsp, addr);
2659         if (change)
2660                 hdsp_write_gain(hdsp, addr, gain);
2661         spin_unlock_irq(&hdsp->lock);
2662         return change;
2663 }
2664
2665 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2666 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2667   .name = xname, \
2668   .index = xindex, \
2669   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2670   .info = snd_hdsp_info_sync_check, \
2671   .get = snd_hdsp_get_wc_sync_check \
2672 }
2673
2674 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2675 {
2676         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2677
2678         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2679 }
2680
2681 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2682 {
2683         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2684         if (status2 & HDSP_wc_lock) {
2685                 if (status2 & HDSP_wc_sync)
2686                         return 2;
2687                 else
2688                          return 1;
2689         } else
2690                 return 0;
2691         return 0;
2692 }
2693
2694 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2695 {
2696         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2697
2698         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2699         return 0;
2700 }
2701
2702 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2703 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2704   .name = xname, \
2705   .index = xindex, \
2706   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2707   .info = snd_hdsp_info_sync_check, \
2708   .get = snd_hdsp_get_spdif_sync_check \
2709 }
2710
2711 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2712 {
2713         int status = hdsp_read(hdsp, HDSP_statusRegister);
2714         if (status & HDSP_SPDIFErrorFlag)
2715                 return 0;
2716         else {
2717                 if (status & HDSP_SPDIFSync)
2718                         return 2;
2719                 else
2720                         return 1;
2721         }
2722         return 0;
2723 }
2724
2725 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2726 {
2727         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2728
2729         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2730         return 0;
2731 }
2732
2733 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2734 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2735   .name = xname, \
2736   .index = xindex, \
2737   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2738   .info = snd_hdsp_info_sync_check, \
2739   .get = snd_hdsp_get_adatsync_sync_check \
2740 }
2741
2742 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2743 {
2744         int status = hdsp_read(hdsp, HDSP_statusRegister);
2745         if (status & HDSP_TimecodeLock) {
2746                 if (status & HDSP_TimecodeSync)
2747                         return 2;
2748                 else
2749                         return 1;
2750         } else
2751                 return 0;
2752 }
2753
2754 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2755 {
2756         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2757
2758         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2759         return 0;
2760 }
2761
2762 #define HDSP_ADAT_SYNC_CHECK \
2763 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2764   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2765   .info = snd_hdsp_info_sync_check, \
2766   .get = snd_hdsp_get_adat_sync_check \
2767 }
2768
2769 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2770 {
2771         int status = hdsp_read(hdsp, HDSP_statusRegister);
2772
2773         if (status & (HDSP_Lock0>>idx)) {
2774                 if (status & (HDSP_Sync0>>idx))
2775                         return 2;
2776                 else
2777                         return 1;
2778         } else
2779                 return 0;
2780 }
2781
2782 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2783 {
2784         int offset;
2785         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2786
2787         offset = ucontrol->id.index - 1;
2788         if (snd_BUG_ON(offset < 0))
2789                 return -EINVAL;
2790
2791         switch (hdsp->io_type) {
2792         case Digiface:
2793         case H9652:
2794                 if (offset >= 3)
2795                         return -EINVAL;
2796                 break;
2797         case Multiface:
2798         case H9632:
2799                 if (offset >= 1)
2800                         return -EINVAL;
2801                 break;
2802         default:
2803                 return -EIO;
2804         }
2805
2806         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2807         return 0;
2808 }
2809
2810 #define HDSP_DDS_OFFSET(xname, xindex) \
2811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2812   .name = xname, \
2813   .index = xindex, \
2814   .info = snd_hdsp_info_dds_offset, \
2815   .get = snd_hdsp_get_dds_offset, \
2816   .put = snd_hdsp_put_dds_offset \
2817 }
2818
2819 static int hdsp_dds_offset(struct hdsp *hdsp)
2820 {
2821         u64 n;
2822         unsigned int dds_value = hdsp->dds_value;
2823         int system_sample_rate = hdsp->system_sample_rate;
2824
2825         if (!dds_value)
2826                 return 0;
2827
2828         n = DDS_NUMERATOR;
2829         /*
2830          * dds_value = n / rate
2831          * rate = n / dds_value
2832          */
2833         n = div_u64(n, dds_value);
2834         if (system_sample_rate >= 112000)
2835                 n *= 4;
2836         else if (system_sample_rate >= 56000)
2837                 n *= 2;
2838         return ((int)n) - system_sample_rate;
2839 }
2840
2841 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2842 {
2843         int rate = hdsp->system_sample_rate + offset_hz;
2844         hdsp_set_dds_value(hdsp, rate);
2845         return 0;
2846 }
2847
2848 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2849 {
2850         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2851         uinfo->count = 1;
2852         uinfo->value.integer.min = -5000;
2853         uinfo->value.integer.max = 5000;
2854         return 0;
2855 }
2856
2857 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2858 {
2859         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2860
2861         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2862         return 0;
2863 }
2864
2865 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2866 {
2867         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2868         int change;
2869         int val;
2870
2871         if (!snd_hdsp_use_is_exclusive(hdsp))
2872                 return -EBUSY;
2873         val = ucontrol->value.integer.value[0];
2874         spin_lock_irq(&hdsp->lock);
2875         if (val != hdsp_dds_offset(hdsp))
2876                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2877         else
2878                 change = 0;
2879         spin_unlock_irq(&hdsp->lock);
2880         return change;
2881 }
2882
2883 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2884 HDSP_DA_GAIN("DA Gain", 0),
2885 HDSP_AD_GAIN("AD Gain", 0),
2886 HDSP_PHONE_GAIN("Phones Gain", 0),
2887 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2888 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2889 };
2890
2891 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2892 {
2893         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2894         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2895         .info =         snd_hdsp_control_spdif_info,
2896         .get =          snd_hdsp_control_spdif_get,
2897         .put =          snd_hdsp_control_spdif_put,
2898 },
2899 {
2900         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2901         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2902         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2903         .info =         snd_hdsp_control_spdif_stream_info,
2904         .get =          snd_hdsp_control_spdif_stream_get,
2905         .put =          snd_hdsp_control_spdif_stream_put,
2906 },
2907 {
2908         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2909         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2910         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2911         .info =         snd_hdsp_control_spdif_mask_info,
2912         .get =          snd_hdsp_control_spdif_mask_get,
2913         .private_value = IEC958_AES0_NONAUDIO |
2914                          IEC958_AES0_PROFESSIONAL |
2915                          IEC958_AES0_CON_EMPHASIS,
2916 },
2917 {
2918         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2919         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2920         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2921         .info =         snd_hdsp_control_spdif_mask_info,
2922         .get =          snd_hdsp_control_spdif_mask_get,
2923         .private_value = IEC958_AES0_NONAUDIO |
2924                          IEC958_AES0_PROFESSIONAL |
2925                          IEC958_AES0_PRO_EMPHASIS,
2926 },
2927 HDSP_MIXER("Mixer", 0),
2928 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2929 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2930 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2931 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2932 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2933 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2934 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2935 {
2936         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2937         .name = "Sample Clock Source Locking",
2938         .info = snd_hdsp_info_clock_source_lock,
2939         .get = snd_hdsp_get_clock_source_lock,
2940         .put = snd_hdsp_put_clock_source_lock,
2941 },
2942 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2943 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2944 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2945 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2946 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2947 /* 'External Rate' complies with the alsa control naming scheme */
2948 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2949 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2950 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2951 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2952 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2953 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2954 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2955 };
2956
2957
2958 static int hdsp_rpm_input12(struct hdsp *hdsp)
2959 {
2960         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2961         case HDSP_RPM_Inp12_Phon_6dB:
2962                 return 0;
2963         case HDSP_RPM_Inp12_Phon_n6dB:
2964                 return 2;
2965         case HDSP_RPM_Inp12_Line_0dB:
2966                 return 3;
2967         case HDSP_RPM_Inp12_Line_n6dB:
2968                 return 4;
2969         }
2970         return 1;
2971 }
2972
2973
2974 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2975 {
2976         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2977
2978         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2979         return 0;
2980 }
2981
2982
2983 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2984 {
2985         hdsp->control_register &= ~HDSP_RPM_Inp12;
2986         switch (mode) {
2987         case 0:
2988                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2989                 break;
2990         case 1:
2991                 break;
2992         case 2:
2993                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2994                 break;
2995         case 3:
2996                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2997                 break;
2998         case 4:
2999                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3000                 break;
3001         default:
3002                 return -1;
3003         }
3004
3005         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3006         return 0;
3007 }
3008
3009
3010 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3011 {
3012         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3013         int change;
3014         int val;
3015
3016         if (!snd_hdsp_use_is_exclusive(hdsp))
3017                 return -EBUSY;
3018         val = ucontrol->value.enumerated.item[0];
3019         if (val < 0)
3020                 val = 0;
3021         if (val > 4)
3022                 val = 4;
3023         spin_lock_irq(&hdsp->lock);
3024         if (val != hdsp_rpm_input12(hdsp))
3025                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3026         else
3027                 change = 0;
3028         spin_unlock_irq(&hdsp->lock);
3029         return change;
3030 }
3031
3032
3033 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3034 {
3035         static const char * const texts[] = {
3036                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3037         };
3038
3039         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3040 }
3041
3042
3043 static int hdsp_rpm_input34(struct hdsp *hdsp)
3044 {
3045         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3046         case HDSP_RPM_Inp34_Phon_6dB:
3047                 return 0;
3048         case HDSP_RPM_Inp34_Phon_n6dB:
3049                 return 2;
3050         case HDSP_RPM_Inp34_Line_0dB:
3051                 return 3;
3052         case HDSP_RPM_Inp34_Line_n6dB:
3053                 return 4;
3054         }
3055         return 1;
3056 }
3057
3058
3059 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3060 {
3061         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3062
3063         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3064         return 0;
3065 }
3066
3067
3068 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3069 {
3070         hdsp->control_register &= ~HDSP_RPM_Inp34;
3071         switch (mode) {
3072         case 0:
3073                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3074                 break;
3075         case 1:
3076                 break;
3077         case 2:
3078                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3079                 break;
3080         case 3:
3081                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3082                 break;
3083         case 4:
3084                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3085                 break;
3086         default:
3087                 return -1;
3088         }
3089
3090         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3091         return 0;
3092 }
3093
3094
3095 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3096 {
3097         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3098         int change;
3099         int val;
3100
3101         if (!snd_hdsp_use_is_exclusive(hdsp))
3102                 return -EBUSY;
3103         val = ucontrol->value.enumerated.item[0];
3104         if (val < 0)
3105                 val = 0;
3106         if (val > 4)
3107                 val = 4;
3108         spin_lock_irq(&hdsp->lock);
3109         if (val != hdsp_rpm_input34(hdsp))
3110                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3111         else
3112                 change = 0;
3113         spin_unlock_irq(&hdsp->lock);
3114         return change;
3115 }
3116
3117
3118 /* RPM Bypass switch */
3119 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3120 {
3121         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3122 }
3123
3124
3125 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3126 {
3127         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3128
3129         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3130         return 0;
3131 }
3132
3133
3134 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3135 {
3136         if (on)
3137                 hdsp->control_register |= HDSP_RPM_Bypass;
3138         else
3139                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3140         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3141         return 0;
3142 }
3143
3144
3145 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3146 {
3147         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3148         int change;
3149         unsigned int val;
3150
3151         if (!snd_hdsp_use_is_exclusive(hdsp))
3152                 return -EBUSY;
3153         val = ucontrol->value.integer.value[0] & 1;
3154         spin_lock_irq(&hdsp->lock);
3155         change = (int)val != hdsp_rpm_bypass(hdsp);
3156         hdsp_set_rpm_bypass(hdsp, val);
3157         spin_unlock_irq(&hdsp->lock);
3158         return change;
3159 }
3160
3161
3162 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3163 {
3164         static const char * const texts[] = {"On", "Off"};
3165
3166         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3167 }
3168
3169
3170 /* RPM Disconnect switch */
3171 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3172 {
3173         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3174 }
3175
3176
3177 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3178 {
3179         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3180
3181         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3182         return 0;
3183 }
3184
3185
3186 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3187 {
3188         if (on)
3189                 hdsp->control_register |= HDSP_RPM_Disconnect;
3190         else
3191                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3192         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3193         return 0;
3194 }
3195
3196
3197 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3198 {
3199         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3200         int change;
3201         unsigned int val;
3202
3203         if (!snd_hdsp_use_is_exclusive(hdsp))
3204                 return -EBUSY;
3205         val = ucontrol->value.integer.value[0] & 1;
3206         spin_lock_irq(&hdsp->lock);
3207         change = (int)val != hdsp_rpm_disconnect(hdsp);
3208         hdsp_set_rpm_disconnect(hdsp, val);
3209         spin_unlock_irq(&hdsp->lock);
3210         return change;
3211 }
3212
3213 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3214 {
3215         static const char * const texts[] = {"On", "Off"};
3216
3217         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3218 }
3219
3220 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3221         {
3222                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3223                 .name = "RPM Bypass",
3224                 .get = snd_hdsp_get_rpm_bypass,
3225                 .put = snd_hdsp_put_rpm_bypass,
3226                 .info = snd_hdsp_info_rpm_bypass
3227         },
3228         {
3229                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3230                 .name = "RPM Disconnect",
3231                 .get = snd_hdsp_get_rpm_disconnect,
3232                 .put = snd_hdsp_put_rpm_disconnect,
3233                 .info = snd_hdsp_info_rpm_disconnect
3234         },
3235         {
3236                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3237                 .name = "Input 1/2",
3238                 .get = snd_hdsp_get_rpm_input12,
3239                 .put = snd_hdsp_put_rpm_input12,
3240                 .info = snd_hdsp_info_rpm_input
3241         },
3242         {
3243                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3244                 .name = "Input 3/4",
3245                 .get = snd_hdsp_get_rpm_input34,
3246                 .put = snd_hdsp_put_rpm_input34,
3247                 .info = snd_hdsp_info_rpm_input
3248         },
3249         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3250         HDSP_MIXER("Mixer", 0)
3251 };
3252
3253 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3254         HDSP_TOGGLE_SETTING("Analog Extension Board",
3255                         HDSP_AnalogExtensionBoard);
3256 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3257
3258 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3259 {
3260         unsigned int idx;
3261         int err;
3262         struct snd_kcontrol *kctl;
3263
3264         if (hdsp->io_type == RPM) {
3265                 /* RPM Bypass, Disconnect and Input switches */
3266                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3267                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3268                         if (err < 0)
3269                                 return err;
3270                 }
3271                 return 0;
3272         }
3273
3274         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3275                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3276                         return err;
3277                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3278                         hdsp->spdif_ctl = kctl;
3279         }
3280
3281         /* ADAT SyncCheck status */
3282         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3283         snd_hdsp_adat_sync_check.index = 1;
3284         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3285                 return err;
3286         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3287                 for (idx = 1; idx < 3; ++idx) {
3288                         snd_hdsp_adat_sync_check.index = idx+1;
3289                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3290                                 return err;
3291                 }
3292         }
3293
3294         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3295         if (hdsp->io_type == H9632) {
3296                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3297                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3298                                 return err;
3299                 }
3300         }
3301
3302         /* AEB control for H96xx card */
3303         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3304                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3305                                 return err;
3306         }
3307
3308         return 0;
3309 }
3310
3311 /*------------------------------------------------------------
3312    /proc interface
3313  ------------------------------------------------------------*/
3314
3315 static void
3316 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3317 {
3318         struct hdsp *hdsp = entry->private_data;
3319         unsigned int status;
3320         unsigned int status2;
3321         char *pref_sync_ref;
3322         char *autosync_ref;
3323         char *system_clock_mode;
3324         char *clock_source;
3325         int x;
3326
3327         status = hdsp_read(hdsp, HDSP_statusRegister);
3328         status2 = hdsp_read(hdsp, HDSP_status2Register);
3329
3330         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3331                     hdsp->card->number + 1);
3332         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3333                     hdsp->capture_buffer, hdsp->playback_buffer);
3334         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3335                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3336         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3337         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3338                     hdsp->control2_register);
3339         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3340         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3341
3342         if (hdsp_check_for_iobox(hdsp)) {
3343                 snd_iprintf(buffer, "No I/O box connected.\n"
3344                             "Please connect one and upload firmware.\n");
3345                 return;
3346         }
3347
3348         if (hdsp_check_for_firmware(hdsp, 0)) {
3349                 if (hdsp->state & HDSP_FirmwareCached) {
3350                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3351                                 snd_iprintf(buffer, "Firmware loading from "
3352                                             "cache failed, "
3353                                             "please upload manually.\n");
3354                                 return;
3355                         }
3356                 } else {
3357                         int err = -EINVAL;
3358                         err = hdsp_request_fw_loader(hdsp);
3359                         if (err < 0) {
3360                                 snd_iprintf(buffer,
3361                                             "No firmware loaded nor cached, "
3362                                             "please upload firmware.\n");
3363                                 return;
3364                         }
3365                 }
3366         }
3367
3368         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3369         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3370         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3371         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3372         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3373         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3374
3375         snd_iprintf(buffer, "\n");
3376
3377         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3378
3379         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3380         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3381         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3382         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3383
3384         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3385
3386         snd_iprintf(buffer, "\n");
3387
3388         switch (hdsp_clock_source(hdsp)) {
3389         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3390                 clock_source = "AutoSync";
3391                 break;
3392         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3393                 clock_source = "Internal 32 kHz";
3394                 break;
3395         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3396                 clock_source = "Internal 44.1 kHz";
3397                 break;
3398         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3399                 clock_source = "Internal 48 kHz";
3400                 break;
3401         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3402                 clock_source = "Internal 64 kHz";
3403                 break;
3404         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3405                 clock_source = "Internal 88.2 kHz";
3406                 break;
3407         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3408                 clock_source = "Internal 96 kHz";
3409                 break;
3410         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3411                 clock_source = "Internal 128 kHz";
3412                 break;
3413         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3414                 clock_source = "Internal 176.4 kHz";
3415                 break;
3416                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3417                 clock_source = "Internal 192 kHz";
3418                 break;
3419         default:
3420                 clock_source = "Error";
3421         }
3422         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3423
3424         if (hdsp_system_clock_mode(hdsp))
3425                 system_clock_mode = "Slave";
3426         else
3427                 system_clock_mode = "Master";
3428
3429         switch (hdsp_pref_sync_ref (hdsp)) {
3430         case HDSP_SYNC_FROM_WORD:
3431                 pref_sync_ref = "Word Clock";
3432                 break;
3433         case HDSP_SYNC_FROM_ADAT_SYNC:
3434                 pref_sync_ref = "ADAT Sync";
3435                 break;
3436         case HDSP_SYNC_FROM_SPDIF:
3437                 pref_sync_ref = "SPDIF";
3438                 break;
3439         case HDSP_SYNC_FROM_ADAT1:
3440                 pref_sync_ref = "ADAT1";
3441                 break;
3442         case HDSP_SYNC_FROM_ADAT2:
3443                 pref_sync_ref = "ADAT2";
3444                 break;
3445         case HDSP_SYNC_FROM_ADAT3:
3446                 pref_sync_ref = "ADAT3";
3447                 break;
3448         default:
3449                 pref_sync_ref = "Word Clock";
3450                 break;
3451         }
3452         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3453
3454         switch (hdsp_autosync_ref (hdsp)) {
3455         case HDSP_AUTOSYNC_FROM_WORD:
3456                 autosync_ref = "Word Clock";
3457                 break;
3458         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3459                 autosync_ref = "ADAT Sync";
3460                 break;
3461         case HDSP_AUTOSYNC_FROM_SPDIF:
3462                 autosync_ref = "SPDIF";
3463                 break;
3464         case HDSP_AUTOSYNC_FROM_NONE:
3465                 autosync_ref = "None";
3466                 break;
3467         case HDSP_AUTOSYNC_FROM_ADAT1:
3468                 autosync_ref = "ADAT1";
3469                 break;
3470         case HDSP_AUTOSYNC_FROM_ADAT2:
3471                 autosync_ref = "ADAT2";
3472                 break;
3473         case HDSP_AUTOSYNC_FROM_ADAT3:
3474                 autosync_ref = "ADAT3";
3475                 break;
3476         default:
3477                 autosync_ref = "---";
3478                 break;
3479         }
3480         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3481
3482         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3483
3484         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3485
3486         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3487         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3488
3489         snd_iprintf(buffer, "\n");
3490
3491         if (hdsp->io_type != RPM) {
3492                 switch (hdsp_spdif_in(hdsp)) {
3493                 case HDSP_SPDIFIN_OPTICAL:
3494                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3495                         break;
3496                 case HDSP_SPDIFIN_COAXIAL:
3497                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3498                         break;
3499                 case HDSP_SPDIFIN_INTERNAL:
3500                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3501                         break;
3502                 case HDSP_SPDIFIN_AES:
3503                         snd_iprintf(buffer, "IEC958 input: AES\n");
3504                         break;
3505                 default:
3506                         snd_iprintf(buffer, "IEC958 input: ???\n");
3507                         break;
3508                 }
3509         }
3510
3511         if (RPM == hdsp->io_type) {
3512                 if (hdsp->control_register & HDSP_RPM_Bypass)
3513                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3514                 else
3515                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3516                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3517                         snd_iprintf(buffer, "RPM disconnected\n");
3518                 else
3519                         snd_iprintf(buffer, "RPM connected\n");
3520
3521                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3522                 case HDSP_RPM_Inp12_Phon_6dB:
3523                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3524                         break;
3525                 case HDSP_RPM_Inp12_Phon_0dB:
3526                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3527                         break;
3528                 case HDSP_RPM_Inp12_Phon_n6dB:
3529                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3530                         break;
3531                 case HDSP_RPM_Inp12_Line_0dB:
3532                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3533                         break;
3534                 case HDSP_RPM_Inp12_Line_n6dB:
3535                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3536                         break;
3537                 default:
3538                         snd_iprintf(buffer, "Input 1/2: ???\n");
3539                 }
3540
3541                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3542                 case HDSP_RPM_Inp34_Phon_6dB:
3543                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3544                         break;
3545                 case HDSP_RPM_Inp34_Phon_0dB:
3546                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3547                         break;
3548                 case HDSP_RPM_Inp34_Phon_n6dB:
3549                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3550                         break;
3551                 case HDSP_RPM_Inp34_Line_0dB:
3552                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3553                         break;
3554                 case HDSP_RPM_Inp34_Line_n6dB:
3555                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3556                         break;
3557                 default:
3558                         snd_iprintf(buffer, "Input 3/4: ???\n");
3559                 }
3560
3561         } else {
3562                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3563                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3564                 else
3565                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3566
3567                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3568                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3569                 else
3570                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3571
3572                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3573                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3574                 else
3575                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3576
3577                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3578                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3579                 else
3580                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3581                 x = hdsp_spdif_sample_rate(hdsp);
3582                 if (x != 0)
3583                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3584                 else
3585                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3586         }
3587         snd_iprintf(buffer, "\n");
3588
3589         /* Sync Check */
3590         x = status & HDSP_Sync0;
3591         if (status & HDSP_Lock0)
3592                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3593         else
3594                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3595
3596         switch (hdsp->io_type) {
3597         case Digiface:
3598         case H9652:
3599                 x = status & HDSP_Sync1;
3600                 if (status & HDSP_Lock1)
3601                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3602                 else
3603                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3604                 x = status & HDSP_Sync2;
3605                 if (status & HDSP_Lock2)
3606                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3607                 else
3608                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3609                 break;
3610         default:
3611                 /* relax */
3612                 break;
3613         }
3614
3615         x = status & HDSP_SPDIFSync;
3616         if (status & HDSP_SPDIFErrorFlag)
3617                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3618         else
3619                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3620
3621         x = status2 & HDSP_wc_sync;
3622         if (status2 & HDSP_wc_lock)
3623                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3624         else
3625                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3626
3627         x = status & HDSP_TimecodeSync;
3628         if (status & HDSP_TimecodeLock)
3629                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3630         else
3631                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3632
3633         snd_iprintf(buffer, "\n");
3634
3635         /* Informations about H9632 specific controls */
3636         if (hdsp->io_type == H9632) {
3637                 char *tmp;
3638
3639                 switch (hdsp_ad_gain(hdsp)) {
3640                 case 0:
3641                         tmp = "-10 dBV";
3642                         break;
3643                 case 1:
3644                         tmp = "+4 dBu";
3645                         break;
3646                 default:
3647                         tmp = "Lo Gain";
3648                         break;
3649                 }
3650                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3651
3652                 switch (hdsp_da_gain(hdsp)) {
3653                 case 0:
3654                         tmp = "Hi Gain";
3655                         break;
3656                 case 1:
3657                         tmp = "+4 dBu";
3658                         break;
3659                 default:
3660                         tmp = "-10 dBV";
3661                         break;
3662                 }
3663                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3664
3665                 switch (hdsp_phone_gain(hdsp)) {
3666                 case 0:
3667                         tmp = "0 dB";
3668                         break;
3669                 case 1:
3670                         tmp = "-6 dB";
3671                         break;
3672                 default:
3673                         tmp = "-12 dB";
3674                         break;
3675                 }
3676                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3677
3678                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3679                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3680                         "yes" : "no");
3681
3682                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3683                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3684                 else
3685                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3686                 snd_iprintf(buffer, "\n");
3687         }
3688
3689 }
3690
3691 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3692 {
3693         snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3694 }
3695
3696 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3697 {
3698         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3699         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3700 }
3701
3702 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3703 {
3704         unsigned long pb_bus, cb_bus;
3705
3706         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3707             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3708                 if (hdsp->capture_dma_buf.area)
3709                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3710                 dev_err(hdsp->card->dev,
3711                         "%s: no buffers available\n", hdsp->card_name);
3712                 return -ENOMEM;
3713         }
3714
3715         /* Align to bus-space 64K boundary */
3716
3717         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3718         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3719
3720         /* Tell the card where it is */
3721
3722         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3723         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3724
3725         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3726         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3727
3728         return 0;
3729 }
3730
3731 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3732 {
3733         unsigned int i;
3734
3735         /* ASSUMPTION: hdsp->lock is either held, or
3736            there is no need to hold it (e.g. during module
3737            initialization).
3738          */
3739
3740         /* set defaults:
3741
3742            SPDIF Input via Coax
3743            Master clock mode
3744            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3745                             which implies 2 4096 sample, 32Kbyte periods).
3746            Enable line out.
3747          */
3748
3749         hdsp->control_register = HDSP_ClockModeMaster |
3750                                  HDSP_SPDIFInputCoaxial |
3751                                  hdsp_encode_latency(7) |
3752                                  HDSP_LineOut;
3753
3754
3755         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3756
3757 #ifdef SNDRV_BIG_ENDIAN
3758         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3759 #else
3760         hdsp->control2_register = 0;
3761 #endif
3762         if (hdsp->io_type == H9652)
3763                 snd_hdsp_9652_enable_mixer (hdsp);
3764         else
3765                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3766
3767         hdsp_reset_hw_pointer(hdsp);
3768         hdsp_compute_period_size(hdsp);
3769
3770         /* silence everything */
3771
3772         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3773                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3774
3775         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3776                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3777                         return -EIO;
3778         }
3779
3780         /* H9632 specific defaults */
3781         if (hdsp->io_type == H9632) {
3782                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3783                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3784         }
3785
3786         /* set a default rate so that the channel map is set up.
3787          */
3788
3789         hdsp_set_rate(hdsp, 48000, 1);
3790
3791         return 0;
3792 }
3793
3794 static void hdsp_midi_tasklet(unsigned long arg)
3795 {
3796         struct hdsp *hdsp = (struct hdsp *)arg;
3797
3798         if (hdsp->midi[0].pending)
3799                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3800         if (hdsp->midi[1].pending)
3801                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3802 }
3803
3804 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3805 {
3806         struct hdsp *hdsp = (struct hdsp *) dev_id;
3807         unsigned int status;
3808         int audio;
3809         int midi0;
3810         int midi1;
3811         unsigned int midi0status;
3812         unsigned int midi1status;
3813         int schedule = 0;
3814
3815         status = hdsp_read(hdsp, HDSP_statusRegister);
3816
3817         audio = status & HDSP_audioIRQPending;
3818         midi0 = status & HDSP_midi0IRQPending;
3819         midi1 = status & HDSP_midi1IRQPending;
3820
3821         if (!audio && !midi0 && !midi1)
3822                 return IRQ_NONE;
3823
3824         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3825
3826         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3827         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3828
3829         if (!(hdsp->state & HDSP_InitializationComplete))
3830                 return IRQ_HANDLED;
3831
3832         if (audio) {
3833                 if (hdsp->capture_substream)
3834                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3835
3836                 if (hdsp->playback_substream)
3837                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3838         }
3839
3840         if (midi0 && midi0status) {
3841                 if (hdsp->use_midi_tasklet) {
3842                         /* we disable interrupts for this input until processing is done */
3843                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3844                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3845                         hdsp->midi[0].pending = 1;
3846                         schedule = 1;
3847                 } else {
3848                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3849                 }
3850         }
3851         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3852                 if (hdsp->use_midi_tasklet) {
3853                         /* we disable interrupts for this input until processing is done */
3854                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3855                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3856                         hdsp->midi[1].pending = 1;
3857                         schedule = 1;
3858                 } else {
3859                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3860                 }
3861         }
3862         if (hdsp->use_midi_tasklet && schedule)
3863                 tasklet_schedule(&hdsp->midi_tasklet);
3864         return IRQ_HANDLED;
3865 }
3866
3867 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3868 {
3869         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3870         return hdsp_hw_pointer(hdsp);
3871 }
3872
3873 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3874                                              int stream,
3875                                              int channel)
3876
3877 {
3878         int mapped_channel;
3879
3880         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3881                 return NULL;
3882
3883         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3884                 return NULL;
3885
3886         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3887                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3888         else
3889                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3890 }
3891
3892 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3893                                   int channel, unsigned long pos,
3894                                   void __user *src, unsigned long count)
3895 {
3896         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3897         char *channel_buf;
3898
3899         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3900                 return -EINVAL;
3901
3902         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3903         if (snd_BUG_ON(!channel_buf))
3904                 return -EIO;
3905         if (copy_from_user(channel_buf + pos, src, count))
3906                 return -EFAULT;
3907         return 0;
3908 }
3909
3910 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3911                                          int channel, unsigned long pos,
3912                                          void *src, unsigned long count)
3913 {
3914         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3915         char *channel_buf;
3916
3917         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3918         if (snd_BUG_ON(!channel_buf))
3919                 return -EIO;
3920         memcpy(channel_buf + pos, src, count);
3921         return 0;
3922 }
3923
3924 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3925                                  int channel, unsigned long pos,
3926                                  void __user *dst, unsigned long count)
3927 {
3928         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3929         char *channel_buf;
3930
3931         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3932                 return -EINVAL;
3933
3934         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3935         if (snd_BUG_ON(!channel_buf))
3936                 return -EIO;
3937         if (copy_to_user(dst, channel_buf + pos, count))
3938                 return -EFAULT;
3939         return 0;
3940 }
3941
3942 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3943                                         int channel, unsigned long pos,
3944                                         void *dst, unsigned long count)
3945 {
3946         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3947         char *channel_buf;
3948
3949         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3950         if (snd_BUG_ON(!channel_buf))
3951                 return -EIO;
3952         memcpy(dst, channel_buf + pos, count);
3953         return 0;
3954 }
3955
3956 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3957                                int channel, unsigned long pos,
3958                                unsigned long count)
3959 {
3960         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3961         char *channel_buf;
3962
3963         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3964         if (snd_BUG_ON(!channel_buf))
3965                 return -EIO;
3966         memset(channel_buf + pos, 0, count);
3967         return 0;
3968 }
3969
3970 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3971 {
3972         struct snd_pcm_runtime *runtime = substream->runtime;
3973         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3974         struct snd_pcm_substream *other;
3975         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3976                 other = hdsp->capture_substream;
3977         else
3978                 other = hdsp->playback_substream;
3979         if (hdsp->running)
3980                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3981         else
3982                 runtime->status->hw_ptr = 0;
3983         if (other) {
3984                 struct snd_pcm_substream *s;
3985                 struct snd_pcm_runtime *oruntime = other->runtime;
3986                 snd_pcm_group_for_each_entry(s, substream) {
3987                         if (s == other) {
3988                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3989                                 break;
3990                         }
3991                 }
3992         }
3993         return 0;
3994 }
3995
3996 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3997                                  struct snd_pcm_hw_params *params)
3998 {
3999         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4000         int err;
4001         pid_t this_pid;
4002         pid_t other_pid;
4003
4004         if (hdsp_check_for_iobox (hdsp))
4005                 return -EIO;
4006
4007         if (hdsp_check_for_firmware(hdsp, 1))
4008                 return -EIO;
4009
4010         spin_lock_irq(&hdsp->lock);
4011
4012         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4013                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4014                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4015                 this_pid = hdsp->playback_pid;
4016                 other_pid = hdsp->capture_pid;
4017         } else {
4018                 this_pid = hdsp->capture_pid;
4019                 other_pid = hdsp->playback_pid;
4020         }
4021
4022         if ((other_pid > 0) && (this_pid != other_pid)) {
4023
4024                 /* The other stream is open, and not by the same
4025                    task as this one. Make sure that the parameters
4026                    that matter are the same.
4027                  */
4028
4029                 if (params_rate(params) != hdsp->system_sample_rate) {
4030                         spin_unlock_irq(&hdsp->lock);
4031                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4032                         return -EBUSY;
4033                 }
4034
4035                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4036                         spin_unlock_irq(&hdsp->lock);
4037                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4038                         return -EBUSY;
4039                 }
4040
4041                 /* We're fine. */
4042
4043                 spin_unlock_irq(&hdsp->lock);
4044                 return 0;
4045
4046         } else {
4047                 spin_unlock_irq(&hdsp->lock);
4048         }
4049
4050         /* how to make sure that the rate matches an externally-set one ?
4051          */
4052
4053         spin_lock_irq(&hdsp->lock);
4054         if (! hdsp->clock_source_locked) {
4055                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4056                         spin_unlock_irq(&hdsp->lock);
4057                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4058                         return err;
4059                 }
4060         }
4061         spin_unlock_irq(&hdsp->lock);
4062
4063         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4064                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4065                 return err;
4066         }
4067
4068         return 0;
4069 }
4070
4071 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4072                                     struct snd_pcm_channel_info *info)
4073 {
4074         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4075         unsigned int channel = info->channel;
4076
4077         if (snd_BUG_ON(channel >= hdsp->max_channels))
4078                 return -EINVAL;
4079         channel = array_index_nospec(channel, hdsp->max_channels);
4080
4081         if (hdsp->channel_map[channel] < 0)
4082                 return -EINVAL;
4083
4084         info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4085         info->first = 0;
4086         info->step = 32;
4087         return 0;
4088 }
4089
4090 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4091                              unsigned int cmd, void *arg)
4092 {
4093         switch (cmd) {
4094         case SNDRV_PCM_IOCTL1_RESET:
4095                 return snd_hdsp_reset(substream);
4096         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4097                 return snd_hdsp_channel_info(substream, arg);
4098         default:
4099                 break;
4100         }
4101
4102         return snd_pcm_lib_ioctl(substream, cmd, arg);
4103 }
4104
4105 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4106 {
4107         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4108         struct snd_pcm_substream *other;
4109         int running;
4110
4111         if (hdsp_check_for_iobox (hdsp))
4112                 return -EIO;
4113
4114         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4115                 return -EIO;
4116
4117         spin_lock(&hdsp->lock);
4118         running = hdsp->running;
4119         switch (cmd) {
4120         case SNDRV_PCM_TRIGGER_START:
4121                 running |= 1 << substream->stream;
4122                 break;
4123         case SNDRV_PCM_TRIGGER_STOP:
4124                 running &= ~(1 << substream->stream);
4125                 break;
4126         default:
4127                 snd_BUG();
4128                 spin_unlock(&hdsp->lock);
4129                 return -EINVAL;
4130         }
4131         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4132                 other = hdsp->capture_substream;
4133         else
4134                 other = hdsp->playback_substream;
4135
4136         if (other) {
4137                 struct snd_pcm_substream *s;
4138                 snd_pcm_group_for_each_entry(s, substream) {
4139                         if (s == other) {
4140                                 snd_pcm_trigger_done(s, substream);
4141                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4142                                         running |= 1 << s->stream;
4143                                 else
4144                                         running &= ~(1 << s->stream);
4145                                 goto _ok;
4146                         }
4147                 }
4148                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4149                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4150                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4151                                 hdsp_silence_playback(hdsp);
4152                 } else {
4153                         if (running &&
4154                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4155                                 hdsp_silence_playback(hdsp);
4156                 }
4157         } else {
4158                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4159                                 hdsp_silence_playback(hdsp);
4160         }
4161  _ok:
4162         snd_pcm_trigger_done(substream, substream);
4163         if (!hdsp->running && running)
4164                 hdsp_start_audio(hdsp);
4165         else if (hdsp->running && !running)
4166                 hdsp_stop_audio(hdsp);
4167         hdsp->running = running;
4168         spin_unlock(&hdsp->lock);
4169
4170         return 0;
4171 }
4172
4173 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4174 {
4175         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4176         int result = 0;
4177
4178         if (hdsp_check_for_iobox (hdsp))
4179                 return -EIO;
4180
4181         if (hdsp_check_for_firmware(hdsp, 1))
4182                 return -EIO;
4183
4184         spin_lock_irq(&hdsp->lock);
4185         if (!hdsp->running)
4186                 hdsp_reset_hw_pointer(hdsp);
4187         spin_unlock_irq(&hdsp->lock);
4188         return result;
4189 }
4190
4191 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4192 {
4193         .info =                 (SNDRV_PCM_INFO_MMAP |
4194                                  SNDRV_PCM_INFO_MMAP_VALID |
4195                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4196                                  SNDRV_PCM_INFO_SYNC_START |
4197                                  SNDRV_PCM_INFO_DOUBLE),
4198 #ifdef SNDRV_BIG_ENDIAN
4199         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4200 #else
4201         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4202 #endif
4203         .rates =                (SNDRV_PCM_RATE_32000 |
4204                                  SNDRV_PCM_RATE_44100 |
4205                                  SNDRV_PCM_RATE_48000 |
4206                                  SNDRV_PCM_RATE_64000 |
4207                                  SNDRV_PCM_RATE_88200 |
4208                                  SNDRV_PCM_RATE_96000),
4209         .rate_min =             32000,
4210         .rate_max =             96000,
4211         .channels_min =         6,
4212         .channels_max =         HDSP_MAX_CHANNELS,
4213         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4214         .period_bytes_min =     (64 * 4) * 10,
4215         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4216         .periods_min =          2,
4217         .periods_max =          2,
4218         .fifo_size =            0
4219 };
4220
4221 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4222 {
4223         .info =                 (SNDRV_PCM_INFO_MMAP |
4224                                  SNDRV_PCM_INFO_MMAP_VALID |
4225                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4226                                  SNDRV_PCM_INFO_SYNC_START),
4227 #ifdef SNDRV_BIG_ENDIAN
4228         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4229 #else
4230         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4231 #endif
4232         .rates =                (SNDRV_PCM_RATE_32000 |
4233                                  SNDRV_PCM_RATE_44100 |
4234                                  SNDRV_PCM_RATE_48000 |
4235                                  SNDRV_PCM_RATE_64000 |
4236                                  SNDRV_PCM_RATE_88200 |
4237                                  SNDRV_PCM_RATE_96000),
4238         .rate_min =             32000,
4239         .rate_max =             96000,
4240         .channels_min =         5,
4241         .channels_max =         HDSP_MAX_CHANNELS,
4242         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4243         .period_bytes_min =     (64 * 4) * 10,
4244         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4245         .periods_min =          2,
4246         .periods_max =          2,
4247         .fifo_size =            0
4248 };
4249
4250 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4251
4252 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4253         .count = ARRAY_SIZE(hdsp_period_sizes),
4254         .list = hdsp_period_sizes,
4255         .mask = 0
4256 };
4257
4258 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4259
4260 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4261         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4262         .list = hdsp_9632_sample_rates,
4263         .mask = 0
4264 };
4265
4266 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4267                                         struct snd_pcm_hw_rule *rule)
4268 {
4269         struct hdsp *hdsp = rule->private;
4270         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4271         if (hdsp->io_type == H9632) {
4272                 unsigned int list[3];
4273                 list[0] = hdsp->qs_in_channels;
4274                 list[1] = hdsp->ds_in_channels;
4275                 list[2] = hdsp->ss_in_channels;
4276                 return snd_interval_list(c, 3, list, 0);
4277         } else {
4278                 unsigned int list[2];
4279                 list[0] = hdsp->ds_in_channels;
4280                 list[1] = hdsp->ss_in_channels;
4281                 return snd_interval_list(c, 2, list, 0);
4282         }
4283 }
4284
4285 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4286                                         struct snd_pcm_hw_rule *rule)
4287 {
4288         unsigned int list[3];
4289         struct hdsp *hdsp = rule->private;
4290         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4291         if (hdsp->io_type == H9632) {
4292                 list[0] = hdsp->qs_out_channels;
4293                 list[1] = hdsp->ds_out_channels;
4294                 list[2] = hdsp->ss_out_channels;
4295                 return snd_interval_list(c, 3, list, 0);
4296         } else {
4297                 list[0] = hdsp->ds_out_channels;
4298                 list[1] = hdsp->ss_out_channels;
4299         }
4300         return snd_interval_list(c, 2, list, 0);
4301 }
4302
4303 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4304                                              struct snd_pcm_hw_rule *rule)
4305 {
4306         struct hdsp *hdsp = rule->private;
4307         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4309         if (r->min > 96000 && hdsp->io_type == H9632) {
4310                 struct snd_interval t = {
4311                         .min = hdsp->qs_in_channels,
4312                         .max = hdsp->qs_in_channels,
4313                         .integer = 1,
4314                 };
4315                 return snd_interval_refine(c, &t);
4316         } else if (r->min > 48000 && r->max <= 96000) {
4317                 struct snd_interval t = {
4318                         .min = hdsp->ds_in_channels,
4319                         .max = hdsp->ds_in_channels,
4320                         .integer = 1,
4321                 };
4322                 return snd_interval_refine(c, &t);
4323         } else if (r->max < 64000) {
4324                 struct snd_interval t = {
4325                         .min = hdsp->ss_in_channels,
4326                         .max = hdsp->ss_in_channels,
4327                         .integer = 1,
4328                 };
4329                 return snd_interval_refine(c, &t);
4330         }
4331         return 0;
4332 }
4333
4334 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4335                                              struct snd_pcm_hw_rule *rule)
4336 {
4337         struct hdsp *hdsp = rule->private;
4338         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4340         if (r->min > 96000 && hdsp->io_type == H9632) {
4341                 struct snd_interval t = {
4342                         .min = hdsp->qs_out_channels,
4343                         .max = hdsp->qs_out_channels,
4344                         .integer = 1,
4345                 };
4346                 return snd_interval_refine(c, &t);
4347         } else if (r->min > 48000 && r->max <= 96000) {
4348                 struct snd_interval t = {
4349                         .min = hdsp->ds_out_channels,
4350                         .max = hdsp->ds_out_channels,
4351                         .integer = 1,
4352                 };
4353                 return snd_interval_refine(c, &t);
4354         } else if (r->max < 64000) {
4355                 struct snd_interval t = {
4356                         .min = hdsp->ss_out_channels,
4357                         .max = hdsp->ss_out_channels,
4358                         .integer = 1,
4359                 };
4360                 return snd_interval_refine(c, &t);
4361         }
4362         return 0;
4363 }
4364
4365 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4366                                              struct snd_pcm_hw_rule *rule)
4367 {
4368         struct hdsp *hdsp = rule->private;
4369         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4370         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4371         if (c->min >= hdsp->ss_out_channels) {
4372                 struct snd_interval t = {
4373                         .min = 32000,
4374                         .max = 48000,
4375                         .integer = 1,
4376                 };
4377                 return snd_interval_refine(r, &t);
4378         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4379                 struct snd_interval t = {
4380                         .min = 128000,
4381                         .max = 192000,
4382                         .integer = 1,
4383                 };
4384                 return snd_interval_refine(r, &t);
4385         } else if (c->max <= hdsp->ds_out_channels) {
4386                 struct snd_interval t = {
4387                         .min = 64000,
4388                         .max = 96000,
4389                         .integer = 1,
4390                 };
4391                 return snd_interval_refine(r, &t);
4392         }
4393         return 0;
4394 }
4395
4396 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4397                                              struct snd_pcm_hw_rule *rule)
4398 {
4399         struct hdsp *hdsp = rule->private;
4400         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4401         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4402         if (c->min >= hdsp->ss_in_channels) {
4403                 struct snd_interval t = {
4404                         .min = 32000,
4405                         .max = 48000,
4406                         .integer = 1,
4407                 };
4408                 return snd_interval_refine(r, &t);
4409         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4410                 struct snd_interval t = {
4411                         .min = 128000,
4412                         .max = 192000,
4413                         .integer = 1,
4414                 };
4415                 return snd_interval_refine(r, &t);
4416         } else if (c->max <= hdsp->ds_in_channels) {
4417                 struct snd_interval t = {
4418                         .min = 64000,
4419                         .max = 96000,
4420                         .integer = 1,
4421                 };
4422                 return snd_interval_refine(r, &t);
4423         }
4424         return 0;
4425 }
4426
4427 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4428 {
4429         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4430         struct snd_pcm_runtime *runtime = substream->runtime;
4431
4432         if (hdsp_check_for_iobox (hdsp))
4433                 return -EIO;
4434
4435         if (hdsp_check_for_firmware(hdsp, 1))
4436                 return -EIO;
4437
4438         spin_lock_irq(&hdsp->lock);
4439
4440         snd_pcm_set_sync(substream);
4441
4442         runtime->hw = snd_hdsp_playback_subinfo;
4443         runtime->dma_area = hdsp->playback_buffer;
4444         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4445
4446         hdsp->playback_pid = current->pid;
4447         hdsp->playback_substream = substream;
4448
4449         spin_unlock_irq(&hdsp->lock);
4450
4451         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4452         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4453         if (hdsp->clock_source_locked) {
4454                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4455         } else if (hdsp->io_type == H9632) {
4456                 runtime->hw.rate_max = 192000;
4457                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4458                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4459         }
4460         if (hdsp->io_type == H9632) {
4461                 runtime->hw.channels_min = hdsp->qs_out_channels;
4462                 runtime->hw.channels_max = hdsp->ss_out_channels;
4463         }
4464
4465         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4466                              snd_hdsp_hw_rule_out_channels, hdsp,
4467                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4468         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4469                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4470                              SNDRV_PCM_HW_PARAM_RATE, -1);
4471         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4472                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4473                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4474
4475         if (RPM != hdsp->io_type) {
4476                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4477                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4478                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4479                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4480         }
4481         return 0;
4482 }
4483
4484 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4485 {
4486         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4487
4488         spin_lock_irq(&hdsp->lock);
4489
4490         hdsp->playback_pid = -1;
4491         hdsp->playback_substream = NULL;
4492
4493         spin_unlock_irq(&hdsp->lock);
4494
4495         if (RPM != hdsp->io_type) {
4496                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4497                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4498                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4499         }
4500         return 0;
4501 }
4502
4503
4504 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4505 {
4506         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4507         struct snd_pcm_runtime *runtime = substream->runtime;
4508
4509         if (hdsp_check_for_iobox (hdsp))
4510                 return -EIO;
4511
4512         if (hdsp_check_for_firmware(hdsp, 1))
4513                 return -EIO;
4514
4515         spin_lock_irq(&hdsp->lock);
4516
4517         snd_pcm_set_sync(substream);
4518
4519         runtime->hw = snd_hdsp_capture_subinfo;
4520         runtime->dma_area = hdsp->capture_buffer;
4521         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4522
4523         hdsp->capture_pid = current->pid;
4524         hdsp->capture_substream = substream;
4525
4526         spin_unlock_irq(&hdsp->lock);
4527
4528         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4529         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4530         if (hdsp->io_type == H9632) {
4531                 runtime->hw.channels_min = hdsp->qs_in_channels;
4532                 runtime->hw.channels_max = hdsp->ss_in_channels;
4533                 runtime->hw.rate_max = 192000;
4534                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4535                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4536         }
4537         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4538                              snd_hdsp_hw_rule_in_channels, hdsp,
4539                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4540         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4541                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4542                              SNDRV_PCM_HW_PARAM_RATE, -1);
4543         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4544                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4545                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4546         return 0;
4547 }
4548
4549 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4550 {
4551         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4552
4553         spin_lock_irq(&hdsp->lock);
4554
4555         hdsp->capture_pid = -1;
4556         hdsp->capture_substream = NULL;
4557
4558         spin_unlock_irq(&hdsp->lock);
4559         return 0;
4560 }
4561
4562 /* helper functions for copying meter values */
4563 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4564 {
4565         u32 val = readl(src);
4566         return copy_to_user(dest, &val, 4);
4567 }
4568
4569 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4570 {
4571         u32 rms_low, rms_high;
4572         u64 rms;
4573         rms_low = readl(src_low);
4574         rms_high = readl(src_high);
4575         rms = ((u64)rms_high << 32) | rms_low;
4576         return copy_to_user(dest, &rms, 8);
4577 }
4578
4579 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4580 {
4581         u32 rms_low, rms_high;
4582         u64 rms;
4583         rms_low = readl(src_low) & 0xffffff00;
4584         rms_high = readl(src_high) & 0xffffff00;
4585         rms = ((u64)rms_high << 32) | rms_low;
4586         return copy_to_user(dest, &rms, 8);
4587 }
4588
4589 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4590 {
4591         int doublespeed = 0;
4592         int i, j, channels, ofs;
4593
4594         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4595                 doublespeed = 1;
4596         channels = doublespeed ? 14 : 26;
4597         for (i = 0, j = 0; i < 26; ++i) {
4598                 if (doublespeed && (i & 4))
4599                         continue;
4600                 ofs = HDSP_9652_peakBase - j * 4;
4601                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4602                         return -EFAULT;
4603                 ofs -= channels * 4;
4604                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4605                         return -EFAULT;
4606                 ofs -= channels * 4;
4607                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4608                         return -EFAULT;
4609                 ofs = HDSP_9652_rmsBase + j * 8;
4610                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4611                                 hdsp->iobase + ofs + 4))
4612                         return -EFAULT;
4613                 ofs += channels * 8;
4614                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4615                                 hdsp->iobase + ofs + 4))
4616                         return -EFAULT;
4617                 ofs += channels * 8;
4618                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4619                                 hdsp->iobase + ofs + 4))
4620                         return -EFAULT;
4621                 j++;
4622         }
4623         return 0;
4624 }
4625
4626 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4627 {
4628         int i, j;
4629         struct hdsp_9632_meters __iomem *m;
4630         int doublespeed = 0;
4631
4632         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4633                 doublespeed = 1;
4634         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4635         for (i = 0, j = 0; i < 16; ++i, ++j) {
4636                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4637                         return -EFAULT;
4638                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4639                         return -EFAULT;
4640                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4641                         return -EFAULT;
4642                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4643                                 &m->input_rms_high[j]))
4644                         return -EFAULT;
4645                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4646                                 &m->playback_rms_high[j]))
4647                         return -EFAULT;
4648                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4649                                 &m->output_rms_high[j]))
4650                         return -EFAULT;
4651                 if (doublespeed && i == 3) i += 4;
4652         }
4653         return 0;
4654 }
4655
4656 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4657 {
4658         int i;
4659
4660         for (i = 0; i < 26; i++) {
4661                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4662                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4663                         return -EFAULT;
4664                 if (copy_u32_le(&peak_rms->input_peaks[i],
4665                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4666                         return -EFAULT;
4667         }
4668         for (i = 0; i < 28; i++) {
4669                 if (copy_u32_le(&peak_rms->output_peaks[i],
4670                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4671                         return -EFAULT;
4672         }
4673         for (i = 0; i < 26; ++i) {
4674                 if (copy_u64_le(&peak_rms->playback_rms[i],
4675                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4676                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4677                         return -EFAULT;
4678                 if (copy_u64_le(&peak_rms->input_rms[i],
4679                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4680                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4681                         return -EFAULT;
4682         }
4683         return 0;
4684 }
4685
4686 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4687 {
4688         struct hdsp *hdsp = hw->private_data;
4689         void __user *argp = (void __user *)arg;
4690         int err;
4691
4692         switch (cmd) {
4693         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4694                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4695
4696                 err = hdsp_check_for_iobox(hdsp);
4697                 if (err < 0)
4698                         return err;
4699
4700                 err = hdsp_check_for_firmware(hdsp, 1);
4701                 if (err < 0)
4702                         return err;
4703
4704                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4705                         dev_err(hdsp->card->dev,
4706                                 "firmware needs to be uploaded to the card.\n");
4707                         return -EINVAL;
4708                 }
4709
4710                 switch (hdsp->io_type) {
4711                 case H9652:
4712                         return hdsp_9652_get_peak(hdsp, peak_rms);
4713                 case H9632:
4714                         return hdsp_9632_get_peak(hdsp, peak_rms);
4715                 default:
4716                         return hdsp_get_peak(hdsp, peak_rms);
4717                 }
4718         }
4719         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4720                 struct hdsp_config_info info;
4721                 unsigned long flags;
4722                 int i;
4723
4724                 err = hdsp_check_for_iobox(hdsp);
4725                 if (err < 0)
4726                         return err;
4727
4728                 err = hdsp_check_for_firmware(hdsp, 1);
4729                 if (err < 0)
4730                         return err;
4731
4732                 memset(&info, 0, sizeof(info));
4733                 spin_lock_irqsave(&hdsp->lock, flags);
4734                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4735                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4736                 if (hdsp->io_type != H9632)
4737                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4738                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4739                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4740                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4741                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4742                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4743                                 HDSP_SPDIFOpticalOut);
4744                 info.spdif_professional = (unsigned char)
4745                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4746                 info.spdif_emphasis = (unsigned char)
4747                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4748                 info.spdif_nonaudio = (unsigned char)
4749                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4750                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4751                 info.system_sample_rate = hdsp->system_sample_rate;
4752                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4753                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4754                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4755                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4756                 info.line_out = (unsigned char)
4757                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4758                 if (hdsp->io_type == H9632) {
4759                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4760                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4761                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4762                         info.xlr_breakout_cable =
4763                                 (unsigned char)hdsp_toggle_setting(hdsp,
4764                                         HDSP_XLRBreakoutCable);
4765
4766                 } else if (hdsp->io_type == RPM) {
4767                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4768                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4769                 }
4770                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4771                         info.analog_extension_board =
4772                                 (unsigned char)hdsp_toggle_setting(hdsp,
4773                                             HDSP_AnalogExtensionBoard);
4774                 spin_unlock_irqrestore(&hdsp->lock, flags);
4775                 if (copy_to_user(argp, &info, sizeof(info)))
4776                         return -EFAULT;
4777                 break;
4778         }
4779         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4780                 struct hdsp_9632_aeb h9632_aeb;
4781
4782                 if (hdsp->io_type != H9632) return -EINVAL;
4783                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4784                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4785                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4786                         return -EFAULT;
4787                 break;
4788         }
4789         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4790                 struct hdsp_version hdsp_version;
4791                 int err;
4792
4793                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4794                 if (hdsp->io_type == Undefined) {
4795                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4796                                 return err;
4797                 }
4798                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4799                 hdsp_version.io_type = hdsp->io_type;
4800                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4801                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4802                         return -EFAULT;
4803                 break;
4804         }
4805         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4806                 struct hdsp_firmware __user *firmware;
4807                 u32 __user *firmware_data;
4808                 int err;
4809
4810                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4811                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4812                 if (hdsp->io_type == Undefined) return -EINVAL;
4813
4814                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4815                         return -EBUSY;
4816
4817                 dev_info(hdsp->card->dev,
4818                          "initializing firmware upload\n");
4819                 firmware = (struct hdsp_firmware __user *)argp;
4820
4821                 if (get_user(firmware_data, &firmware->firmware_data))
4822                         return -EFAULT;
4823
4824                 if (hdsp_check_for_iobox (hdsp))
4825                         return -EIO;
4826
4827                 if (!hdsp->fw_uploaded) {
4828                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4829                         if (!hdsp->fw_uploaded)
4830                                 return -ENOMEM;
4831                 }
4832
4833                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4834                                    HDSP_FIRMWARE_SIZE)) {
4835                         vfree(hdsp->fw_uploaded);
4836                         hdsp->fw_uploaded = NULL;
4837                         return -EFAULT;
4838                 }
4839
4840                 hdsp->state |= HDSP_FirmwareCached;
4841
4842                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4843                         return err;
4844
4845                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4846                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4847                                 return err;
4848
4849                         snd_hdsp_initialize_channels(hdsp);
4850                         snd_hdsp_initialize_midi_flush(hdsp);
4851
4852                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4853                                 dev_err(hdsp->card->dev,
4854                                         "error creating alsa devices\n");
4855                                 return err;
4856                         }
4857                 }
4858                 break;
4859         }
4860         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4861                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4862                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4863                         return -EFAULT;
4864                 break;
4865         }
4866         default:
4867                 return -EINVAL;
4868         }
4869         return 0;
4870 }
4871
4872 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4873         .open =         snd_hdsp_playback_open,
4874         .close =        snd_hdsp_playback_release,
4875         .ioctl =        snd_hdsp_ioctl,
4876         .hw_params =    snd_hdsp_hw_params,
4877         .prepare =      snd_hdsp_prepare,
4878         .trigger =      snd_hdsp_trigger,
4879         .pointer =      snd_hdsp_hw_pointer,
4880         .copy_user =    snd_hdsp_playback_copy,
4881         .copy_kernel =  snd_hdsp_playback_copy_kernel,
4882         .fill_silence = snd_hdsp_hw_silence,
4883 };
4884
4885 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4886         .open =         snd_hdsp_capture_open,
4887         .close =        snd_hdsp_capture_release,
4888         .ioctl =        snd_hdsp_ioctl,
4889         .hw_params =    snd_hdsp_hw_params,
4890         .prepare =      snd_hdsp_prepare,
4891         .trigger =      snd_hdsp_trigger,
4892         .pointer =      snd_hdsp_hw_pointer,
4893         .copy_user =    snd_hdsp_capture_copy,
4894         .copy_kernel =  snd_hdsp_capture_copy_kernel,
4895 };
4896
4897 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4898 {
4899         struct snd_hwdep *hw;
4900         int err;
4901
4902         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4903                 return err;
4904
4905         hdsp->hwdep = hw;
4906         hw->private_data = hdsp;
4907         strcpy(hw->name, "HDSP hwdep interface");
4908
4909         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4910         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4911
4912         return 0;
4913 }
4914
4915 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4916 {
4917         struct snd_pcm *pcm;
4918         int err;
4919
4920         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4921                 return err;
4922
4923         hdsp->pcm = pcm;
4924         pcm->private_data = hdsp;
4925         strcpy(pcm->name, hdsp->card_name);
4926
4927         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4928         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4929
4930         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4931
4932         return 0;
4933 }
4934
4935 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4936 {
4937         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4938         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4939 }
4940
4941 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4942 {
4943         int i;
4944
4945         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4946                 dev_err(hdsp->card->dev,
4947                         "enable_io fifo_wait failed\n");
4948                 return -EIO;
4949         }
4950
4951         for (i = 0; i < hdsp->max_channels; ++i) {
4952                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4953                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4954         }
4955
4956         return 0;
4957 }
4958
4959 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4960 {
4961         int status, aebi_channels, aebo_channels;
4962
4963         switch (hdsp->io_type) {
4964         case Digiface:
4965                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4966                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4967                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4968                 break;
4969
4970         case H9652:
4971                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4972                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4973                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4974                 break;
4975
4976         case H9632:
4977                 status = hdsp_read(hdsp, HDSP_statusRegister);
4978                 /* HDSP_AEBx bits are low when AEB are connected */
4979                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4980                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4981                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4982                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4983                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4984                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4985                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4986                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4987                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4988                 break;
4989
4990         case Multiface:
4991                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4992                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4993                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4994                 break;
4995
4996         case RPM:
4997                 hdsp->card_name = "RME Hammerfall DSP + RPM";
4998                 hdsp->ss_in_channels = RPM_CHANNELS-1;
4999                 hdsp->ss_out_channels = RPM_CHANNELS;
5000                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5001                 hdsp->ds_out_channels = RPM_CHANNELS;
5002                 break;
5003
5004         default:
5005                 /* should never get here */
5006                 break;
5007         }
5008 }
5009
5010 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5011 {
5012         snd_hdsp_flush_midi_input (hdsp, 0);
5013         snd_hdsp_flush_midi_input (hdsp, 1);
5014 }
5015
5016 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5017 {
5018         int err;
5019
5020         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5021                 dev_err(card->dev,
5022                         "Error creating pcm interface\n");
5023                 return err;
5024         }
5025
5026
5027         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5028                 dev_err(card->dev,
5029                         "Error creating first midi interface\n");
5030                 return err;
5031         }
5032
5033         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5034                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5035                         dev_err(card->dev,
5036                                 "Error creating second midi interface\n");
5037                         return err;
5038                 }
5039         }
5040
5041         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5042                 dev_err(card->dev,
5043                         "Error creating ctl interface\n");
5044                 return err;
5045         }
5046
5047         snd_hdsp_proc_init(hdsp);
5048
5049         hdsp->system_sample_rate = -1;
5050         hdsp->playback_pid = -1;
5051         hdsp->capture_pid = -1;
5052         hdsp->capture_substream = NULL;
5053         hdsp->playback_substream = NULL;
5054
5055         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5056                 dev_err(card->dev,
5057                         "Error setting default values\n");
5058                 return err;
5059         }
5060
5061         if (!(hdsp->state & HDSP_InitializationComplete)) {
5062                 strcpy(card->shortname, "Hammerfall DSP");
5063                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5064                         hdsp->port, hdsp->irq);
5065
5066                 if ((err = snd_card_register(card)) < 0) {
5067                         dev_err(card->dev,
5068                                 "error registering card\n");
5069                         return err;
5070                 }
5071                 hdsp->state |= HDSP_InitializationComplete;
5072         }
5073
5074         return 0;
5075 }
5076
5077 /* load firmware via hotplug fw loader */
5078 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5079 {
5080         const char *fwfile;
5081         const struct firmware *fw;
5082         int err;
5083
5084         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5085                 return 0;
5086         if (hdsp->io_type == Undefined) {
5087                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5088                         return err;
5089                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5090                         return 0;
5091         }
5092
5093         /* caution: max length of firmware filename is 30! */
5094         switch (hdsp->io_type) {
5095         case RPM:
5096                 fwfile = "/*(DEBLOBBED)*/";
5097                 break;
5098         case Multiface:
5099                 if (hdsp->firmware_rev == 0xa)
5100                         fwfile = "/*(DEBLOBBED)*/";
5101                 else
5102                         fwfile = "/*(DEBLOBBED)*/";
5103                 break;
5104         case Digiface:
5105                 if (hdsp->firmware_rev == 0xa)
5106                         fwfile = "/*(DEBLOBBED)*/";
5107                 else
5108                         fwfile = "/*(DEBLOBBED)*/";
5109                 break;
5110         default:
5111                 dev_err(hdsp->card->dev,
5112                         "invalid io_type %d\n", hdsp->io_type);
5113                 return -EINVAL;
5114         }
5115
5116         if (reject_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5117                 dev_err(hdsp->card->dev,
5118                         "cannot load firmware %s\n", fwfile);
5119                 return -ENOENT;
5120         }
5121         if (fw->size < HDSP_FIRMWARE_SIZE) {
5122                 dev_err(hdsp->card->dev,
5123                         "too short firmware size %d (expected %d)\n",
5124                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5125                 release_firmware(fw);
5126                 return -EINVAL;
5127         }
5128
5129         hdsp->firmware = fw;
5130
5131         hdsp->state |= HDSP_FirmwareCached;
5132
5133         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5134                 return err;
5135
5136         if (!(hdsp->state & HDSP_InitializationComplete)) {
5137                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5138                         return err;
5139
5140                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5141                         dev_err(hdsp->card->dev,
5142                                 "error creating hwdep device\n");
5143                         return err;
5144                 }
5145                 snd_hdsp_initialize_channels(hdsp);
5146                 snd_hdsp_initialize_midi_flush(hdsp);
5147                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5148                         dev_err(hdsp->card->dev,
5149                                 "error creating alsa devices\n");
5150                         return err;
5151                 }
5152         }
5153         return 0;
5154 }
5155
5156 static int snd_hdsp_create(struct snd_card *card,
5157                            struct hdsp *hdsp)
5158 {
5159         struct pci_dev *pci = hdsp->pci;
5160         int err;
5161         int is_9652 = 0;
5162         int is_9632 = 0;
5163
5164         hdsp->irq = -1;
5165         hdsp->state = 0;
5166         hdsp->midi[0].rmidi = NULL;
5167         hdsp->midi[1].rmidi = NULL;
5168         hdsp->midi[0].input = NULL;
5169         hdsp->midi[1].input = NULL;
5170         hdsp->midi[0].output = NULL;
5171         hdsp->midi[1].output = NULL;
5172         hdsp->midi[0].pending = 0;
5173         hdsp->midi[1].pending = 0;
5174         spin_lock_init(&hdsp->midi[0].lock);
5175         spin_lock_init(&hdsp->midi[1].lock);
5176         hdsp->iobase = NULL;
5177         hdsp->control_register = 0;
5178         hdsp->control2_register = 0;
5179         hdsp->io_type = Undefined;
5180         hdsp->max_channels = 26;
5181
5182         hdsp->card = card;
5183
5184         spin_lock_init(&hdsp->lock);
5185
5186         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5187
5188         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5189         hdsp->firmware_rev &= 0xff;
5190
5191         /* From Martin Bjoernsen :
5192             "It is important that the card's latency timer register in
5193             the PCI configuration space is set to a value much larger
5194             than 0 by the computer's BIOS or the driver.
5195             The windows driver always sets this 8 bit register [...]
5196             to its maximum 255 to avoid problems with some computers."
5197         */
5198         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5199
5200         strcpy(card->driver, "H-DSP");
5201         strcpy(card->mixername, "Xilinx FPGA");
5202
5203         if (hdsp->firmware_rev < 0xa)
5204                 return -ENODEV;
5205         else if (hdsp->firmware_rev < 0x64)
5206                 hdsp->card_name = "RME Hammerfall DSP";
5207         else if (hdsp->firmware_rev < 0x96) {
5208                 hdsp->card_name = "RME HDSP 9652";
5209                 is_9652 = 1;
5210         } else {
5211                 hdsp->card_name = "RME HDSP 9632";
5212                 hdsp->max_channels = 16;
5213                 is_9632 = 1;
5214         }
5215
5216         if ((err = pci_enable_device(pci)) < 0)
5217                 return err;
5218
5219         pci_set_master(hdsp->pci);
5220
5221         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5222                 return err;
5223         hdsp->port = pci_resource_start(pci, 0);
5224         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5225                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5226                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5227                 return -EBUSY;
5228         }
5229
5230         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5231                         KBUILD_MODNAME, hdsp)) {
5232                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5233                 return -EBUSY;
5234         }
5235
5236         hdsp->irq = pci->irq;
5237         hdsp->precise_ptr = 0;
5238         hdsp->use_midi_tasklet = 1;
5239         hdsp->dds_value = 0;
5240
5241         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5242                 return err;
5243
5244         if (!is_9652 && !is_9632) {
5245                 /* we wait a maximum of 10 seconds to let freshly
5246                  * inserted cardbus cards do their hardware init */
5247                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5248
5249                 if (err < 0)
5250                         return err;
5251
5252                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5253                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5254                                 /* we don't fail as this can happen
5255                                    if userspace is not ready for
5256                                    firmware upload
5257                                 */
5258                                 dev_err(hdsp->card->dev,
5259                                         "couldn't get firmware from userspace. try using hdsploader\n");
5260                         else
5261                                 /* init is complete, we return */
5262                                 return 0;
5263                         /* we defer initialization */
5264                         dev_info(hdsp->card->dev,
5265                                  "card initialization pending : waiting for firmware\n");
5266                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5267                                 return err;
5268                         return 0;
5269                 } else {
5270                         dev_info(hdsp->card->dev,
5271                                  "Firmware already present, initializing card.\n");
5272                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5273                                 hdsp->io_type = RPM;
5274                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5275                                 hdsp->io_type = Multiface;
5276                         else
5277                                 hdsp->io_type = Digiface;
5278                 }
5279         }
5280
5281         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5282                 return err;
5283
5284         if (is_9652)
5285                 hdsp->io_type = H9652;
5286
5287         if (is_9632)
5288                 hdsp->io_type = H9632;
5289
5290         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5291                 return err;
5292
5293         snd_hdsp_initialize_channels(hdsp);
5294         snd_hdsp_initialize_midi_flush(hdsp);
5295
5296         hdsp->state |= HDSP_FirmwareLoaded;
5297
5298         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5299                 return err;
5300
5301         return 0;
5302 }
5303
5304 static int snd_hdsp_free(struct hdsp *hdsp)
5305 {
5306         if (hdsp->port) {
5307                 /* stop the audio, and cancel all interrupts */
5308                 tasklet_kill(&hdsp->midi_tasklet);
5309                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5310                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5311         }
5312
5313         if (hdsp->irq >= 0)
5314                 free_irq(hdsp->irq, (void *)hdsp);
5315
5316         snd_hdsp_free_buffers(hdsp);
5317
5318         release_firmware(hdsp->firmware);
5319         vfree(hdsp->fw_uploaded);
5320         iounmap(hdsp->iobase);
5321
5322         if (hdsp->port)
5323                 pci_release_regions(hdsp->pci);
5324
5325         pci_disable_device(hdsp->pci);
5326         return 0;
5327 }
5328
5329 static void snd_hdsp_card_free(struct snd_card *card)
5330 {
5331         struct hdsp *hdsp = card->private_data;
5332
5333         if (hdsp)
5334                 snd_hdsp_free(hdsp);
5335 }
5336
5337 static int snd_hdsp_probe(struct pci_dev *pci,
5338                           const struct pci_device_id *pci_id)
5339 {
5340         static int dev;
5341         struct hdsp *hdsp;
5342         struct snd_card *card;
5343         int err;
5344
5345         if (dev >= SNDRV_CARDS)
5346                 return -ENODEV;
5347         if (!enable[dev]) {
5348                 dev++;
5349                 return -ENOENT;
5350         }
5351
5352         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5353                            sizeof(struct hdsp), &card);
5354         if (err < 0)
5355                 return err;
5356
5357         hdsp = card->private_data;
5358         card->private_free = snd_hdsp_card_free;
5359         hdsp->dev = dev;
5360         hdsp->pci = pci;
5361         err = snd_hdsp_create(card, hdsp);
5362         if (err)
5363                 goto free_card;
5364
5365         strcpy(card->shortname, "Hammerfall DSP");
5366         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5367                 hdsp->port, hdsp->irq);
5368         err = snd_card_register(card);
5369         if (err) {
5370 free_card:
5371                 snd_card_free(card);
5372                 return err;
5373         }
5374         pci_set_drvdata(pci, card);
5375         dev++;
5376         return 0;
5377 }
5378
5379 static void snd_hdsp_remove(struct pci_dev *pci)
5380 {
5381         snd_card_free(pci_get_drvdata(pci));
5382 }
5383
5384 static struct pci_driver hdsp_driver = {
5385         .name =     KBUILD_MODNAME,
5386         .id_table = snd_hdsp_ids,
5387         .probe =    snd_hdsp_probe,
5388         .remove = snd_hdsp_remove,
5389 };
5390
5391 module_pci_driver(hdsp_driver);