sound/pci/hda/hda_controller.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  Implementation of primary alsa driver code base for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  */
  11
  12 #include <linux/clocksource.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #ifdef CONFIG_X86
  21 /* for art-tsc conversion */
  22 #include <asm/tsc.h>
  23 #endif
  24
  25 #include <sound/core.h>
  26 #include <sound/initval.h>
  27 #include "hda_controller.h"
  28
  29 #define CREATE_TRACE_POINTS
  30 #include "hda_controller_trace.h"
  31
  32 /* DSP lock helpers */
  33 #define dsp_lock(dev)           snd_hdac_dsp_lock(azx_stream(dev))
  34 #define dsp_unlock(dev)         snd_hdac_dsp_unlock(azx_stream(dev))
  35 #define dsp_is_locked(dev)      snd_hdac_stream_is_locked(azx_stream(dev))
  36
  37 /* assign a stream for the PCM */
  38 static inline struct azx_dev *
  39 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
  40 {
  41         struct hdac_stream *s;
  42
  43         s = snd_hdac_stream_assign(azx_bus(chip), substream);
  44         if (!s)
  45                 return NULL;
  46         return stream_to_azx_dev(s);
  47 }
  48
  49 /* release the assigned stream */
  50 static inline void azx_release_device(struct azx_dev *azx_dev)
  51 {
  52         snd_hdac_stream_release(azx_stream(azx_dev));
  53 }
  54
  55 static inline struct hda_pcm_stream *
  56 to_hda_pcm_stream(struct snd_pcm_substream *substream)
  57 {
  58         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  59         return &apcm->info->stream[substream->stream];
  60 }
  61
  62 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
  63                                 u64 nsec)
  64 {
  65         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  66         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  67         u64 codec_frames, codec_nsecs;
  68
  69         if (!hinfo->ops.get_delay)
  70                 return nsec;
  71
  72         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
  73         codec_nsecs = div_u64(codec_frames * 1000000000LL,
  74                               substream->runtime->rate);
  75
  76         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  77                 return nsec + codec_nsecs;
  78
  79         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
  80 }
  81
  82 /*
  83  * PCM ops
  84  */
  85
  86 static int azx_pcm_close(struct snd_pcm_substream *substream)
  87 {
  88         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  89         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  90         struct azx *chip = apcm->chip;
  91         struct azx_dev *azx_dev = get_azx_dev(substream);
  92
  93         trace_azx_pcm_close(chip, azx_dev);
  94         mutex_lock(&chip->open_mutex);
  95         azx_release_device(azx_dev);
  96         if (hinfo->ops.close)
  97                 hinfo->ops.close(hinfo, apcm->codec, substream);
  98         snd_hda_power_down(apcm->codec);
  99         mutex_unlock(&chip->open_mutex);
 100         snd_hda_codec_pcm_put(apcm->info);
 101         return 0;
 102 }
 103
 104 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 105                              struct snd_pcm_hw_params *hw_params)
 106 {
 107         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 108         struct azx *chip = apcm->chip;
 109         struct azx_dev *azx_dev = get_azx_dev(substream);
 110         int ret;
 111
 112         trace_azx_pcm_hw_params(chip, azx_dev);
 113         dsp_lock(azx_dev);
 114         if (dsp_is_locked(azx_dev)) {
 115                 ret = -EBUSY;
 116                 goto unlock;
 117         }
 118
 119         azx_dev->core.bufsize = 0;
 120         azx_dev->core.period_bytes = 0;
 121         azx_dev->core.format_val = 0;
 122         ret = snd_pcm_lib_malloc_pages(substream,
 123                                        params_buffer_bytes(hw_params));
 124
 125 unlock:
 126         dsp_unlock(azx_dev);
 127         return ret;
 128 }
 129
 130 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 131 {
 132         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 133         struct azx_dev *azx_dev = get_azx_dev(substream);
 134         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 135         int err;
 136
 137         /* reset BDL address */
 138         dsp_lock(azx_dev);
 139         if (!dsp_is_locked(azx_dev))
 140                 snd_hdac_stream_cleanup(azx_stream(azx_dev));
 141
 142         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 143
 144         err = snd_pcm_lib_free_pages(substream);
 145         azx_stream(azx_dev)->prepared = 0;
 146         dsp_unlock(azx_dev);
 147         return err;
 148 }
 149
 150 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 151 {
 152         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 153         struct azx *chip = apcm->chip;
 154         struct azx_dev *azx_dev = get_azx_dev(substream);
 155         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 156         struct snd_pcm_runtime *runtime = substream->runtime;
 157         unsigned int format_val, stream_tag;
 158         int err;
 159         struct hda_spdif_out *spdif =
 160                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 161         unsigned short ctls = spdif ? spdif->ctls : 0;
 162
 163         trace_azx_pcm_prepare(chip, azx_dev);
 164         dsp_lock(azx_dev);
 165         if (dsp_is_locked(azx_dev)) {
 166                 err = -EBUSY;
 167                 goto unlock;
 168         }
 169
 170         snd_hdac_stream_reset(azx_stream(azx_dev));
 171         format_val = snd_hdac_calc_stream_format(runtime->rate,
 172                                                 runtime->channels,
 173                                                 runtime->format,
 174                                                 hinfo->maxbps,
 175                                                 ctls);
 176         if (!format_val) {
 177                 dev_err(chip->card->dev,
 178                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 179                         runtime->rate, runtime->channels, runtime->format);
 180                 err = -EINVAL;
 181                 goto unlock;
 182         }
 183
 184         err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
 185         if (err < 0)
 186                 goto unlock;
 187
 188         snd_hdac_stream_setup(azx_stream(azx_dev));
 189
 190         stream_tag = azx_dev->core.stream_tag;
 191         /* CA-IBG chips need the playback stream starting from 1 */
 192         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 193             stream_tag > chip->capture_streams)
 194                 stream_tag -= chip->capture_streams;
 195         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 196                                      azx_dev->core.format_val, substream);
 197
 198  unlock:
 199         if (!err)
 200                 azx_stream(azx_dev)->prepared = 1;
 201         dsp_unlock(azx_dev);
 202         return err;
 203 }
 204
 205 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 206 {
 207         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 208         struct azx *chip = apcm->chip;
 209         struct hdac_bus *bus = azx_bus(chip);
 210         struct azx_dev *azx_dev;
 211         struct snd_pcm_substream *s;
 212         struct hdac_stream *hstr;
 213         bool start;
 214         int sbits = 0;
 215         int sync_reg;
 216
 217         azx_dev = get_azx_dev(substream);
 218         trace_azx_pcm_trigger(chip, azx_dev, cmd);
 219
 220         hstr = azx_stream(azx_dev);
 221         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 222                 sync_reg = AZX_REG_OLD_SSYNC;
 223         else
 224                 sync_reg = AZX_REG_SSYNC;
 225
 226         if (dsp_is_locked(azx_dev) || !hstr->prepared)
 227                 return -EPIPE;
 228
 229         switch (cmd) {
 230         case SNDRV_PCM_TRIGGER_START:
 231         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 232         case SNDRV_PCM_TRIGGER_RESUME:
 233                 start = true;
 234                 break;
 235         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 236         case SNDRV_PCM_TRIGGER_SUSPEND:
 237         case SNDRV_PCM_TRIGGER_STOP:
 238                 start = false;
 239                 break;
 240         default:
 241                 return -EINVAL;
 242         }
 243
 244         snd_pcm_group_for_each_entry(s, substream) {
 245                 if (s->pcm->card != substream->pcm->card)
 246                         continue;
 247                 azx_dev = get_azx_dev(s);
 248                 sbits |= 1 << azx_dev->core.index;
 249                 snd_pcm_trigger_done(s, substream);
 250         }
 251
 252         spin_lock(&bus->reg_lock);
 253
 254         /* first, set SYNC bits of corresponding streams */
 255         snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
 256
 257         snd_pcm_group_for_each_entry(s, substream) {
 258                 if (s->pcm->card != substream->pcm->card)
 259                         continue;
 260                 azx_dev = get_azx_dev(s);
 261                 if (start) {
 262                         azx_dev->insufficient = 1;
 263                         snd_hdac_stream_start(azx_stream(azx_dev), true);
 264                 } else {
 265                         snd_hdac_stream_stop(azx_stream(azx_dev));
 266                 }
 267         }
 268         spin_unlock(&bus->reg_lock);
 269
 270         snd_hdac_stream_sync(hstr, start, sbits);
 271
 272         spin_lock(&bus->reg_lock);
 273         /* reset SYNC bits */
 274         snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
 275         if (start)
 276                 snd_hdac_stream_timecounter_init(hstr, sbits);
 277         spin_unlock(&bus->reg_lock);
 278         return 0;
 279 }
 280
 281 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 282 {
 283         return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 284 }
 285 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 286
 287 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 288 {
 289         return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
 290 }
 291 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 292
 293 unsigned int azx_get_position(struct azx *chip,
 294                               struct azx_dev *azx_dev)
 295 {
 296         struct snd_pcm_substream *substream = azx_dev->core.substream;
 297         unsigned int pos;
 298         int stream = substream->stream;
 299         int delay = 0;
 300
 301         if (chip->get_position[stream])
 302                 pos = chip->get_position[stream](chip, azx_dev);
 303         else /* use the position buffer as default */
 304                 pos = azx_get_pos_posbuf(chip, azx_dev);
 305
 306         if (pos >= azx_dev->core.bufsize)
 307                 pos = 0;
 308
 309         if (substream->runtime) {
 310                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 311                 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 312
 313                 if (chip->get_delay[stream])
 314                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 315                 if (hinfo->ops.get_delay)
 316                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 317                                                       substream);
 318                 substream->runtime->delay = delay;
 319         }
 320
 321         trace_azx_get_position(chip, azx_dev, pos, delay);
 322         return pos;
 323 }
 324 EXPORT_SYMBOL_GPL(azx_get_position);
 325
 326 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 327 {
 328         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 329         struct azx *chip = apcm->chip;
 330         struct azx_dev *azx_dev = get_azx_dev(substream);
 331         return bytes_to_frames(substream->runtime,
 332                                azx_get_position(chip, azx_dev));
 333 }
 334
 335 /*
 336  * azx_scale64: Scale base by mult/div while not overflowing sanely
 337  *
 338  * Derived from scale64_check_overflow in kernel/time/timekeeping.c
 339  *
 340  * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
 341  * is about 384307 ie ~4.5 days.
 342  *
 343  * This scales the calculation so that overflow will happen but after 2^64 /
 344  * 48000 secs, which is pretty large!
 345  *
 346  * In caln below:
 347  *      base may overflow, but since there isn’t any additional division
 348  *      performed on base it’s OK
 349  *      rem can’t overflow because both are 32-bit values
 350  */
 351
 352 #ifdef CONFIG_X86
 353 static u64 azx_scale64(u64 base, u32 num, u32 den)
 354 {
 355         u64 rem;
 356
 357         rem = do_div(base, den);
 358
 359         base *= num;
 360         rem *= num;
 361
 362         do_div(rem, den);
 363
 364         return base + rem;
 365 }
 366
 367 static int azx_get_sync_time(ktime_t *device,
 368                 struct system_counterval_t *system, void *ctx)
 369 {
 370         struct snd_pcm_substream *substream = ctx;
 371         struct azx_dev *azx_dev = get_azx_dev(substream);
 372         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 373         struct azx *chip = apcm->chip;
 374         struct snd_pcm_runtime *runtime;
 375         u64 ll_counter, ll_counter_l, ll_counter_h;
 376         u64 tsc_counter, tsc_counter_l, tsc_counter_h;
 377         u32 wallclk_ctr, wallclk_cycles;
 378         bool direction;
 379         u32 dma_select;
 380         u32 timeout = 200;
 381         u32 retry_count = 0;
 382
 383         runtime = substream->runtime;
 384
 385         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 386                 direction = 1;
 387         else
 388                 direction = 0;
 389
 390         /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
 391         do {
 392                 timeout = 100;
 393                 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
 394                                         (azx_dev->core.stream_tag - 1);
 395                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
 396
 397                 /* Enable the capture */
 398                 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
 399
 400                 while (timeout) {
 401                         if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
 402                                                 GTSCC_TSCCD_MASK)
 403                                 break;
 404
 405                         timeout--;
 406                 }
 407
 408                 if (!timeout) {
 409                         dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
 410                         return -EIO;
 411                 }
 412
 413                 /* Read wall clock counter */
 414                 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
 415
 416                 /* Read TSC counter */
 417                 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
 418                 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
 419
 420                 /* Read Link counter */
 421                 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
 422                 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
 423
 424                 /* Ack: registers read done */
 425                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
 426
 427                 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
 428                                                 tsc_counter_l;
 429
 430                 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
 431                 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
 432
 433                 /*
 434                  * An error occurs near frame "rollover". The clocks in
 435                  * frame value indicates whether this error may have
 436                  * occurred. Here we use the value of 10 i.e.,
 437                  * HDA_MAX_CYCLE_OFFSET
 438                  */
 439                 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
 440                                         && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
 441                         break;
 442
 443                 /*
 444                  * Sleep before we read again, else we may again get
 445                  * value near to MAX_CYCLE. Try to sleep for different
 446                  * amount of time so we dont hit the same number again
 447                  */
 448                 udelay(retry_count++);
 449
 450         } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
 451
 452         if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
 453                 dev_err_ratelimited(chip->card->dev,
 454                         "Error in WALFCC cycle count\n");
 455                 return -EIO;
 456         }
 457
 458         *device = ns_to_ktime(azx_scale64(ll_counter,
 459                                 NSEC_PER_SEC, runtime->rate));
 460         *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
 461                                ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
 462
 463         *system = convert_art_to_tsc(tsc_counter);
 464
 465         return 0;
 466 }
 467
 468 #else
 469 static int azx_get_sync_time(ktime_t *device,
 470                 struct system_counterval_t *system, void *ctx)
 471 {
 472         return -ENXIO;
 473 }
 474 #endif
 475
 476 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
 477                               struct system_device_crosststamp *xtstamp)
 478 {
 479         return get_device_system_crosststamp(azx_get_sync_time,
 480                                         substream, NULL, xtstamp);
 481 }
 482
 483 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
 484                                 struct snd_pcm_audio_tstamp_config *ts)
 485 {
 486         if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
 487                 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
 488                         return true;
 489
 490         return false;
 491 }
 492
 493 static int azx_get_time_info(struct snd_pcm_substream *substream,
 494                         struct timespec *system_ts, struct timespec *audio_ts,
 495                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 496                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 497 {
 498         struct azx_dev *azx_dev = get_azx_dev(substream);
 499         struct snd_pcm_runtime *runtime = substream->runtime;
 500         struct system_device_crosststamp xtstamp;
 501         int ret;
 502         u64 nsec;
 503
 504         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 505                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 506
 507                 snd_pcm_gettime(substream->runtime, system_ts);
 508
 509                 nsec = timecounter_read(&azx_dev->core.tc);
 510                 nsec = div_u64(nsec, 3); /* can be optimized */
 511                 if (audio_tstamp_config->report_delay)
 512                         nsec = azx_adjust_codec_delay(substream, nsec);
 513
 514                 *audio_ts = ns_to_timespec(nsec);
 515
 516                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 517                 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 518                 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 519
 520         } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
 521
 522                 ret = azx_get_crosststamp(substream, &xtstamp);
 523                 if (ret)
 524                         return ret;
 525
 526                 switch (runtime->tstamp_type) {
 527                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
 528                         return -EINVAL;
 529
 530                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
 531                         *system_ts = ktime_to_timespec(xtstamp.sys_monoraw);
 532                         break;
 533
 534                 default:
 535                         *system_ts = ktime_to_timespec(xtstamp.sys_realtime);
 536                         break;
 537
 538                 }
 539
 540                 *audio_ts = ktime_to_timespec(xtstamp.device);
 541
 542                 audio_tstamp_report->actual_type =
 543                         SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
 544                 audio_tstamp_report->accuracy_report = 1;
 545                 /* 24 MHz WallClock == 42ns resolution */
 546                 audio_tstamp_report->accuracy = 42;
 547
 548         } else {
 549                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static struct snd_pcm_hardware azx_pcm_hw = {
 556         .info =                 (SNDRV_PCM_INFO_MMAP |
 557                                  SNDRV_PCM_INFO_INTERLEAVED |
 558                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 559                                  SNDRV_PCM_INFO_MMAP_VALID |
 560                                  /* No full-resume yet implemented */
 561                                  /* SNDRV_PCM_INFO_RESUME |*/
 562                                  SNDRV_PCM_INFO_PAUSE |
 563                                  SNDRV_PCM_INFO_SYNC_START |
 564                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 565                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 566                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 567         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 568         .rates =                SNDRV_PCM_RATE_48000,
 569         .rate_min =             48000,
 570         .rate_max =             48000,
 571         .channels_min =         2,
 572         .channels_max =         2,
 573         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 574         .period_bytes_min =     128,
 575         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 576         .periods_min =          2,
 577         .periods_max =          AZX_MAX_FRAG,
 578         .fifo_size =            0,
 579 };
 580
 581 static int azx_pcm_open(struct snd_pcm_substream *substream)
 582 {
 583         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 584         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 585         struct azx *chip = apcm->chip;
 586         struct azx_dev *azx_dev;
 587         struct snd_pcm_runtime *runtime = substream->runtime;
 588         int err;
 589         int buff_step;
 590
 591         snd_hda_codec_pcm_get(apcm->info);
 592         mutex_lock(&chip->open_mutex);
 593         azx_dev = azx_assign_device(chip, substream);
 594         trace_azx_pcm_open(chip, azx_dev);
 595         if (azx_dev == NULL) {
 596                 err = -EBUSY;
 597                 goto unlock;
 598         }
 599         runtime->private_data = azx_dev;
 600
 601         runtime->hw = azx_pcm_hw;
 602         if (chip->gts_present)
 603                 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
 604         runtime->hw.channels_min = hinfo->channels_min;
 605         runtime->hw.channels_max = hinfo->channels_max;
 606         runtime->hw.formats = hinfo->formats;
 607         runtime->hw.rates = hinfo->rates;
 608         snd_pcm_limit_hw_rates(runtime);
 609         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 610
 611         /* avoid wrap-around with wall-clock */
 612         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 613                                      20,
 614                                      178000000);
 615
 616         /* by some reason, the playback stream stalls on PulseAudio with
 617          * tsched=1 when a capture stream triggers.  Until we figure out the
 618          * real cause, disable tsched mode by telling the PCM info flag.
 619          */
 620         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND)
 621                 runtime->hw.info |= SNDRV_PCM_INFO_BATCH;
 622
 623         if (chip->align_buffer_size)
 624                 /* constrain buffer sizes to be multiple of 128
 625                    bytes. This is more efficient in terms of memory
 626                    access but isn't required by the HDA spec and
 627                    prevents users from specifying exact period/buffer
 628                    sizes. For example for 44.1kHz, a period size set
 629                    to 20ms will be rounded to 19.59ms. */
 630                 buff_step = 128;
 631         else
 632                 /* Don't enforce steps on buffer sizes, still need to
 633                    be multiple of 4 bytes (HDA spec). Tested on Intel
 634                    HDA controllers, may not work on all devices where
 635                    option needs to be disabled */
 636                 buff_step = 4;
 637
 638         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 639                                    buff_step);
 640         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 641                                    buff_step);
 642         snd_hda_power_up(apcm->codec);
 643         if (hinfo->ops.open)
 644                 err = hinfo->ops.open(hinfo, apcm->codec, substream);
 645         else
 646                 err = -ENODEV;
 647         if (err < 0) {
 648                 azx_release_device(azx_dev);
 649                 goto powerdown;
 650         }
 651         snd_pcm_limit_hw_rates(runtime);
 652         /* sanity check */
 653         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 654             snd_BUG_ON(!runtime->hw.channels_max) ||
 655             snd_BUG_ON(!runtime->hw.formats) ||
 656             snd_BUG_ON(!runtime->hw.rates)) {
 657                 azx_release_device(azx_dev);
 658                 if (hinfo->ops.close)
 659                         hinfo->ops.close(hinfo, apcm->codec, substream);
 660                 err = -EINVAL;
 661                 goto powerdown;
 662         }
 663
 664         /* disable LINK_ATIME timestamps for capture streams
 665            until we figure out how to handle digital inputs */
 666         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 667                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 668                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 669         }
 670
 671         snd_pcm_set_sync(substream);
 672         mutex_unlock(&chip->open_mutex);
 673         return 0;
 674
 675  powerdown:
 676         snd_hda_power_down(apcm->codec);
 677  unlock:
 678         mutex_unlock(&chip->open_mutex);
 679         snd_hda_codec_pcm_put(apcm->info);
 680         return err;
 681 }
 682
 683 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
 684                         struct vm_area_struct *area)
 685 {
 686         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 687         struct azx *chip = apcm->chip;
 688         if (chip->ops->pcm_mmap_prepare)
 689                 chip->ops->pcm_mmap_prepare(substream, area);
 690         return snd_pcm_lib_default_mmap(substream, area);
 691 }
 692
 693 static const struct snd_pcm_ops azx_pcm_ops = {
 694         .open = azx_pcm_open,
 695         .close = azx_pcm_close,
 696         .ioctl = snd_pcm_lib_ioctl,
 697         .hw_params = azx_pcm_hw_params,
 698         .hw_free = azx_pcm_hw_free,
 699         .prepare = azx_pcm_prepare,
 700         .trigger = azx_pcm_trigger,
 701         .pointer = azx_pcm_pointer,
 702         .get_time_info =  azx_get_time_info,
 703         .mmap = azx_pcm_mmap,
 704         .page = snd_pcm_sgbuf_ops_page,
 705 };
 706
 707 static void azx_pcm_free(struct snd_pcm *pcm)
 708 {
 709         struct azx_pcm *apcm = pcm->private_data;
 710         if (apcm) {
 711                 list_del(&apcm->list);
 712                 apcm->info->pcm = NULL;
 713                 kfree(apcm);
 714         }
 715 }
 716
 717 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 718
 719 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
 720                               struct hda_pcm *cpcm)
 721 {
 722         struct hdac_bus *bus = &_bus->core;
 723         struct azx *chip = bus_to_azx(bus);
 724         struct snd_pcm *pcm;
 725         struct azx_pcm *apcm;
 726         int pcm_dev = cpcm->device;
 727         unsigned int size;
 728         int s, err;
 729         int type = SNDRV_DMA_TYPE_DEV_SG;
 730
 731         list_for_each_entry(apcm, &chip->pcm_list, list) {
 732                 if (apcm->pcm->device == pcm_dev) {
 733                         dev_err(chip->card->dev, "PCM %d already exists\n",
 734                                 pcm_dev);
 735                         return -EBUSY;
 736                 }
 737         }
 738         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 739                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 740                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 741                           &pcm);
 742         if (err < 0)
 743                 return err;
 744         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
 745         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 746         if (apcm == NULL) {
 747                 snd_device_free(chip->card, pcm);
 748                 return -ENOMEM;
 749         }
 750         apcm->chip = chip;
 751         apcm->pcm = pcm;
 752         apcm->codec = codec;
 753         apcm->info = cpcm;
 754         pcm->private_data = apcm;
 755         pcm->private_free = azx_pcm_free;
 756         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 757                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 758         list_add_tail(&apcm->list, &chip->pcm_list);
 759         cpcm->pcm = pcm;
 760         for (s = 0; s < 2; s++) {
 761                 if (cpcm->stream[s].substreams)
 762                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 763         }
 764         /* buffer pre-allocation */
 765         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 766         if (size > MAX_PREALLOC_SIZE)
 767                 size = MAX_PREALLOC_SIZE;
 768         if (chip->uc_buffer)
 769                 type = SNDRV_DMA_TYPE_DEV_UC_SG;
 770         snd_pcm_lib_preallocate_pages_for_all(pcm, type,
 771                                               chip->card->dev,
 772                                               size, MAX_PREALLOC_SIZE);
 773         return 0;
 774 }
 775
 776 static unsigned int azx_command_addr(u32 cmd)
 777 {
 778         unsigned int addr = cmd >> 28;
 779
 780         if (addr >= AZX_MAX_CODECS) {
 781                 snd_BUG();
 782                 addr = 0;
 783         }
 784
 785         return addr;
 786 }
 787
 788 /* receive a response */
 789 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
 790                                  unsigned int *res)
 791 {
 792         struct azx *chip = bus_to_azx(bus);
 793         struct hda_bus *hbus = &chip->bus;
 794         unsigned long timeout;
 795         unsigned long loopcounter;
 796         int do_poll = 0;
 797
 798  again:
 799         timeout = jiffies + msecs_to_jiffies(1000);
 800
 801         for (loopcounter = 0;; loopcounter++) {
 802                 spin_lock_irq(&bus->reg_lock);
 803                 if (bus->polling_mode || do_poll)
 804                         snd_hdac_bus_update_rirb(bus);
 805                 if (!bus->rirb.cmds[addr]) {
 806                         if (!do_poll)
 807                                 bus->poll_count = 0;
 808                         if (res)
 809                                 *res = bus->rirb.res[addr]; /* the last value */
 810                         spin_unlock_irq(&bus->reg_lock);
 811                         return 0;
 812                 }
 813                 spin_unlock_irq(&bus->reg_lock);
 814                 if (time_after(jiffies, timeout))
 815                         break;
 816                 if (hbus->needs_damn_long_delay || loopcounter > 3000)
 817                         msleep(2); /* temporary workaround */
 818                 else {
 819                         udelay(10);
 820                         cond_resched();
 821                 }
 822         }
 823
 824         if (hbus->no_response_fallback)
 825                 return -EIO;
 826
 827         if (!bus->polling_mode && bus->poll_count < 2) {
 828                 dev_dbg(chip->card->dev,
 829                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
 830                         bus->last_cmd[addr]);
 831                 do_poll = 1;
 832                 bus->poll_count++;
 833                 goto again;
 834         }
 835
 836
 837         if (!bus->polling_mode) {
 838                 dev_warn(chip->card->dev,
 839                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 840                          bus->last_cmd[addr]);
 841                 bus->polling_mode = 1;
 842                 goto again;
 843         }
 844
 845         if (chip->msi) {
 846                 dev_warn(chip->card->dev,
 847                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
 848                          bus->last_cmd[addr]);
 849                 if (chip->ops->disable_msi_reset_irq &&
 850                     chip->ops->disable_msi_reset_irq(chip) < 0)
 851                         return -EIO;
 852                 goto again;
 853         }
 854
 855         if (chip->probing) {
 856                 /* If this critical timeout happens during the codec probing
 857                  * phase, this is likely an access to a non-existing codec
 858                  * slot.  Better to return an error and reset the system.
 859                  */
 860                 return -EIO;
 861         }
 862
 863         /* no fallback mechanism? */
 864         if (!chip->fallback_to_single_cmd)
 865                 return -EIO;
 866
 867         /* a fatal communication error; need either to reset or to fallback
 868          * to the single_cmd mode
 869          */
 870         if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
 871                 hbus->response_reset = 1;
 872                 dev_err(chip->card->dev,
 873                         "No response from codec, resetting bus: last cmd=0x%08x\n",
 874                         bus->last_cmd[addr]);
 875                 return -EAGAIN; /* give a chance to retry */
 876         }
 877
 878         dev_WARN(chip->card->dev,
 879                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
 880                 bus->last_cmd[addr]);
 881         chip->single_cmd = 1;
 882         hbus->response_reset = 0;
 883         snd_hdac_bus_stop_cmd_io(bus);
 884         return -EIO;
 885 }
 886
 887 /*
 888  * Use the single immediate command instead of CORB/RIRB for simplicity
 889  *
 890  * Note: according to Intel, this is not preferred use.  The command was
 891  *       intended for the BIOS only, and may get confused with unsolicited
 892  *       responses.  So, we shouldn't use it for normal operation from the
 893  *       driver.
 894  *       I left the codes, however, for debugging/testing purposes.
 895  */
 896
 897 /* receive a response */
 898 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 899 {
 900         int timeout = 50;
 901
 902         while (timeout--) {
 903                 /* check IRV busy bit */
 904                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
 905                         /* reuse rirb.res as the response return value */
 906                         azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
 907                         return 0;
 908                 }
 909                 udelay(1);
 910         }
 911         if (printk_ratelimit())
 912                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
 913                         azx_readw(chip, IRS));
 914         azx_bus(chip)->rirb.res[addr] = -1;
 915         return -EIO;
 916 }
 917
 918 /* send a command */
 919 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
 920 {
 921         struct azx *chip = bus_to_azx(bus);
 922         unsigned int addr = azx_command_addr(val);
 923         int timeout = 50;
 924
 925         bus->last_cmd[azx_command_addr(val)] = val;
 926         while (timeout--) {
 927                 /* check ICB busy bit */
 928                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
 929                         /* Clear IRV valid bit */
 930                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 931                                    AZX_IRS_VALID);
 932                         azx_writel(chip, IC, val);
 933                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 934                                    AZX_IRS_BUSY);
 935                         return azx_single_wait_for_response(chip, addr);
 936                 }
 937                 udelay(1);
 938         }
 939         if (printk_ratelimit())
 940                 dev_dbg(chip->card->dev,
 941                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 942                         azx_readw(chip, IRS), val);
 943         return -EIO;
 944 }
 945
 946 /* receive a response */
 947 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
 948                                    unsigned int *res)
 949 {
 950         if (res)
 951                 *res = bus->rirb.res[addr];
 952         return 0;
 953 }
 954
 955 /*
 956  * The below are the main callbacks from hda_codec.
 957  *
 958  * They are just the skeleton to call sub-callbacks according to the
 959  * current setting of chip->single_cmd.
 960  */
 961
 962 /* send a command */
 963 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
 964 {
 965         struct azx *chip = bus_to_azx(bus);
 966
 967         if (chip->disabled)
 968                 return 0;
 969         if (chip->single_cmd)
 970                 return azx_single_send_cmd(bus, val);
 971         else
 972                 return snd_hdac_bus_send_cmd(bus, val);
 973 }
 974
 975 /* get a response */
 976 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
 977                             unsigned int *res)
 978 {
 979         struct azx *chip = bus_to_azx(bus);
 980
 981         if (chip->disabled)
 982                 return 0;
 983         if (chip->single_cmd)
 984                 return azx_single_get_response(bus, addr, res);
 985         else
 986                 return azx_rirb_get_response(bus, addr, res);
 987 }
 988
 989 static const struct hdac_bus_ops bus_core_ops = {
 990         .command = azx_send_cmd,
 991         .get_response = azx_get_response,
 992 };
 993
 994 #ifdef CONFIG_SND_HDA_DSP_LOADER
 995 /*
 996  * DSP loading code (e.g. for CA0132)
 997  */
 998
 999 /* use the first stream for loading DSP */
1000 static struct azx_dev *
1001 azx_get_dsp_loader_dev(struct azx *chip)
1002 {
1003         struct hdac_bus *bus = azx_bus(chip);
1004         struct hdac_stream *s;
1005
1006         list_for_each_entry(s, &bus->stream_list, list)
1007                 if (s->index == chip->playback_index_offset)
1008                         return stream_to_azx_dev(s);
1009
1010         return NULL;
1011 }
1012
1013 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1014                                    unsigned int byte_size,
1015                                    struct snd_dma_buffer *bufp)
1016 {
1017         struct hdac_bus *bus = &codec->bus->core;
1018         struct azx *chip = bus_to_azx(bus);
1019         struct azx_dev *azx_dev;
1020         struct hdac_stream *hstr;
1021         bool saved = false;
1022         int err;
1023
1024         azx_dev = azx_get_dsp_loader_dev(chip);
1025         hstr = azx_stream(azx_dev);
1026         spin_lock_irq(&bus->reg_lock);
1027         if (hstr->opened) {
1028                 chip->saved_azx_dev = *azx_dev;
1029                 saved = true;
1030         }
1031         spin_unlock_irq(&bus->reg_lock);
1032
1033         err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
1034         if (err < 0) {
1035                 spin_lock_irq(&bus->reg_lock);
1036                 if (saved)
1037                         *azx_dev = chip->saved_azx_dev;
1038                 spin_unlock_irq(&bus->reg_lock);
1039                 return err;
1040         }
1041
1042         hstr->prepared = 0;
1043         return err;
1044 }
1045 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
1046
1047 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1048 {
1049         struct hdac_bus *bus = &codec->bus->core;
1050         struct azx *chip = bus_to_azx(bus);
1051         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1052
1053         snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
1054 }
1055 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
1056
1057 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1058                                     struct snd_dma_buffer *dmab)
1059 {
1060         struct hdac_bus *bus = &codec->bus->core;
1061         struct azx *chip = bus_to_azx(bus);
1062         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1063         struct hdac_stream *hstr = azx_stream(azx_dev);
1064
1065         if (!dmab->area || !hstr->locked)
1066                 return;
1067
1068         snd_hdac_dsp_cleanup(hstr, dmab);
1069         spin_lock_irq(&bus->reg_lock);
1070         if (hstr->opened)
1071                 *azx_dev = chip->saved_azx_dev;
1072         hstr->locked = false;
1073         spin_unlock_irq(&bus->reg_lock);
1074 }
1075 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1076 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1077
1078 /*
1079  * reset and start the controller registers
1080  */
1081 void azx_init_chip(struct azx *chip, bool full_reset)
1082 {
1083         if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1084                 /* correct RINTCNT for CXT */
1085                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1086                         azx_writew(chip, RINTCNT, 0xc0);
1087         }
1088 }
1089 EXPORT_SYMBOL_GPL(azx_init_chip);
1090
1091 void azx_stop_all_streams(struct azx *chip)
1092 {
1093         struct hdac_bus *bus = azx_bus(chip);
1094         struct hdac_stream *s;
1095
1096         list_for_each_entry(s, &bus->stream_list, list)
1097                 snd_hdac_stream_stop(s);
1098 }
1099 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1100
1101 void azx_stop_chip(struct azx *chip)
1102 {
1103         snd_hdac_bus_stop_chip(azx_bus(chip));
1104 }
1105 EXPORT_SYMBOL_GPL(azx_stop_chip);
1106
1107 /*
1108  * interrupt handler
1109  */
1110 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1111 {
1112         struct azx *chip = bus_to_azx(bus);
1113         struct azx_dev *azx_dev = stream_to_azx_dev(s);
1114
1115         /* check whether this IRQ is really acceptable */
1116         if (!chip->ops->position_check ||
1117             chip->ops->position_check(chip, azx_dev)) {
1118                 spin_unlock(&bus->reg_lock);
1119                 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1120                 spin_lock(&bus->reg_lock);
1121         }
1122 }
1123
1124 irqreturn_t azx_interrupt(int irq, void *dev_id)
1125 {
1126         struct azx *chip = dev_id;
1127         struct hdac_bus *bus = azx_bus(chip);
1128         u32 status;
1129         bool active, handled = false;
1130         int repeat = 0; /* count for avoiding endless loop */
1131
1132 #ifdef CONFIG_PM
1133         if (azx_has_pm_runtime(chip))
1134                 if (!pm_runtime_active(chip->card->dev))
1135                         return IRQ_NONE;
1136 #endif
1137
1138         spin_lock(&bus->reg_lock);
1139
1140         if (chip->disabled)
1141                 goto unlock;
1142
1143         do {
1144                 status = azx_readl(chip, INTSTS);
1145                 if (status == 0 || status == 0xffffffff)
1146                         break;
1147
1148                 handled = true;
1149                 active = false;
1150                 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1151                         active = true;
1152
1153                 /* clear rirb int */
1154                 status = azx_readb(chip, RIRBSTS);
1155                 if (status & RIRB_INT_MASK) {
1156                         active = true;
1157                         if (status & RIRB_INT_RESPONSE) {
1158                                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1159                                         udelay(80);
1160                                 snd_hdac_bus_update_rirb(bus);
1161                         }
1162                         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1163                 }
1164         } while (active && ++repeat < 10);
1165
1166  unlock:
1167         spin_unlock(&bus->reg_lock);
1168
1169         return IRQ_RETVAL(handled);
1170 }
1171 EXPORT_SYMBOL_GPL(azx_interrupt);
1172
1173 /*
1174  * Codec initerface
1175  */
1176
1177 /*
1178  * Probe the given codec address
1179  */
1180 static int probe_codec(struct azx *chip, int addr)
1181 {
1182         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1183                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1184         struct hdac_bus *bus = azx_bus(chip);
1185         int err;
1186         unsigned int res = -1;
1187
1188         mutex_lock(&bus->cmd_mutex);
1189         chip->probing = 1;
1190         azx_send_cmd(bus, cmd);
1191         err = azx_get_response(bus, addr, &res);
1192         chip->probing = 0;
1193         mutex_unlock(&bus->cmd_mutex);
1194         if (err < 0 || res == -1)
1195                 return -EIO;
1196         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1197         return 0;
1198 }
1199
1200 void snd_hda_bus_reset(struct hda_bus *bus)
1201 {
1202         struct azx *chip = bus_to_azx(&bus->core);
1203
1204         bus->in_reset = 1;
1205         azx_stop_chip(chip);
1206         azx_init_chip(chip, true);
1207         if (bus->core.chip_init)
1208                 snd_hda_bus_reset_codecs(bus);
1209         bus->in_reset = 0;
1210 }
1211
1212 /* HD-audio bus initialization */
1213 int azx_bus_init(struct azx *chip, const char *model,
1214                  const struct hdac_io_ops *io_ops)
1215 {
1216         struct hda_bus *bus = &chip->bus;
1217         int err;
1218
1219         err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
1220                                 io_ops);
1221         if (err < 0)
1222                 return err;
1223
1224         bus->card = chip->card;
1225         mutex_init(&bus->prepare_mutex);
1226         bus->pci = chip->pci;
1227         bus->modelname = model;
1228         bus->mixer_assigned = -1;
1229         bus->core.snoop = azx_snoop(chip);
1230         if (chip->get_position[0] != azx_get_pos_lpib ||
1231             chip->get_position[1] != azx_get_pos_lpib)
1232                 bus->core.use_posbuf = true;
1233         bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1234         if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1235                 bus->core.corbrp_self_clear = true;
1236
1237         if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1238                 bus->core.align_bdle_4k = true;
1239
1240         /* AMD chipsets often cause the communication stalls upon certain
1241          * sequence like the pin-detection.  It seems that forcing the synced
1242          * access works around the stall.  Grrr...
1243          */
1244         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1245                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1246                 bus->core.sync_write = 1;
1247                 bus->allow_bus_reset = 1;
1248         }
1249
1250         return 0;
1251 }
1252 EXPORT_SYMBOL_GPL(azx_bus_init);
1253
1254 /* Probe codecs */
1255 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1256 {
1257         struct hdac_bus *bus = azx_bus(chip);
1258         int c, codecs, err;
1259
1260         codecs = 0;
1261         if (!max_slots)
1262                 max_slots = AZX_DEFAULT_CODECS;
1263
1264         /* First try to probe all given codec slots */
1265         for (c = 0; c < max_slots; c++) {
1266                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1267                         if (probe_codec(chip, c) < 0) {
1268                                 /* Some BIOSen give you wrong codec addresses
1269                                  * that don't exist
1270                                  */
1271                                 dev_warn(chip->card->dev,
1272                                          "Codec #%d probe error; disabling it...\n", c);
1273                                 bus->codec_mask &= ~(1 << c);
1274                                 /* More badly, accessing to a non-existing
1275                                  * codec often screws up the controller chip,
1276                                  * and disturbs the further communications.
1277                                  * Thus if an error occurs during probing,
1278                                  * better to reset the controller chip to
1279                                  * get back to the sanity state.
1280                                  */
1281                                 azx_stop_chip(chip);
1282                                 azx_init_chip(chip, true);
1283                         }
1284                 }
1285         }
1286
1287         /* Then create codec instances */
1288         for (c = 0; c < max_slots; c++) {
1289                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1290                         struct hda_codec *codec;
1291                         err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1292                         if (err < 0)
1293                                 continue;
1294                         codec->jackpoll_interval = chip->jackpoll_interval;
1295                         codec->beep_mode = chip->beep_mode;
1296                         codecs++;
1297                 }
1298         }
1299         if (!codecs) {
1300                 dev_err(chip->card->dev, "no codecs initialized\n");
1301                 return -ENXIO;
1302         }
1303         return 0;
1304 }
1305 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1306
1307 /* configure each codec instance */
1308 int azx_codec_configure(struct azx *chip)
1309 {
1310         struct hda_codec *codec, *next;
1311
1312         /* use _safe version here since snd_hda_codec_configure() deregisters
1313          * the device upon error and deletes itself from the bus list.
1314          */
1315         list_for_each_codec_safe(codec, next, &chip->bus) {
1316                 snd_hda_codec_configure(codec);
1317         }
1318
1319         if (!azx_bus(chip)->num_codecs)
1320                 return -ENODEV;
1321         return 0;
1322 }
1323 EXPORT_SYMBOL_GPL(azx_codec_configure);
1324
1325 static int stream_direction(struct azx *chip, unsigned char index)
1326 {
1327         if (index >= chip->capture_index_offset &&
1328             index < chip->capture_index_offset + chip->capture_streams)
1329                 return SNDRV_PCM_STREAM_CAPTURE;
1330         return SNDRV_PCM_STREAM_PLAYBACK;
1331 }
1332
1333 /* initialize SD streams */
1334 int azx_init_streams(struct azx *chip)
1335 {
1336         int i;
1337         int stream_tags[2] = { 0, 0 };
1338
1339         /* initialize each stream (aka device)
1340          * assign the starting bdl address to each stream (device)
1341          * and initialize
1342          */
1343         for (i = 0; i < chip->num_streams; i++) {
1344                 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1345                 int dir, tag;
1346
1347                 if (!azx_dev)
1348                         return -ENOMEM;
1349
1350                 dir = stream_direction(chip, i);
1351                 /* stream tag must be unique throughout
1352                  * the stream direction group,
1353                  * valid values 1...15
1354                  * use separate stream tag if the flag
1355                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1356                  */
1357                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1358                         tag = ++stream_tags[dir];
1359                 else
1360                         tag = i + 1;
1361                 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1362                                      i, dir, tag);
1363         }
1364
1365         return 0;
1366 }
1367 EXPORT_SYMBOL_GPL(azx_init_streams);
1368
1369 void azx_free_streams(struct azx *chip)
1370 {
1371         struct hdac_bus *bus = azx_bus(chip);
1372         struct hdac_stream *s;
1373
1374         while (!list_empty(&bus->stream_list)) {
1375                 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1376                 list_del(&s->list);
1377                 kfree(stream_to_azx_dev(s));
1378         }
1379 }
1380 EXPORT_SYMBOL_GPL(azx_free_streams);