3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
42 #if CONFIG_POST & CFG_POST_UART
43 #if defined(CONFIG_8xx)
45 #elif defined(CONFIG_MPC8260)
46 #include <asm/cpm_8260.h>
48 #error "Apparently a bad configuration, please fix."
56 /* The list of controllers to test */
57 #if defined(CONFIG_MPC823)
58 static int ctlr_list[][2] =
59 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
61 static int ctlr_list[][2] = { };
64 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
67 void (*init) (int index);
68 void (*putc) (int index, const char c);
69 int (*getc) (int index);
72 static char *ctlr_name[2] = { "SMC", "SCC" };
74 static int used_by_uart[2] = { -1, -1 };
76 static int used_by_ether[2] = { -1, -1 };
79 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
80 static int proff_scc[] =
81 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
87 static void smc_init (int smc_index)
89 DECLARE_GLOBAL_DATA_PTR;
91 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
93 volatile immap_t *im = (immap_t *) CFG_IMMR;
95 volatile smc_uart_t *up;
96 volatile cbd_t *tbdf, *rbdf;
97 volatile cpm8xx_t *cp = &(im->im_cpm);
100 /* initialize pointers to SMC */
102 sp = (smc_t *) & (cp->cp_smc[smc_index]);
103 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
105 /* Disable transmitter/receiver.
107 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
111 im->im_siu_conf.sc_sdcr = 1;
113 /* clear error conditions */
115 im->im_sdma.sdma_sdsr = CFG_SDSR;
117 im->im_sdma.sdma_sdsr = 0x83;
120 /* clear SDMA interrupt mask */
122 im->im_sdma.sdma_sdmr = CFG_SDMR;
124 im->im_sdma.sdma_sdmr = 0x00;
127 #if defined(CONFIG_FADS)
130 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
133 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
134 /* Enable Monitor Port Transceiver */
135 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
138 /* Set the physical address of the host memory buffers in
139 * the buffer descriptors.
142 #ifdef CFG_ALLOC_DPRAM
143 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
145 dpaddr = CPM_POST_BASE;
148 /* Allocate space for two buffer descriptors in the DP ram.
149 * For now, this address seems OK, but it may have to
150 * change with newer versions of the firmware.
151 * damm: allocating space after the two buffers for rx/tx data
154 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
155 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
158 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
161 /* Set up the uart parameters in the parameter ram.
163 up->smc_rbase = dpaddr;
164 up->smc_tbase = dpaddr + sizeof (cbd_t);
165 up->smc_rfcr = SMC_EB;
166 up->smc_tfcr = SMC_EB;
168 #if defined(CONFIG_MBX)
169 board_serial_init ();
172 /* Set UART mode, 8 bit, no parity, one stop.
173 * Enable receive and transmit.
174 * Set local loopback mode.
176 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
178 /* Mask all interrupts and remove anything pending.
183 /* Set up the baud rate generator.
185 cp->cp_simode = 0x00000000;
188 (((gd->cpu_clk / 16 / gd->baudrate) -
189 1) << 1) | CPM_BRG_EN;
191 /* Make the first buffer the only buffer.
193 tbdf->cbd_sc |= BD_SC_WRAP;
194 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
196 /* Single character receive.
201 /* Initialize Tx/Rx parameters.
204 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
208 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
210 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
213 /* Enable transmitter/receiver.
215 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
218 static void smc_putc (int smc_index, const char c)
220 volatile cbd_t *tbdf;
222 volatile smc_uart_t *up;
223 volatile immap_t *im = (immap_t *) CFG_IMMR;
224 volatile cpm8xx_t *cpmp = &(im->im_cpm);
226 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
228 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
230 /* Wait for last character to go.
233 buf = (char *) tbdf->cbd_bufaddr;
236 while (tbdf->cbd_sc & BD_SC_READY)
241 tbdf->cbd_datlen = 1;
242 tbdf->cbd_sc |= BD_SC_READY;
245 while (tbdf->cbd_sc & BD_SC_READY)
250 static int smc_getc (int smc_index)
252 volatile cbd_t *rbdf;
253 volatile unsigned char *buf;
254 volatile smc_uart_t *up;
255 volatile immap_t *im = (immap_t *) CFG_IMMR;
256 volatile cpm8xx_t *cpmp = &(im->im_cpm);
260 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
262 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
264 /* Wait for character to show up.
266 buf = (unsigned char *) rbdf->cbd_bufaddr;
268 while (rbdf->cbd_sc & BD_SC_EMPTY);
270 for (i = 100; i > 0; i--) {
271 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
280 rbdf->cbd_sc |= BD_SC_EMPTY;
289 static void scc_init (int scc_index)
291 DECLARE_GLOBAL_DATA_PTR;
293 static int cpm_cr_ch[] = {
300 volatile immap_t *im = (immap_t *) CFG_IMMR;
302 volatile scc_uart_t *up;
303 volatile cbd_t *tbdf, *rbdf;
304 volatile cpm8xx_t *cp = &(im->im_cpm);
307 /* initialize pointers to SCC */
309 sp = (scc_t *) & (cp->cp_scc[scc_index]);
310 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
312 /* Disable transmitter/receiver.
314 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
317 /* Allocate space for two buffer descriptors in the DP ram.
320 #ifdef CFG_ALLOC_DPRAM
321 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
323 dpaddr = CPM_POST_BASE;
328 im->im_siu_conf.sc_sdcr = 0x0001;
330 /* Set the physical address of the host memory buffers in
331 * the buffer descriptors.
334 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
335 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
338 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
341 /* Set up the baud rate generator.
343 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
344 /* no |= needed, since BRG1 is 000 */
347 (((gd->cpu_clk / 16 / gd->baudrate) -
348 1) << 1) | CPM_BRG_EN;
350 /* Set up the uart parameters in the parameter ram.
352 up->scc_genscc.scc_rbase = dpaddr;
353 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
355 /* Initialize Tx/Rx parameters.
357 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
360 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
362 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
365 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
366 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
368 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
369 up->scc_maxidl = 0; /* disable max idle */
370 up->scc_brkcr = 1; /* send one break character on stop TX */
378 up->scc_char1 = 0x8000;
379 up->scc_char2 = 0x8000;
380 up->scc_char3 = 0x8000;
381 up->scc_char4 = 0x8000;
382 up->scc_char5 = 0x8000;
383 up->scc_char6 = 0x8000;
384 up->scc_char7 = 0x8000;
385 up->scc_char8 = 0x8000;
386 up->scc_rccm = 0xc0ff;
388 /* Set low latency / small fifo.
390 sp->scc_gsmrh = SCC_GSMRH_RFW;
394 sp->scc_gsmrl &= ~0xF;
395 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
397 /* Set local loopback mode.
399 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
400 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
402 /* Set clock divider 16 on Tx and Rx
404 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
406 sp->scc_psmr |= SCU_PSMR_CL;
408 /* Mask all interrupts and remove anything pending.
411 sp->scc_scce = 0xffff;
412 sp->scc_dsr = 0x7e7e;
413 sp->scc_psmr = 0x3000;
415 /* Make the first buffer the only buffer.
417 tbdf->cbd_sc |= BD_SC_WRAP;
418 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
420 /* Enable transmitter/receiver.
422 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
425 static void scc_putc (int scc_index, const char c)
427 volatile cbd_t *tbdf;
429 volatile scc_uart_t *up;
430 volatile immap_t *im = (immap_t *) CFG_IMMR;
431 volatile cpm8xx_t *cpmp = &(im->im_cpm);
433 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
435 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
437 /* Wait for last character to go.
440 buf = (char *) tbdf->cbd_bufaddr;
443 while (tbdf->cbd_sc & BD_SC_READY)
448 tbdf->cbd_datlen = 1;
449 tbdf->cbd_sc |= BD_SC_READY;
452 while (tbdf->cbd_sc & BD_SC_READY)
457 static int scc_getc (int scc_index)
459 volatile cbd_t *rbdf;
460 volatile unsigned char *buf;
461 volatile scc_uart_t *up;
462 volatile immap_t *im = (immap_t *) CFG_IMMR;
463 volatile cpm8xx_t *cpmp = &(im->im_cpm);
467 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
469 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
471 /* Wait for character to show up.
473 buf = (unsigned char *) rbdf->cbd_bufaddr;
475 while (rbdf->cbd_sc & BD_SC_EMPTY);
477 for (i = 100; i > 0; i--) {
478 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
487 rbdf->cbd_sc |= BD_SC_EMPTY;
496 static int test_ctlr (int ctlr, int index)
499 char test_str[] = "*** UART Test String ***\r\n";
502 #if !defined(CONFIG_8xx_CONS_NONE)
503 if (used_by_uart[ctlr] == index) {
504 while (ctlr_proc[ctlr].getc (index) != -1);
508 ctlr_proc[ctlr].init (index);
510 for (i = 0; i < sizeof (test_str) - 1; i++) {
511 ctlr_proc[ctlr].putc (index, test_str[i]);
512 if (ctlr_proc[ctlr].getc (index) != test_str[i])
520 #if !defined(CONFIG_8xx_CONS_NONE)
521 if (used_by_uart[ctlr] == index) {
526 #if defined(SCC_ENET)
527 if (used_by_ether[ctlr] == index) {
528 DECLARE_GLOBAL_DATA_PTR;
535 post_log ("uart %s%d test failed\n",
536 ctlr_name[ctlr], index + 1);
542 int uart_post_test (int flags)
547 #if defined(CONFIG_8xx_CONS_SMC1)
548 used_by_uart[CTLR_SMC] = 0;
549 #elif defined(CONFIG_8xx_CONS_SMC2)
550 used_by_uart[CTLR_SMC] = 1;
551 #elif defined(CONFIG_8xx_CONS_SCC1)
552 used_by_uart[CTLR_SCC] = 0;
553 #elif defined(CONFIG_8xx_CONS_SCC2)
554 used_by_uart[CTLR_SCC] = 1;
555 #elif defined(CONFIG_8xx_CONS_SCC3)
556 used_by_uart[CTLR_SCC] = 2;
557 #elif defined(CONFIG_8xx_CONS_SCC4)
558 used_by_uart[CTLR_SCC] = 3;
561 #if defined(SCC_ENET)
562 used_by_ether[CTLR_SCC] = SCC_ENET;
565 ctlr_proc[CTLR_SMC].init = smc_init;
566 ctlr_proc[CTLR_SMC].putc = smc_putc;
567 ctlr_proc[CTLR_SMC].getc = smc_getc;
569 ctlr_proc[CTLR_SCC].init = scc_init;
570 ctlr_proc[CTLR_SCC].putc = scc_putc;
571 ctlr_proc[CTLR_SCC].getc = scc_getc;
573 for (i = 0; i < CTRL_LIST_SIZE; i++) {
574 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
582 #endif /* CONFIG_POST & CFG_POST_UART */
584 #endif /* CONFIG_POST */