3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
42 #if defined(CONFIG_8xx)
44 #elif defined(CONFIG_MPC8260)
45 #include <asm/cpm_8260.h>
47 #error "Apparently a bad configuration, please fix."
52 #if CONFIG_POST & CFG_POST_UART
57 /* The list of controllers to test */
58 #if defined(CONFIG_MPC823)
59 static int ctlr_list[][2] =
60 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
62 static int ctlr_list[][2] = { };
65 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
68 void (*init) (int index);
69 void (*putc) (int index, const char c);
70 int (*getc) (int index);
73 static char *ctlr_name[2] = { "SMC", "SCC" };
75 static int used_by_uart[2] = { -1, -1 };
77 static int used_by_ether[2] = { -1, -1 };
80 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
81 static int proff_scc[] =
82 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
88 static void smc_init (int smc_index)
90 DECLARE_GLOBAL_DATA_PTR;
92 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
94 volatile immap_t *im = (immap_t *) CFG_IMMR;
96 volatile smc_uart_t *up;
97 volatile cbd_t *tbdf, *rbdf;
98 volatile cpm8xx_t *cp = &(im->im_cpm);
101 /* initialize pointers to SMC */
103 sp = (smc_t *) & (cp->cp_smc[smc_index]);
104 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
106 /* Disable transmitter/receiver.
108 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
112 im->im_siu_conf.sc_sdcr = 1;
114 /* clear error conditions */
116 im->im_sdma.sdma_sdsr = CFG_SDSR;
118 im->im_sdma.sdma_sdsr = 0x83;
121 /* clear SDMA interrupt mask */
123 im->im_sdma.sdma_sdmr = CFG_SDMR;
125 im->im_sdma.sdma_sdmr = 0x00;
128 #if defined(CONFIG_FADS)
131 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
134 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
135 /* Enable Monitor Port Transceiver */
136 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
139 /* Set the physical address of the host memory buffers in
140 * the buffer descriptors.
143 #ifdef CFG_ALLOC_DPRAM
144 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
146 dpaddr = CPM_POST_BASE;
149 /* Allocate space for two buffer descriptors in the DP ram.
150 * For now, this address seems OK, but it may have to
151 * change with newer versions of the firmware.
152 * damm: allocating space after the two buffers for rx/tx data
155 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
156 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
159 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
162 /* Set up the uart parameters in the parameter ram.
164 up->smc_rbase = dpaddr;
165 up->smc_tbase = dpaddr + sizeof (cbd_t);
166 up->smc_rfcr = SMC_EB;
167 up->smc_tfcr = SMC_EB;
169 #if defined(CONFIG_MBX)
170 board_serial_init ();
173 /* Set UART mode, 8 bit, no parity, one stop.
174 * Enable receive and transmit.
175 * Set local loopback mode.
177 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
179 /* Mask all interrupts and remove anything pending.
184 /* Set up the baud rate generator.
186 cp->cp_simode = 0x00000000;
189 (((gd->cpu_clk / 16 / gd->baudrate) -
190 1) << 1) | CPM_BRG_EN;
192 /* Make the first buffer the only buffer.
194 tbdf->cbd_sc |= BD_SC_WRAP;
195 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
197 /* Single character receive.
202 /* Initialize Tx/Rx parameters.
205 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
209 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
211 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
214 /* Enable transmitter/receiver.
216 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
219 static void smc_putc (int smc_index, const char c)
221 volatile cbd_t *tbdf;
223 volatile smc_uart_t *up;
224 volatile immap_t *im = (immap_t *) CFG_IMMR;
225 volatile cpm8xx_t *cpmp = &(im->im_cpm);
227 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
229 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
231 /* Wait for last character to go.
234 buf = (char *) tbdf->cbd_bufaddr;
237 while (tbdf->cbd_sc & BD_SC_READY)
242 tbdf->cbd_datlen = 1;
243 tbdf->cbd_sc |= BD_SC_READY;
246 while (tbdf->cbd_sc & BD_SC_READY)
251 static int smc_getc (int smc_index)
253 volatile cbd_t *rbdf;
254 volatile unsigned char *buf;
255 volatile smc_uart_t *up;
256 volatile immap_t *im = (immap_t *) CFG_IMMR;
257 volatile cpm8xx_t *cpmp = &(im->im_cpm);
261 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
263 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
265 /* Wait for character to show up.
267 buf = (unsigned char *) rbdf->cbd_bufaddr;
269 while (rbdf->cbd_sc & BD_SC_EMPTY);
271 for (i = 100; i > 0; i--) {
272 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
281 rbdf->cbd_sc |= BD_SC_EMPTY;
290 static void scc_init (int scc_index)
292 DECLARE_GLOBAL_DATA_PTR;
294 static int cpm_cr_ch[] = {
301 volatile immap_t *im = (immap_t *) CFG_IMMR;
303 volatile scc_uart_t *up;
304 volatile cbd_t *tbdf, *rbdf;
305 volatile cpm8xx_t *cp = &(im->im_cpm);
308 /* initialize pointers to SCC */
310 sp = (scc_t *) & (cp->cp_scc[scc_index]);
311 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
313 /* Disable transmitter/receiver.
315 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
318 /* Allocate space for two buffer descriptors in the DP ram.
321 #ifdef CFG_ALLOC_DPRAM
322 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
324 dpaddr = CPM_POST_BASE;
329 im->im_siu_conf.sc_sdcr = 0x0001;
331 /* Set the physical address of the host memory buffers in
332 * the buffer descriptors.
335 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
336 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
339 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
342 /* Set up the baud rate generator.
344 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
345 /* no |= needed, since BRG1 is 000 */
348 (((gd->cpu_clk / 16 / gd->baudrate) -
349 1) << 1) | CPM_BRG_EN;
351 /* Set up the uart parameters in the parameter ram.
353 up->scc_genscc.scc_rbase = dpaddr;
354 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
356 /* Initialize Tx/Rx parameters.
358 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
361 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
363 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
366 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
367 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
369 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
370 up->scc_maxidl = 0; /* disable max idle */
371 up->scc_brkcr = 1; /* send one break character on stop TX */
379 up->scc_char1 = 0x8000;
380 up->scc_char2 = 0x8000;
381 up->scc_char3 = 0x8000;
382 up->scc_char4 = 0x8000;
383 up->scc_char5 = 0x8000;
384 up->scc_char6 = 0x8000;
385 up->scc_char7 = 0x8000;
386 up->scc_char8 = 0x8000;
387 up->scc_rccm = 0xc0ff;
389 /* Set low latency / small fifo.
391 sp->scc_gsmrh = SCC_GSMRH_RFW;
395 sp->scc_gsmrl &= ~0xF;
396 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
398 /* Set local loopback mode.
400 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
401 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
403 /* Set clock divider 16 on Tx and Rx
405 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
407 sp->scc_psmr |= SCU_PSMR_CL;
409 /* Mask all interrupts and remove anything pending.
412 sp->scc_scce = 0xffff;
413 sp->scc_dsr = 0x7e7e;
414 sp->scc_psmr = 0x3000;
416 /* Make the first buffer the only buffer.
418 tbdf->cbd_sc |= BD_SC_WRAP;
419 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
421 /* Enable transmitter/receiver.
423 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
426 static void scc_putc (int scc_index, const char c)
428 volatile cbd_t *tbdf;
430 volatile scc_uart_t *up;
431 volatile immap_t *im = (immap_t *) CFG_IMMR;
432 volatile cpm8xx_t *cpmp = &(im->im_cpm);
434 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
436 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
438 /* Wait for last character to go.
441 buf = (char *) tbdf->cbd_bufaddr;
444 while (tbdf->cbd_sc & BD_SC_READY)
449 tbdf->cbd_datlen = 1;
450 tbdf->cbd_sc |= BD_SC_READY;
453 while (tbdf->cbd_sc & BD_SC_READY)
458 static int scc_getc (int scc_index)
460 volatile cbd_t *rbdf;
461 volatile unsigned char *buf;
462 volatile scc_uart_t *up;
463 volatile immap_t *im = (immap_t *) CFG_IMMR;
464 volatile cpm8xx_t *cpmp = &(im->im_cpm);
468 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
470 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
472 /* Wait for character to show up.
474 buf = (unsigned char *) rbdf->cbd_bufaddr;
476 while (rbdf->cbd_sc & BD_SC_EMPTY);
478 for (i = 100; i > 0; i--) {
479 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
488 rbdf->cbd_sc |= BD_SC_EMPTY;
497 static int test_ctlr (int ctlr, int index)
500 char test_str[] = "*** UART Test String ***\r\n";
503 #if !defined(CONFIG_8xx_CONS_NONE)
504 if (used_by_uart[ctlr] == index) {
505 while (ctlr_proc[ctlr].getc (index) != -1);
509 ctlr_proc[ctlr].init (index);
511 for (i = 0; i < sizeof (test_str) - 1; i++) {
512 ctlr_proc[ctlr].putc (index, test_str[i]);
513 if (ctlr_proc[ctlr].getc (index) != test_str[i])
521 #if !defined(CONFIG_8xx_CONS_NONE)
522 if (used_by_uart[ctlr] == index) {
527 #if defined(SCC_ENET)
528 if (used_by_ether[ctlr] == index) {
529 DECLARE_GLOBAL_DATA_PTR;
536 post_log ("uart %s%d test failed\n",
537 ctlr_name[ctlr], index + 1);
543 int uart_post_test (int flags)
548 #if defined(CONFIG_8xx_CONS_SMC1)
549 used_by_uart[CTLR_SMC] = 0;
550 #elif defined(CONFIG_8xx_CONS_SMC2)
551 used_by_uart[CTLR_SMC] = 1;
552 #elif defined(CONFIG_8xx_CONS_SCC1)
553 used_by_uart[CTLR_SCC] = 0;
554 #elif defined(CONFIG_8xx_CONS_SCC2)
555 used_by_uart[CTLR_SCC] = 1;
556 #elif defined(CONFIG_8xx_CONS_SCC3)
557 used_by_uart[CTLR_SCC] = 2;
558 #elif defined(CONFIG_8xx_CONS_SCC4)
559 used_by_uart[CTLR_SCC] = 3;
562 #if defined(SCC_ENET)
563 used_by_ether[CTLR_SCC] = SCC_ENET;
566 ctlr_proc[CTLR_SMC].init = smc_init;
567 ctlr_proc[CTLR_SMC].putc = smc_putc;
568 ctlr_proc[CTLR_SMC].getc = smc_getc;
570 ctlr_proc[CTLR_SCC].init = scc_init;
571 ctlr_proc[CTLR_SCC].putc = scc_putc;
572 ctlr_proc[CTLR_SCC].getc = scc_getc;
574 for (i = 0; i < CTRL_LIST_SIZE; i++) {
575 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
583 #endif /* CONFIG_POST & CFG_POST_UART */
585 #endif /* CONFIG_POST */