3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
42 #if CONFIG_POST & CFG_POST_UART
43 #if defined(CONFIG_8xx)
45 #elif defined(CONFIG_MPC8260)
46 #include <asm/cpm_8260.h>
48 #error "Apparently a bad configuration, please fix."
56 /* The list of controllers to test */
57 #if defined(CONFIG_MPC823)
58 static int ctlr_list[][2] =
59 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
61 static int ctlr_list[][2] = { };
64 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
67 void (*init) (int index);
68 void (*putc) (int index, const char c);
69 int (*getc) (int index);
72 static char *ctlr_name[2] = { "SMC", "SCC" };
74 static int used_by_uart[2] = { -1, -1 };
76 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
77 static int proff_scc[] =
78 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
84 static void smc_init (int smc_index)
86 DECLARE_GLOBAL_DATA_PTR;
88 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
90 volatile immap_t *im = (immap_t *) CFG_IMMR;
92 volatile smc_uart_t *up;
93 volatile cbd_t *tbdf, *rbdf;
94 volatile cpm8xx_t *cp = &(im->im_cpm);
97 /* initialize pointers to SMC */
99 sp = (smc_t *) & (cp->cp_smc[smc_index]);
100 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
102 /* Disable transmitter/receiver.
104 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
108 im->im_siu_conf.sc_sdcr = 1;
110 /* clear error conditions */
112 im->im_sdma.sdma_sdsr = CFG_SDSR;
114 im->im_sdma.sdma_sdsr = 0x83;
117 /* clear SDMA interrupt mask */
119 im->im_sdma.sdma_sdmr = CFG_SDMR;
121 im->im_sdma.sdma_sdmr = 0x00;
124 #if defined(CONFIG_FADS)
127 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
130 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
131 /* Enable Monitor Port Transceiver */
132 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
135 /* Set the physical address of the host memory buffers in
136 * the buffer descriptors.
139 #ifdef CFG_ALLOC_DPRAM
140 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
142 dpaddr = CPM_POST_BASE;
145 /* Allocate space for two buffer descriptors in the DP ram.
146 * For now, this address seems OK, but it may have to
147 * change with newer versions of the firmware.
148 * damm: allocating space after the two buffers for rx/tx data
151 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
152 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
155 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
158 /* Set up the uart parameters in the parameter ram.
160 up->smc_rbase = dpaddr;
161 up->smc_tbase = dpaddr + sizeof (cbd_t);
162 up->smc_rfcr = SMC_EB;
163 up->smc_tfcr = SMC_EB;
165 #if defined(CONFIG_MBX)
166 board_serial_init ();
169 /* Set UART mode, 8 bit, no parity, one stop.
170 * Enable receive and transmit.
171 * Set local loopback mode.
173 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
175 /* Mask all interrupts and remove anything pending.
180 /* Set up the baud rate generator.
182 cp->cp_simode = 0x00000000;
185 (((gd->cpu_clk / 16 / gd->baudrate) -
186 1) << 1) | CPM_BRG_EN;
188 /* Make the first buffer the only buffer.
190 tbdf->cbd_sc |= BD_SC_WRAP;
191 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
193 /* Single character receive.
198 /* Initialize Tx/Rx parameters.
201 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
205 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
207 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
210 /* Enable transmitter/receiver.
212 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
215 static void smc_putc (int smc_index, const char c)
217 volatile cbd_t *tbdf;
219 volatile smc_uart_t *up;
220 volatile immap_t *im = (immap_t *) CFG_IMMR;
221 volatile cpm8xx_t *cpmp = &(im->im_cpm);
223 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
225 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
227 /* Wait for last character to go.
230 buf = (char *) tbdf->cbd_bufaddr;
233 while (tbdf->cbd_sc & BD_SC_READY)
238 tbdf->cbd_datlen = 1;
239 tbdf->cbd_sc |= BD_SC_READY;
242 while (tbdf->cbd_sc & BD_SC_READY)
247 static int smc_getc (int smc_index)
249 volatile cbd_t *rbdf;
250 volatile unsigned char *buf;
251 volatile smc_uart_t *up;
252 volatile immap_t *im = (immap_t *) CFG_IMMR;
253 volatile cpm8xx_t *cpmp = &(im->im_cpm);
257 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
259 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
261 /* Wait for character to show up.
263 buf = (unsigned char *) rbdf->cbd_bufaddr;
265 while (rbdf->cbd_sc & BD_SC_EMPTY);
267 for (i = 100; i > 0; i--) {
268 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
277 rbdf->cbd_sc |= BD_SC_EMPTY;
286 static void scc_init (int scc_index)
288 DECLARE_GLOBAL_DATA_PTR;
290 static int cpm_cr_ch[] = {
297 volatile immap_t *im = (immap_t *) CFG_IMMR;
299 volatile scc_uart_t *up;
300 volatile cbd_t *tbdf, *rbdf;
301 volatile cpm8xx_t *cp = &(im->im_cpm);
304 /* initialize pointers to SCC */
306 sp = (scc_t *) & (cp->cp_scc[scc_index]);
307 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
309 /* Disable transmitter/receiver.
311 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
314 /* Allocate space for two buffer descriptors in the DP ram.
317 #ifdef CFG_ALLOC_DPRAM
318 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
320 dpaddr = CPM_POST_BASE;
325 im->im_siu_conf.sc_sdcr = 0x0001;
327 /* Set the physical address of the host memory buffers in
328 * the buffer descriptors.
331 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
332 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
335 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
338 /* Set up the baud rate generator.
340 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
341 /* no |= needed, since BRG1 is 000 */
344 (((gd->cpu_clk / 16 / gd->baudrate) -
345 1) << 1) | CPM_BRG_EN;
347 /* Set up the uart parameters in the parameter ram.
349 up->scc_genscc.scc_rbase = dpaddr;
350 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
352 /* Initialize Tx/Rx parameters.
354 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
357 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
359 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
362 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
363 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
365 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
366 up->scc_maxidl = 0; /* disable max idle */
367 up->scc_brkcr = 1; /* send one break character on stop TX */
375 up->scc_char1 = 0x8000;
376 up->scc_char2 = 0x8000;
377 up->scc_char3 = 0x8000;
378 up->scc_char4 = 0x8000;
379 up->scc_char5 = 0x8000;
380 up->scc_char6 = 0x8000;
381 up->scc_char7 = 0x8000;
382 up->scc_char8 = 0x8000;
383 up->scc_rccm = 0xc0ff;
385 /* Set low latency / small fifo.
387 sp->scc_gsmrh = SCC_GSMRH_RFW;
391 sp->scc_gsmrl &= ~0xF;
392 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
394 /* Set local loopback mode.
396 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
397 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
399 /* Set clock divider 16 on Tx and Rx
401 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
403 sp->scc_psmr |= SCU_PSMR_CL;
405 /* Mask all interrupts and remove anything pending.
408 sp->scc_scce = 0xffff;
409 sp->scc_dsr = 0x7e7e;
410 sp->scc_psmr = 0x3000;
412 /* Make the first buffer the only buffer.
414 tbdf->cbd_sc |= BD_SC_WRAP;
415 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
417 /* Enable transmitter/receiver.
419 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
422 static void scc_putc (int scc_index, const char c)
424 volatile cbd_t *tbdf;
426 volatile scc_uart_t *up;
427 volatile immap_t *im = (immap_t *) CFG_IMMR;
428 volatile cpm8xx_t *cpmp = &(im->im_cpm);
430 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
432 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
434 /* Wait for last character to go.
437 buf = (char *) tbdf->cbd_bufaddr;
440 while (tbdf->cbd_sc & BD_SC_READY)
445 tbdf->cbd_datlen = 1;
446 tbdf->cbd_sc |= BD_SC_READY;
449 while (tbdf->cbd_sc & BD_SC_READY)
454 static int scc_getc (int scc_index)
456 volatile cbd_t *rbdf;
457 volatile unsigned char *buf;
458 volatile scc_uart_t *up;
459 volatile immap_t *im = (immap_t *) CFG_IMMR;
460 volatile cpm8xx_t *cpmp = &(im->im_cpm);
464 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
466 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
468 /* Wait for character to show up.
470 buf = (unsigned char *) rbdf->cbd_bufaddr;
472 while (rbdf->cbd_sc & BD_SC_EMPTY);
474 for (i = 100; i > 0; i--) {
475 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
484 rbdf->cbd_sc |= BD_SC_EMPTY;
493 static int test_ctlr (int ctlr, int index)
496 char test_str[] = "*** UART Test String ***\r\n";
499 #if !defined(CONFIG_8xx_CONS_NONE)
500 if (used_by_uart[ctlr] == index) {
501 while (ctlr_proc[ctlr].getc (index) != -1);
505 ctlr_proc[ctlr].init (index);
507 for (i = 0; i < sizeof (test_str) - 1; i++) {
508 ctlr_proc[ctlr].putc (index, test_str[i]);
509 if (ctlr_proc[ctlr].getc (index) != test_str[i])
517 #if !defined(CONFIG_8xx_CONS_NONE)
518 if (used_by_uart[ctlr] == index) {
524 post_log ("uart %s%d test failed\n",
525 ctlr_name[ctlr], index + 1);
531 int uart_post_test (int flags)
536 #if defined(CONFIG_8xx_CONS_SMC1)
537 used_by_uart[CTLR_SMC] = 0;
538 #elif defined(CONFIG_8xx_CONS_SMC2)
539 used_by_uart[CTLR_SMC] = 1;
540 #elif defined(CONFIG_8xx_CONS_SCC1)
541 used_by_uart[CTLR_SCC] = 0;
542 #elif defined(CONFIG_8xx_CONS_SCC2)
543 used_by_uart[CTLR_SCC] = 1;
544 #elif defined(CONFIG_8xx_CONS_SCC3)
545 used_by_uart[CTLR_SCC] = 2;
546 #elif defined(CONFIG_8xx_CONS_SCC4)
547 used_by_uart[CTLR_SCC] = 3;
550 ctlr_proc[CTLR_SMC].init = smc_init;
551 ctlr_proc[CTLR_SMC].putc = smc_putc;
552 ctlr_proc[CTLR_SMC].getc = smc_getc;
554 ctlr_proc[CTLR_SCC].init = scc_init;
555 ctlr_proc[CTLR_SCC].putc = scc_putc;
556 ctlr_proc[CTLR_SCC].getc = scc_getc;
558 for (i = 0; i < CTRL_LIST_SIZE; i++) {
559 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
567 #endif /* CONFIG_POST & CFG_POST_UART */
569 #endif /* CONFIG_POST */