1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u)
13 * All operations are performed on a 16-byte array. The array
14 * is 4-byte aligned. The base register points to offset 8.
15 * The immediate offset (index register) ranges in [-8 ... +7].
16 * The test cases are composed so that they do not
17 * cause alignment exceptions.
18 * The test contains a pre-built table describing all test cases.
19 * The table entry contains:
20 * the instruction opcode, the value of the index register and
21 * the value of the source register. After executing the
22 * instruction, the test verifies the contents of the array
23 * and the value of the base register (it must change for "store
24 * with update" instructions).
30 #if CONFIG_POST & CONFIG_SYS_POST_CPU
32 extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3);
33 extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2);
35 static struct cpu_post_store_s
43 } cpu_post_store_table[] =
142 static unsigned int cpu_post_store_size = ARRAY_SIZE(cpu_post_store_table);
144 int cpu_post_test_store (void)
148 int flag = disable_interrupts();
150 for (i = 0; i < cpu_post_store_size && ret == 0; i++)
152 struct cpu_post_store_s *test = cpu_post_store_table + i;
154 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
155 ulong base0 = (ulong) (data + 8);
162 ASM_12(test->cmd, 5, 3, 4),
166 cpu_post_exec_12w (code, &base, test->offset, test->value);
172 ASM_11I(test->cmd, 4, 3, test->offset),
176 cpu_post_exec_11w (code, &base, test->value);
182 ret = base == base0 + test->offset ? 0 : -1;
184 ret = base == base0 ? 0 : -1;
192 ret = *(uchar *)(base0 + test->offset) == test->value ?
196 ret = *(ushort *)(base0 + test->offset) == test->value ?
200 ret = *(ulong *)(base0 + test->offset) == test->value ?
208 post_log ("Error at store test %d !\n", i);