1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Logic instructions: andi., andis.
13 * The test contains a pre-built table of instructions, operands and
14 * expected results. For each table entry, the test will cyclically use
15 * different sets of operand registers and result registers.
21 #if CONFIG_POST & CONFIG_SYS_POST_CPU
23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
24 extern ulong cpu_post_makecr (long v);
26 static struct cpu_post_andi_s
32 } cpu_post_andi_table[] =
47 static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table);
49 int cpu_post_test_andi (void)
53 int flag = disable_interrupts();
55 for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
57 struct cpu_post_andi_s *test = cpu_post_andi_table + i;
59 for (reg = 0; reg < 32 && ret == 0; reg++)
61 unsigned int reg0 = (reg + 0) % 32;
62 unsigned int reg1 = (reg + 1) % 32;
63 unsigned int stk = reg < 16 ? 31 : 15;
64 unsigned long codecr[] =
67 ASM_ADDI(stk, 1, -16),
69 ASM_STW(reg0, stk, 4),
70 ASM_STW(reg1, stk, 0),
71 ASM_LWZ(reg0, stk, 8),
72 ASM_11IX(test->cmd, reg1, reg0, test->op2),
73 ASM_STW(reg1, stk, 8),
74 ASM_LWZ(reg1, stk, 0),
75 ASM_LWZ(reg0, stk, 4),
84 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
86 ret = res == test->res &&
87 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
91 post_log ("Error at andi test %d !\n", i);