3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The controllers are configured to loopback mode and several
30 * characters are transmitted.
37 #if CONFIG_POST & CFG_POST_UART
39 #include <asm/processor.h>
42 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
43 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
44 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
45 #define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
47 #define CR0_MASK 0xdfffffff
48 #define CR0_EXTCLK_ENA 0x00800000
49 #define CR0_UDIV_POS 0
50 #define UDIV_SUBTRACT 0
51 #define UART0_SDR sdr_uart0
52 #define UART1_SDR sdr_uart1
53 #define UART2_SDR sdr_uart2
54 #define UART3_SDR sdr_uart3
55 #define MFREG(a, d) mfsdr(a, d)
56 #define MTREG(a, d) mtsdr(a, d)
74 #define asyncLSRDataReady1 0x01
75 #define asyncLSROverrunError1 0x02
76 #define asyncLSRParityError1 0x04
77 #define asyncLSRFramingError1 0x08
78 #define asyncLSRBreakInterrupt1 0x10
79 #define asyncLSRTxHoldEmpty1 0x20
80 #define asyncLSRTxShiftEmpty1 0x40
81 #define asyncLSRRxFifoError1 0x80
83 DECLARE_GLOBAL_DATA_PTR;
85 static int uart_post_init (unsigned long dev_base)
91 #ifdef CFG_EXT_SERIAL_CLOCK
96 for (i = 0; i < 3500; i++) {
97 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
101 MFREG(UART0_SDR, reg);
104 #ifdef CFG_EXT_SERIAL_CLOCK
105 reg |= CR0_EXTCLK_ENA;
107 tmp = gd->baudrate * 16;
108 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
110 /* For 440, the cpu clock is on divider chain A, UART on divider
111 * chain B ... so cpu clock is irrelevant. Get the "optimized"
112 * values that are subject to the 1/2 opb clock constraint
114 serial_divs (gd->baudrate, &udiv, &bdiv);
117 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
120 * Configure input clock to baudrate generator for all
121 * available serial ports here
123 MTREG(UART0_SDR, reg);
124 #if defined(UART1_SDR)
125 MTREG(UART1_SDR, reg);
127 #if defined(UART2_SDR)
128 MTREG(UART2_SDR, reg);
130 #if defined(UART3_SDR)
131 MTREG(UART3_SDR, reg);
134 out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
135 out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
136 out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
137 out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
138 out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
139 out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
140 val = in8(dev_base + UART_LSR); /* clear line status */
141 val = in8(dev_base + UART_RBR); /* read receive buffer */
142 out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
143 out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
148 static void uart_post_putc (unsigned long dev_base, char c)
152 out8 (dev_base + UART_THR, c); /* put character out */
154 /* Wait for transfer completion */
155 for (i = 0; i < 3500; i++) {
156 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
162 static int uart_post_getc (unsigned long dev_base)
166 /* Wait for character available */
167 for (i = 0; i < 3500; i++) {
168 if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
172 return 0xff & in8 (dev_base + UART_RBR);
175 static int test_ctlr (unsigned long dev_base, int index)
178 char test_str[] = "*** UART Test String ***\r\n";
181 uart_post_init (dev_base);
183 for (i = 0; i < sizeof (test_str) - 1; i++) {
184 uart_post_putc (dev_base, test_str[i]);
185 if (uart_post_getc (dev_base) != test_str[i])
191 post_log ("uart%d test failed\n", index);
196 int uart_post_test (int flags)
199 static unsigned long base[] = {
200 UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
203 for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
204 if (test_ctlr (base[i], i))
207 serial_reinit_all ();
212 #endif /* CONFIG_POST & CFG_POST_UART */
214 #endif /* CONFIG_POST */