3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <ppc_asm.tmpl>
15 #include <asm/cache.h>
18 #if CONFIG_POST & CONFIG_SYS_POST_CACHE
23 * All 44x variants deal with cache management differently
24 * because they have the address translation always enabled.
25 * The 40x ppc's don't use address translation in U-Boot at all,
26 * so we have to distinguish here between 40x and 44x.
29 /* void cache_post_disable (int tlb)
33 ori r0, r0, TLB_WORD2_I_ENABLE@l
39 /* void cache_post_wt (int tlb)
43 ori r0, r0, TLB_WORD2_W_ENABLE@l
44 andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
50 /* void cache_post_wb (int tlb)
54 andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
55 andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
61 /* void cache_post_disable (int tlb)
71 /* void cache_post_wt (int tlb)
84 /* void cache_post_wb (int tlb)
98 /* void cache_post_dinvalidate (void *p, int size)
100 cache_post_dinvalidate:
102 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
103 subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
104 bgt cache_post_dinvalidate
108 /* void cache_post_dstore (void *p, int size)
112 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
113 subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
114 bgt cache_post_dstore
118 /* void cache_post_dtouch (void *p, int size)
122 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
123 subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
124 bgt cache_post_dtouch
128 /* void cache_post_iinvalidate (void)
130 cache_post_iinvalidate:
135 /* void cache_post_memset (void *p, int val, int size)
145 /* int cache_post_check (void *p, int size)
161 #define CACHE_POST_DISABLE() \
163 bl cache_post_disable
165 #define CACHE_POST_WT() \
169 #define CACHE_POST_WB() \
173 #define CACHE_POST_DINVALIDATE() \
176 bl cache_post_dinvalidate
178 #define CACHE_POST_DFLUSH() \
183 #define CACHE_POST_DSTORE() \
188 #define CACHE_POST_DTOUCH() \
193 #define CACHE_POST_IINVALIDATE() \
194 bl cache_post_iinvalidate
196 #define CACHE_POST_MEMSET(val) \
202 #define CACHE_POST_CHECK() \
205 bl cache_post_check; \
209 * Write and read 0xff pattern with caching enabled.
211 .global cache_post_test1
216 mr r12, r5 /* size */
219 CACHE_POST_DINVALIDATE()
221 /* Write the negative pattern to the test area */
222 CACHE_POST_MEMSET(0xff)
224 /* Read the test area */
227 CACHE_POST_DINVALIDATE()
235 * Write zeroes with caching enabled.
236 * Write 0xff pattern with caching disabled.
237 * Read 0xff pattern with caching enabled.
239 .global cache_post_test2
244 mr r12, r5 /* size */
247 CACHE_POST_DINVALIDATE()
249 /* Write the zero pattern to the test area */
252 CACHE_POST_DINVALIDATE()
255 /* Write the negative pattern to the test area */
256 CACHE_POST_MEMSET(0xff)
260 /* Read the test area */
263 CACHE_POST_DINVALIDATE()
271 * Write-through mode test.
272 * Write zeroes, store the cache, write 0xff pattern.
273 * Invalidate the cache.
274 * Check that 0xff pattern is read.
276 .global cache_post_test3
281 mr r12, r5 /* size */
284 CACHE_POST_DINVALIDATE()
286 /* Cache the test area */
289 /* Write the zero pattern to the test area */
294 /* Write the negative pattern to the test area */
295 CACHE_POST_MEMSET(0xff)
297 CACHE_POST_DINVALIDATE()
300 /* Read the test area */
308 * Write-back mode test.
309 * Write 0xff pattern, store the cache, write zeroes.
310 * Invalidate the cache.
311 * Check that 0xff pattern is read.
313 .global cache_post_test4
318 mr r12, r5 /* size */
321 CACHE_POST_DINVALIDATE()
323 /* Cache the test area */
326 /* Write the negative pattern to the test area */
327 CACHE_POST_MEMSET(0xff)
331 /* Write the zero pattern to the test area */
334 CACHE_POST_DINVALIDATE()
337 /* Read the test area */
345 * Load the test instructions into the instruction cache.
346 * Replace the test instructions.
347 * Check that the original instructions are executed.
349 .global cache_post_test5
354 mr r12, r5 /* size */
357 CACHE_POST_IINVALIDATE()
359 /* Compute r13 = cache_post_test_inst */
360 bl cache_post_test5_reloc
361 cache_post_test5_reloc:
363 lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
364 ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
367 /* Copy the test instructions to the test area */
374 /* Invalidate the cache line */
379 /* Execute the test instructions */
383 /* Replace the test instruction */
388 /* Do not invalidate the cache line */
391 /* Execute the test instructions */
396 CACHE_POST_IINVALIDATE()
397 CACHE_POST_DINVALIDATE()
405 * Load the test instructions into the instruction cache.
406 * Replace the test instructions and invalidate the cache.
407 * Check that the replaced instructions are executed.
409 .global cache_post_test6
414 mr r12, r5 /* size */
417 CACHE_POST_IINVALIDATE()
419 /* Compute r13 = cache_post_test_inst */
420 bl cache_post_test6_reloc
421 cache_post_test6_reloc:
423 lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
424 ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
427 /* Copy the test instructions to the test area */
434 /* Invalidate the cache line */
439 /* Execute the test instructions */
443 /* Replace the test instruction */
448 /* Invalidate the cache line */
453 /* Execute the test instructions */
458 CACHE_POST_IINVALIDATE()
459 CACHE_POST_DINVALIDATE()
466 /* Test instructions.
468 cache_post_test_inst:
473 #endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */