3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * This test verifies the CPU data and instruction cache using
31 * several test scenarios.
36 #if CONFIG_POST & CONFIG_SYS_POST_CACHE
41 #define CACHE_POST_SIZE 1024
43 int cache_post_test1 (int tlb, void *p, int size);
44 int cache_post_test2 (int tlb, void *p, int size);
45 int cache_post_test3 (int tlb, void *p, int size);
46 int cache_post_test4 (int tlb, void *p, int size);
47 int cache_post_test5 (int tlb, void *p, int size);
48 int cache_post_test6 (int tlb, void *p, int size);
51 static unsigned char testarea[CACHE_POST_SIZE]
52 __attribute__((__aligned__(CACHE_POST_SIZE)));
55 int cache_post_test (int flags)
57 void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
60 int tlb = -1; /* index to the victim TLB entry */
63 * All 44x variants deal with cache management differently
64 * because they have the address translation always enabled.
65 * The 40x ppc's don't use address translation in U-Boot at all,
66 * so we have to distinguish here between 40x and 44x.
72 * Allocate a new TLB entry, since we are going to modify
73 * the write-through and caching inhibited storage attributes.
75 program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
78 /* Find the TLB entry */
80 if (i >= PPC4XX_TLB_SIZE) {
81 printf ("Failed to program tlb entry\n");
85 if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
91 ints = disable_interrupts ();
95 res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
98 res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
101 res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
104 res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
107 res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
110 res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
113 enable_interrupts ();
116 remove_tlb((u32)virt, CACHE_POST_SIZE);
122 #endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */