3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
40 #if CONFIG_POST & CONFIG_SYS_POST_UART
41 #if defined(CONFIG_8xx)
43 #elif defined(CONFIG_MPC8260)
44 #include <asm/cpm_8260.h>
46 #error "Apparently a bad configuration, please fix."
51 DECLARE_GLOBAL_DATA_PTR;
56 /* The list of controllers to test */
57 #if defined(CONFIG_MPC823)
58 static int ctlr_list[][2] =
59 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
61 static int ctlr_list[][2] = { };
65 void (*init) (int index);
66 void (*halt) (int index);
67 void (*putc) (int index, const char c);
68 int (*getc) (int index);
71 static char *ctlr_name[2] = { "SMC", "SCC" };
73 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
74 static int proff_scc[] =
75 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
81 static void smc_init (int smc_index)
83 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
85 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
87 volatile smc_uart_t *up;
88 volatile cbd_t *tbdf, *rbdf;
89 volatile cpm8xx_t *cp = &(im->im_cpm);
92 /* initialize pointers to SMC */
94 sp = (smc_t *) & (cp->cp_smc[smc_index]);
95 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
97 /* Disable transmitter/receiver.
99 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
103 im->im_siu_conf.sc_sdcr = 1;
105 /* clear error conditions */
106 #ifdef CONFIG_SYS_SDSR
107 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
109 im->im_sdma.sdma_sdsr = 0x83;
112 /* clear SDMA interrupt mask */
113 #ifdef CONFIG_SYS_SDMR
114 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
116 im->im_sdma.sdma_sdmr = 0x00;
119 #if defined(CONFIG_FADS)
122 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
125 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
126 /* Enable Monitor Port Transceiver */
127 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
130 /* Set the physical address of the host memory buffers in
131 * the buffer descriptors.
134 #ifdef CONFIG_SYS_ALLOC_DPRAM
135 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
137 dpaddr = CPM_POST_BASE;
140 /* Allocate space for two buffer descriptors in the DP ram.
141 * For now, this address seems OK, but it may have to
142 * change with newer versions of the firmware.
143 * damm: allocating space after the two buffers for rx/tx data
146 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
147 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
150 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
153 /* Set up the uart parameters in the parameter ram.
155 up->smc_rbase = dpaddr;
156 up->smc_tbase = dpaddr + sizeof (cbd_t);
157 up->smc_rfcr = SMC_EB;
158 up->smc_tfcr = SMC_EB;
160 #if defined(CONFIG_MBX)
161 board_serial_init ();
164 /* Set UART mode, 8 bit, no parity, one stop.
165 * Enable receive and transmit.
166 * Set local loopback mode.
168 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
170 /* Mask all interrupts and remove anything pending.
175 /* Set up the baud rate generator.
177 cp->cp_simode = 0x00000000;
180 (((gd->cpu_clk / 16 / gd->baudrate) -
181 1) << 1) | CPM_BRG_EN;
183 /* Make the first buffer the only buffer.
185 tbdf->cbd_sc |= BD_SC_WRAP;
186 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
188 /* Single character receive.
193 /* Initialize Tx/Rx parameters.
196 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
200 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
202 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
205 /* Enable transmitter/receiver.
207 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
210 static void smc_halt(int smc_index)
214 static void smc_putc (int smc_index, const char c)
216 volatile cbd_t *tbdf;
218 volatile smc_uart_t *up;
219 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
220 volatile cpm8xx_t *cpmp = &(im->im_cpm);
222 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
224 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
226 /* Wait for last character to go.
229 buf = (char *) tbdf->cbd_bufaddr;
232 while (tbdf->cbd_sc & BD_SC_READY)
237 tbdf->cbd_datlen = 1;
238 tbdf->cbd_sc |= BD_SC_READY;
241 while (tbdf->cbd_sc & BD_SC_READY)
246 static int smc_getc (int smc_index)
248 volatile cbd_t *rbdf;
249 volatile unsigned char *buf;
250 volatile smc_uart_t *up;
251 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
252 volatile cpm8xx_t *cpmp = &(im->im_cpm);
256 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
258 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
260 /* Wait for character to show up.
262 buf = (unsigned char *) rbdf->cbd_bufaddr;
264 while (rbdf->cbd_sc & BD_SC_EMPTY);
266 for (i = 100; i > 0; i--) {
267 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
276 rbdf->cbd_sc |= BD_SC_EMPTY;
285 static void scc_init (int scc_index)
287 static int cpm_cr_ch[] = {
294 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
296 volatile scc_uart_t *up;
297 volatile cbd_t *tbdf, *rbdf;
298 volatile cpm8xx_t *cp = &(im->im_cpm);
301 /* initialize pointers to SCC */
303 sp = (scc_t *) & (cp->cp_scc[scc_index]);
304 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
306 /* Disable transmitter/receiver.
308 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
311 /* Allocate space for two buffer descriptors in the DP ram.
314 #ifdef CONFIG_SYS_ALLOC_DPRAM
315 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
317 dpaddr = CPM_POST_BASE;
322 im->im_siu_conf.sc_sdcr = 0x0001;
324 /* Set the physical address of the host memory buffers in
325 * the buffer descriptors.
328 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
329 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
332 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
335 /* Set up the baud rate generator.
337 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
338 /* no |= needed, since BRG1 is 000 */
341 (((gd->cpu_clk / 16 / gd->baudrate) -
342 1) << 1) | CPM_BRG_EN;
344 /* Set up the uart parameters in the parameter ram.
346 up->scc_genscc.scc_rbase = dpaddr;
347 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
349 /* Initialize Tx/Rx parameters.
351 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
354 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
356 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
359 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
360 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
362 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
363 up->scc_maxidl = 0; /* disable max idle */
364 up->scc_brkcr = 1; /* send one break character on stop TX */
372 up->scc_char1 = 0x8000;
373 up->scc_char2 = 0x8000;
374 up->scc_char3 = 0x8000;
375 up->scc_char4 = 0x8000;
376 up->scc_char5 = 0x8000;
377 up->scc_char6 = 0x8000;
378 up->scc_char7 = 0x8000;
379 up->scc_char8 = 0x8000;
380 up->scc_rccm = 0xc0ff;
382 /* Set low latency / small fifo.
384 sp->scc_gsmrh = SCC_GSMRH_RFW;
388 sp->scc_gsmrl &= ~0xF;
389 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
391 /* Set local loopback mode.
393 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
394 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
396 /* Set clock divider 16 on Tx and Rx
398 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
400 sp->scc_psmr |= SCU_PSMR_CL;
402 /* Mask all interrupts and remove anything pending.
405 sp->scc_scce = 0xffff;
406 sp->scc_dsr = 0x7e7e;
407 sp->scc_psmr = 0x3000;
409 /* Make the first buffer the only buffer.
411 tbdf->cbd_sc |= BD_SC_WRAP;
412 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
414 /* Enable transmitter/receiver.
416 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
419 static void scc_halt(int scc_index)
421 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
422 volatile cpm8xx_t *cp = &(im->im_cpm);
423 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
425 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
428 static void scc_putc (int scc_index, const char c)
430 volatile cbd_t *tbdf;
432 volatile scc_uart_t *up;
433 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
434 volatile cpm8xx_t *cpmp = &(im->im_cpm);
436 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
438 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
440 /* Wait for last character to go.
443 buf = (char *) tbdf->cbd_bufaddr;
446 while (tbdf->cbd_sc & BD_SC_READY)
451 tbdf->cbd_datlen = 1;
452 tbdf->cbd_sc |= BD_SC_READY;
455 while (tbdf->cbd_sc & BD_SC_READY)
460 static int scc_getc (int scc_index)
462 volatile cbd_t *rbdf;
463 volatile unsigned char *buf;
464 volatile scc_uart_t *up;
465 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
466 volatile cpm8xx_t *cpmp = &(im->im_cpm);
470 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
472 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
474 /* Wait for character to show up.
476 buf = (unsigned char *) rbdf->cbd_bufaddr;
478 while (rbdf->cbd_sc & BD_SC_EMPTY);
480 for (i = 100; i > 0; i--) {
481 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
490 rbdf->cbd_sc |= BD_SC_EMPTY;
499 static int test_ctlr (int ctlr, int index)
502 char test_str[] = "*** UART Test String ***\r\n";
505 ctlr_proc[ctlr].init (index);
507 for (i = 0; i < sizeof (test_str) - 1; i++) {
508 ctlr_proc[ctlr].putc (index, test_str[i]);
509 if (ctlr_proc[ctlr].getc (index) != test_str[i])
516 ctlr_proc[ctlr].halt (index);
519 post_log ("uart %s%d test failed\n",
520 ctlr_name[ctlr], index + 1);
526 int uart_post_test (int flags)
531 ctlr_proc[CTLR_SMC].init = smc_init;
532 ctlr_proc[CTLR_SMC].halt = smc_halt;
533 ctlr_proc[CTLR_SMC].putc = smc_putc;
534 ctlr_proc[CTLR_SMC].getc = smc_getc;
536 ctlr_proc[CTLR_SCC].init = scc_init;
537 ctlr_proc[CTLR_SCC].halt = scc_halt;
538 ctlr_proc[CTLR_SCC].putc = scc_putc;
539 ctlr_proc[CTLR_SCC].getc = scc_getc;
541 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
542 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
547 #if !defined(CONFIG_8xx_CONS_NONE)
548 serial_reinit_all ();
554 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */