post/cpu/cpu_asm.h

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _CPU_ASM_H
  24 #define _CPU_ASM_H
  25
  26 #define BIT_C                           0x00000001
  27
  28 #define OP_BLR                          0x4e800020
  29 #define OP_EXTSB                        0x7c000774
  30 #define OP_EXTSH                        0x7c000734
  31 #define OP_NEG                          0x7c0000d0
  32 #define OP_CNTLZW                       0x7c000034
  33 #define OP_ADD                          0x7c000214
  34 #define OP_ADDC                         0x7c000014
  35 #define OP_ADDME                        0x7c0001d4
  36 #define OP_ADDZE                        0x7c000194
  37 #define OP_ADDE                         0x7c000114
  38 #define OP_ADDI                         0x38000000
  39 #define OP_SUBF                         0x7c000050
  40 #define OP_SUBFC                        0x7c000010
  41 #define OP_SUBFE                        0x7c000110
  42 #define OP_SUBFME                       0x7c0001d0
  43 #define OP_SUBFZE                       0x7c000190
  44 #define OP_MFCR                         0x7c000026
  45 #define OP_MTCR                         0x7c0ff120
  46 #define OP_MFXER                        0x7c0102a6
  47 #define OP_MTXER                        0x7c0103a6
  48 #define OP_MCRXR                        0x7c000400
  49 #define OP_MCRF                         0x4c000000
  50 #define OP_CRAND                        0x4c000202
  51 #define OP_CRANDC                       0x4c000102
  52 #define OP_CROR                         0x4c000382
  53 #define OP_CRORC                        0x4c000342
  54 #define OP_CRXOR                        0x4c000182
  55 #define OP_CRNAND                       0x4c0001c2
  56 #define OP_CRNOR                        0x4c000042
  57 #define OP_CREQV                        0x4c000242
  58 #define OP_CMPW                         0x7c000000
  59 #define OP_CMPLW                        0x7c000040
  60 #define OP_CMPWI                        0x2c000000
  61 #define OP_CMPLWI                       0x28000000
  62 #define OP_MULLW                        0x7c0001d6
  63 #define OP_MULHW                        0x7c000096
  64 #define OP_MULHWU                       0x7c000016
  65 #define OP_DIVW                         0x7c0003d6
  66 #define OP_DIVWU                        0x7c000396
  67 #define OP_OR                           0x7c000378
  68 #define OP_ORC                          0x7c000338
  69 #define OP_XOR                          0x7c000278
  70 #define OP_NAND                         0x7c0003b8
  71 #define OP_NOR                          0x7c0000f8
  72 #define OP_EQV                          0x7c000238
  73 #define OP_SLW                          0x7c000030
  74 #define OP_SRW                          0x7c000430
  75 #define OP_SRAW                         0x7c000630
  76 #define OP_ORI                          0x60000000
  77 #define OP_ORIS                         0x64000000
  78 #define OP_XORI                         0x68000000
  79 #define OP_XORIS                        0x6c000000
  80 #define OP_ANDI_                        0x70000000
  81 #define OP_ANDIS_                       0x74000000
  82 #define OP_SRAWI                        0x7c000670
  83 #define OP_RLWINM                       0x54000000
  84 #define OP_RLWNM                        0x5c000000
  85 #define OP_RLWIMI                       0x50000000
  86 #define OP_LWZ                          0x80000000
  87 #define OP_LHZ                          0xa0000000
  88 #define OP_LHA                          0xa8000000
  89 #define OP_LBZ                          0x88000000
  90 #define OP_LWZU                         0x84000000
  91 #define OP_LHZU                         0xa4000000
  92 #define OP_LHAU                         0xac000000
  93 #define OP_LBZU                         0x8c000000
  94 #define OP_LWZX                         0x7c00002e
  95 #define OP_LHZX                         0x7c00022e
  96 #define OP_LHAX                         0x7c0002ae
  97 #define OP_LBZX                         0x7c0000ae
  98 #define OP_LWZUX                        0x7c00006e
  99 #define OP_LHZUX                        0x7c00026e
 100 #define OP_LHAUX                        0x7c0002ee
 101 #define OP_LBZUX                        0x7c0000ee
 102 #define OP_STW                          0x90000000
 103 #define OP_STH                          0xb0000000
 104 #define OP_STB                          0x98000000
 105 #define OP_STWU                         0x94000000
 106 #define OP_STHU                         0xb4000000
 107 #define OP_STBU                         0x9c000000
 108 #define OP_STWX                         0x7c00012e
 109 #define OP_STHX                         0x7c00032e
 110 #define OP_STBX                         0x7c0001ae
 111 #define OP_STWUX                        0x7c00016e
 112 #define OP_STHUX                        0x7c00036e
 113 #define OP_STBUX                        0x7c0001ee
 114 #define OP_B                            0x48000000
 115 #define OP_BL                           0x48000001
 116 #define OP_BC                           0x40000000
 117 #define OP_BCL                          0x40000001
 118 #define OP_MTLR                         0x7c0803a6
 119 #define OP_MFLR                         0x7c0802a6
 120 #define OP_MTCTR                        0x7c0903a6
 121 #define OP_MFCTR                        0x7c0902a6
 122 #define OP_LMW                          0xb8000000
 123 #define OP_STMW                         0xbc000000
 124 #define OP_LSWI                         0x7c0004aa
 125 #define OP_LSWX                         0x7c00042a
 126 #define OP_STSWI                        0x7c0005aa
 127 #define OP_STSWX                        0x7c00052a
 128
 129 #define ASM_0(opcode)                   (opcode)
 130 #define ASM_1(opcode, rd)               ((opcode) +             \
 131                                          ((rd) << 21))
 132 #define ASM_1C(opcode, cr)              ((opcode) +             \
 133                                          ((cr) << 23))
 134 #define ASM_11(opcode, rd, rs)          ((opcode) +             \
 135                                          ((rd) << 21) +         \
 136                                          ((rs) << 16))
 137 #define ASM_11C(opcode, cd, cs)         ((opcode) +             \
 138                                          ((cd) << 23) +         \
 139                                          ((cs) << 18))
 140 #define ASM_11X(opcode, rd, rs)         ((opcode) +             \
 141                                          ((rs) << 21) +         \
 142                                          ((rd) << 16))
 143 #define ASM_11I(opcode, rd, rs, simm)   ((opcode) +             \
 144                                          ((rd) << 21) +         \
 145                                          ((rs) << 16) +         \
 146                                          ((simm) & 0xffff))
 147 #define ASM_11IF(opcode, rd, rs, simm)  ((opcode) +             \
 148                                          ((rd) << 21) +         \
 149                                          ((rs) << 16) +         \
 150                                          ((simm) << 11))
 151 #define ASM_11S(opcode, rd, rs, sh)     ((opcode) +             \
 152                                          ((rs) << 21) +         \
 153                                          ((rd) << 16) +         \
 154                                          ((sh) << 11))
 155 #define ASM_11IX(opcode, rd, rs, imm)   ((opcode) +             \
 156                                          ((rs) << 21) +         \
 157                                          ((rd) << 16) +         \
 158                                          ((imm) & 0xffff))
 159 #define ASM_12(opcode, rd, rs1, rs2)    ((opcode) +             \
 160                                          ((rd) << 21) +         \
 161                                          ((rs1) << 16) +        \
 162                                          ((rs2) << 11))
 163 #define ASM_12F(opcode, fd, fs1, fs2)   ((opcode) +             \
 164                                          ((fd) << 21) +         \
 165                                          ((fs1) << 16) +        \
 166                                          ((fs2) << 11))
 167 #define ASM_12X(opcode, rd, rs1, rs2)   ((opcode) +             \
 168                                          ((rs1) << 21) +        \
 169                                          ((rd) << 16) +         \
 170                                          ((rs2) << 11))
 171 #define ASM_2C(opcode, cr, rs1, rs2)    ((opcode) +             \
 172                                          ((cr) << 23) +         \
 173                                          ((rs1) << 16) +        \
 174                                          ((rs2) << 11))
 175 #define ASM_1IC(opcode, cr, rs, imm)    ((opcode) +             \
 176                                          ((cr) << 23) +         \
 177                                          ((rs) << 16) +         \
 178                                          ((imm) & 0xffff))
 179 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2)               \
 180                                         ((opcode) +             \
 181                                          ((rs1) << 21) +        \
 182                                          ((rd) << 16) +         \
 183                                          ((rs2) << 11) +        \
 184                                          ((imm1) << 6) +        \
 185                                          ((imm2) << 1))
 186 #define ASM_113(opcode, rd, rs, imm1, imm2, imm3)               \
 187                                         ((opcode) +             \
 188                                          ((rs) << 21) +         \
 189                                          ((rd) << 16) +         \
 190                                          ((imm1) << 11) +       \
 191                                          ((imm2) << 6) +        \
 192                                          ((imm3) << 1))
 193 #define ASM_1O(opcode, off)             ((opcode) + (off))
 194 #define ASM_3O(opcode, bo, bi, off)     ((opcode) +             \
 195                                          ((bo) << 21) +         \
 196                                          ((bi) << 16) +         \
 197                                          (off))
 198
 199 #define ASM_ADDI(rd, rs, simm)          ASM_11I(OP_ADDI, rd, rs, simm)
 200 #define ASM_BLR                         ASM_0(OP_BLR)
 201 #define ASM_STW(rd, rs, simm)           ASM_11I(OP_STW, rd, rs, simm)
 202 #define ASM_LWZ(rd, rs, simm)           ASM_11I(OP_LWZ, rd, rs, simm)
 203 #define ASM_MFCR(rd)                    ASM_1(OP_MFCR, rd)
 204 #define ASM_MTCR(rd)                    ASM_1(OP_MTCR, rd)
 205 #define ASM_MFXER(rd)                   ASM_1(OP_MFXER, rd)
 206 #define ASM_MTXER(rd)                   ASM_1(OP_MTXER, rd)
 207 #define ASM_MFCTR(rd)                   ASM_1(OP_MFCTR, rd)
 208 #define ASM_MTCTR(rd)                   ASM_1(OP_MTCTR, rd)
 209 #define ASM_MCRXR(cr)                   ASM_1C(OP_MCRXR, cr)
 210 #define ASM_MCRF(cd, cs)                ASM_11C(OP_MCRF, cd, cs)
 211 #define ASM_B(off)                      ASM_1O(OP_B, off)
 212 #define ASM_BL(off)                     ASM_1O(OP_BL, off)
 213 #define ASM_MFLR(rd)                    ASM_1(OP_MFLR, rd)
 214 #define ASM_MTLR(rd)                    ASM_1(OP_MTLR, rd)
 215 #define ASM_LI(rd, imm)                 ASM_ADDI(rd, 0, imm)
 216 #define ASM_LMW(rd, rs, simm)           ASM_11I(OP_LMW, rd, rs, simm)
 217 #define ASM_STMW(rd, rs, simm)          ASM_11I(OP_STMW, rd, rs, simm)
 218 #define ASM_LSWI(rd, rs, simm)          ASM_11IF(OP_LSWI, rd, rs, simm)
 219 #define ASM_LSWX(rd, rs1, rs2)          ASM_12(OP_LSWX, rd, rs1, rs2)
 220 #define ASM_STSWI(rd, rs, simm)         ASM_11IF(OP_STSWI, rd, rs, simm)
 221 #define ASM_STSWX(rd, rs1, rs2)         ASM_12(OP_STSWX, rd, rs1, rs2)
 222
 223
 224 #endif /* _CPU_ASM_H */