2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/processor.h>
38 #define PCI_HOSE_OP(rw, size, type) \
39 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
41 int offset, type value) \
43 return hose->rw##_##size(hose, dev, offset, value); \
46 PCI_HOSE_OP(read, byte, u8 *)
47 PCI_HOSE_OP(read, word, u16 *)
48 PCI_HOSE_OP(read, dword, u32 *)
49 PCI_HOSE_OP(write, byte, u8)
50 PCI_HOSE_OP(write, word, u16)
51 PCI_HOSE_OP(write, dword, u32)
54 #define PCI_OP(rw, size, type, error_code) \
55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
57 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
65 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
68 PCI_OP(read, byte, u8 *, *value = 0xff)
69 PCI_OP(read, word, u16 *, *value = 0xffff)
70 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
71 PCI_OP(write, byte, u8, )
72 PCI_OP(write, word, u16, )
73 PCI_OP(write, dword, u32, )
74 #endif /* CONFIG_IXP425 */
76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
79 int offset, type val) \
83 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
88 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
96 int offset, type val) \
98 u32 val32, mask, ldata, shift; \
100 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
103 shift = ((offset & (int)off_mask) * 8); \
104 ldata = (((unsigned long)val) & val_mask) << shift; \
105 mask = val_mask << shift; \
106 val32 = (val32 & ~mask) | ldata; \
108 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
114 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
115 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
116 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
117 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
119 /* Get a virtual address associated with a BAR region */
120 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
122 pci_addr_t pci_bus_addr;
125 /* read BAR address */
126 pci_read_config_dword(pdev, bar, &bar_response);
127 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
130 * Pass "0" as the length argument to pci_bus_to_virt. The arg
131 * isn't actualy used on any platform because u-boot assumes a static
132 * linear mapping. In the future, this could read the BAR size
133 * and pass that as the size if needed.
135 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
142 static struct pci_controller* hose_head;
144 void pci_register_hose(struct pci_controller* hose)
146 struct pci_controller **phose = &hose_head;
149 phose = &(*phose)->next;
156 struct pci_controller *pci_bus_to_hose (int bus)
158 struct pci_controller *hose;
160 for (hose = hose_head; hose; hose = hose->next)
161 if (bus >= hose->first_busno && bus <= hose->last_busno)
164 printf("pci_bus_to_hose() failed\n");
168 int pci_last_busno(void)
170 struct pci_controller *hose = hose_head;
178 return hose->last_busno;
181 #ifndef CONFIG_IXP425
182 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
184 struct pci_controller * hose;
188 int i, bus, found_multi = 0;
190 for (hose = hose_head; hose; hose = hose->next)
192 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
193 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
195 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
197 for (bdf = PCI_BDF(bus,0,0);
198 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
199 bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
201 bdf < PCI_BDF(bus+1,0,0);
203 bdf += PCI_BDF(0,0,1))
205 if (!PCI_FUNC(bdf)) {
206 pci_read_config_byte(bdf,
210 found_multi = header_type & 0x80;
216 pci_read_config_word(bdf,
219 pci_read_config_word(bdf,
223 for (i=0; ids[i].vendor != 0; i++)
224 if (vendor == ids[i].vendor &&
225 device == ids[i].device)
237 #endif /* CONFIG_IXP425 */
239 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
241 static struct pci_device_id ids[2] = {{}, {0, 0}};
243 ids[0].vendor = vendor;
244 ids[0].device = device;
246 return pci_find_devices(ids, index);
253 int __pci_hose_phys_to_bus (struct pci_controller *hose,
254 phys_addr_t phys_addr,
256 unsigned long skip_mask,
259 struct pci_region *res;
263 for (i = 0; i < hose->region_count; i++) {
264 res = &hose->regions[i];
266 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
269 if (res->flags & skip_mask)
272 bus_addr = phys_addr - res->phys_start + res->bus_start;
274 if (bus_addr >= res->bus_start &&
275 bus_addr < res->bus_start + res->size) {
284 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
285 phys_addr_t phys_addr,
288 pci_addr_t bus_addr = 0;
292 puts ("pci_hose_phys_to_bus: invalid hose\n");
296 /* if PCI_REGION_MEM is set we do a two pass search with preference
297 * on matches that don't have PCI_REGION_SYS_MEMORY set */
298 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
299 ret = __pci_hose_phys_to_bus(hose, phys_addr,
300 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
305 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
308 puts ("pci_hose_phys_to_bus: invalid physical address\n");
313 int __pci_hose_bus_to_phys (struct pci_controller *hose,
316 unsigned long skip_mask,
319 struct pci_region *res;
322 for (i = 0; i < hose->region_count; i++) {
323 res = &hose->regions[i];
325 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
328 if (res->flags & skip_mask)
331 if (bus_addr >= res->bus_start &&
332 bus_addr < res->bus_start + res->size) {
333 *pa = (bus_addr - res->bus_start + res->phys_start);
341 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
345 phys_addr_t phys_addr = 0;
349 puts ("pci_hose_bus_to_phys: invalid hose\n");
353 /* if PCI_REGION_MEM is set we do a two pass search with preference
354 * on matches that don't have PCI_REGION_SYS_MEMORY set */
355 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
356 ret = __pci_hose_bus_to_phys(hose, bus_addr,
357 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
362 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
365 puts ("pci_hose_bus_to_phys: invalid physical address\n");
374 int pci_hose_config_device(struct pci_controller *hose,
378 unsigned long command)
380 unsigned int bar_response, old_command;
381 pci_addr_t bar_value;
384 int bar, found_mem64;
386 debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
387 io, (u64)mem, command);
389 pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
391 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
392 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
393 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
400 /* Check the BAR type and set our address mask */
401 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
402 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
403 /* round up region base address to a multiple of size */
404 io = ((io - 1) | (bar_size - 1)) + 1;
406 /* compute new region base address */
409 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
410 PCI_BASE_ADDRESS_MEM_TYPE_64) {
411 u32 bar_response_upper;
413 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
414 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
416 bar64 = ((u64)bar_response_upper << 32) | bar_response;
418 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
421 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
424 /* round up region base address to multiple of size */
425 mem = ((mem - 1) | (bar_size - 1)) + 1;
427 /* compute new region base address */
428 mem = mem + bar_size;
431 /* Write it out and update our limit */
432 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
436 #ifdef CONFIG_SYS_PCI_64BIT
437 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
439 pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
444 /* Configure Cache Line Size Register */
445 pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
447 /* Configure Latency Timer */
448 pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
450 /* Disable interrupt line, if device says it wants to use interrupts */
451 pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
453 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
456 pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
457 pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
458 (old_command & 0xffff0000) | command);
467 struct pci_config_table *pci_find_config(struct pci_controller *hose,
468 unsigned short class,
475 struct pci_config_table *table;
477 for (table = hose->config_table; table && table->vendor; table++) {
478 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
479 (table->device == PCI_ANY_ID || table->device == device) &&
480 (table->class == PCI_ANY_ID || table->class == class) &&
481 (table->bus == PCI_ANY_ID || table->bus == bus) &&
482 (table->dev == PCI_ANY_ID || table->dev == dev) &&
483 (table->func == PCI_ANY_ID || table->func == func)) {
491 void pci_cfgfunc_config_device(struct pci_controller *hose,
493 struct pci_config_table *entry)
495 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
498 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
499 pci_dev_t dev, struct pci_config_table *entry)
507 /* HJF: Changed this to return int. I think this is required
508 * to get the correct result when scanning bridges
510 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
511 extern void pciauto_config_init(struct pci_controller *hose);
513 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
514 const char * pci_class_str(u8 class)
517 case PCI_CLASS_NOT_DEFINED:
518 return "Build before PCI Rev2.0";
520 case PCI_BASE_CLASS_STORAGE:
521 return "Mass storage controller";
523 case PCI_BASE_CLASS_NETWORK:
524 return "Network controller";
526 case PCI_BASE_CLASS_DISPLAY:
527 return "Display controller";
529 case PCI_BASE_CLASS_MULTIMEDIA:
530 return "Multimedia device";
532 case PCI_BASE_CLASS_MEMORY:
533 return "Memory controller";
535 case PCI_BASE_CLASS_BRIDGE:
536 return "Bridge device";
538 case PCI_BASE_CLASS_COMMUNICATION:
539 return "Simple comm. controller";
541 case PCI_BASE_CLASS_SYSTEM:
542 return "Base system peripheral";
544 case PCI_BASE_CLASS_INPUT:
545 return "Input device";
547 case PCI_BASE_CLASS_DOCKING:
548 return "Docking station";
550 case PCI_BASE_CLASS_PROCESSOR:
553 case PCI_BASE_CLASS_SERIAL:
554 return "Serial bus controller";
556 case PCI_BASE_CLASS_INTELLIGENT:
557 return "Intelligent controller";
559 case PCI_BASE_CLASS_SATELLITE:
560 return "Satellite controller";
562 case PCI_BASE_CLASS_CRYPT:
563 return "Cryptographic device";
565 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
568 case PCI_CLASS_OTHERS:
569 return "Does not fit any class";
576 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
578 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
581 * Check if pci device should be skipped in configuration
583 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
584 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
586 * Only skip configuration if "pciconfighost" is not set
588 if (getenv("pciconfighost") == NULL)
597 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
598 __attribute__((weak, alias("__pci_skip_dev")));
600 #ifdef CONFIG_PCI_SCAN_SHOW
601 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
603 if (dev == PCI_BDF(hose->first_busno, 0, 0))
608 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
609 __attribute__((weak, alias("__pci_print_dev")));
610 #endif /* CONFIG_PCI_SCAN_SHOW */
612 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
614 unsigned int sub_bus, found_multi=0;
615 unsigned short vendor, device, class;
616 unsigned char header_type;
617 struct pci_config_table *cfg;
619 #ifdef CONFIG_PCI_SCAN_SHOW
620 static int indent = 0;
625 for (dev = PCI_BDF(bus,0,0);
626 dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
627 dev += PCI_BDF(0,0,1)) {
629 if (pci_skip_dev(hose, dev))
632 if (PCI_FUNC(dev) && !found_multi)
635 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
637 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
639 if (vendor == 0xffff || vendor == 0x0000)
643 found_multi = header_type & 0x80;
645 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
646 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
648 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
649 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
651 #ifdef CONFIG_PCI_SCAN_SHOW
654 /* Print leading space, including bus indentation */
655 printf("%*c", indent + 1, ' ');
657 if (pci_print_dev(hose, dev)) {
658 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
659 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
660 vendor, device, pci_class_str(class >> 8));
664 cfg = pci_find_config(hose, class, vendor, device,
665 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
667 cfg->config_device(hose, dev, cfg);
668 sub_bus = max(sub_bus, hose->current_busno);
669 #ifdef CONFIG_PCI_PNP
671 int n = pciauto_config_device(hose, dev);
673 sub_bus = max(sub_bus, n);
677 #ifdef CONFIG_PCI_SCAN_SHOW
682 hose->fixup_irq(hose, dev);
688 int pci_hose_scan(struct pci_controller *hose)
690 /* Start scan at current_busno.
691 * PCIe will start scan at first_busno+1.
693 /* For legacy support, ensure current>=first */
694 if (hose->first_busno > hose->current_busno)
695 hose->current_busno = hose->first_busno;
696 #ifdef CONFIG_PCI_PNP
697 pciauto_config_init(hose);
699 return pci_hose_scan_bus(hose, hose->current_busno);
704 #if defined(CONFIG_PCI_BOOTDELAY)
708 /* wait "pcidelay" ms (if defined)... */
709 s = getenv ("pcidelay");
711 int val = simple_strtoul (s, NULL, 10);
712 for (i=0; i<val; i++)
715 #endif /* CONFIG_PCI_BOOTDELAY */
719 /* now call board specific pci_init()... */