3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Thomas Langer, Ralph Hempel
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/addrspace.h>
32 #include <asm/danube.h>
33 #include <asm/reboot.h>
35 #if defined(CONFIG_CMD_HTTPD)
38 #if defined(CONFIG_PCI)
41 #if defined(CONFIG_AR8216_SWITCH)
42 #include "athrs26_phy.h"
45 extern ulong ifx_get_ddr_hz(void);
46 extern ulong ifx_get_cpuclk(void);
48 /* IDs and registers of known external switches */
49 void _machine_restart(void)
51 *DANUBE_RCU_RST_REQ |=1<<30;
54 #ifdef CONFIG_SYS_RAMBOOT
55 phys_size_t initdram(int board_type)
57 return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
59 #elif defined(CONFIG_USE_DDR_RAM)
60 phys_size_t initdram(int board_type)
62 return (CONFIG_SYS_MAX_RAM);
66 static ulong max_sdram_size(void) /* per Chip Select */
68 /* The only supported SDRAM data width is 16bit.
72 /* The only supported number of SDRAM banks is 4.
76 ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
77 int cols = cfgpb0 & 0xF;
78 int rows = (cfgpb0 & 0xF0) >> 4;
79 ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
85 * Check memory range for valid RAM. A simple memory test determines
86 * the actually available RAM size between addresses `base' and
90 static long int dram_size(long int *base, long int maxsize)
92 volatile long int *addr;
94 ulong save[32]; /* to make test non-destructive */
97 for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
98 addr = base + cnt; /* pointer arith! */
104 /* write 0 to base address */
109 /* check at base address */
110 if ((val = *addr) != 0) {
115 for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
116 addr = base + cnt; /* pointer arith! */
122 return (cnt * sizeof (long));
128 phys_size_t initdram(int board_type)
130 int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
131 ulong size, max_size = 0;
134 /* load t9 into our_address */
135 asm volatile ("move %0, $25" : "=r" (our_address) :);
137 /* Can't probe for RAM size unless we are running from Flash.
138 * find out whether running from DRAM or Flash.
140 if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
142 return max_sdram_size();
145 for (cols = 0x8; cols <= 0xC; cols++)
147 for (rows = 0xB; rows <= 0xD; rows++)
149 *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
151 size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
156 best_val = *DANUBE_SDRAM_MC_CFGPB0;
162 *DANUBE_SDRAM_MC_CFGPB0 = best_val;
167 static void gpio_default(void)
169 #ifdef CONFIG_SWITCH_PORT0
170 *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
171 *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
172 *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
173 *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
174 *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
175 #elif defined(CONFIG_SWITCH_PORT1)
176 *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
177 *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
178 *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
179 *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
180 *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
182 #ifdef CONFIG_EBU_GPIO
185 printf ("bring up ebu gpio\n");
186 *DANUBE_EBU_BUSCON1 = 0x1e7ff;
187 *DANUBE_EBU_ADDSEL1 = 0x14000001;
189 *((volatile u16*)0xb4000000) = 0x0;
190 for(i = 0; i < 1000; i++)
192 *((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
193 *DANUBE_EBU_BUSCON1 = 0x8001e7ff;
196 #ifdef CONFIG_BUTTON_PORT0
197 *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
198 *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
199 *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
200 if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
202 printf("button is pressed\n");
203 setenv("bootdelay", "0");
204 setenv("bootcmd", "httpd");
206 #elif defined(CONFIG_BUTTON_PORT1)
207 *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
208 *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
209 *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
210 if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
212 printf("button is pressed\n");
213 setenv("bootdelay", "0");
214 setenv("bootcmd", "httpd");
217 #ifdef CONFIG_ARV4525
218 *DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
219 *DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
220 *DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
221 *DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
222 *DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
226 int checkboard (void)
228 unsigned long chipid = *DANUBE_MPS_CHIPID;
231 puts ("Board: "CONFIG_ARCADYAN"\n");
234 part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
240 puts("Danube/Twinpass/Vinax-VE ");
243 printf ("unknown, chip part number 0x%03X ", part_num);
246 printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
248 printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
249 printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
255 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
256 int board_early_init_f(void)
258 #ifdef CONFIG_EBU_ADDSEL0
259 (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
261 #ifdef CONFIG_EBU_ADDSEL1
262 (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
264 #ifdef CONFIG_EBU_ADDSEL2
265 (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
267 #ifdef CONFIG_EBU_ADDSEL3
268 (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
270 #ifdef CONFIG_EBU_BUSCON0
271 (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
273 #ifdef CONFIG_EBU_BUSCON1
274 (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
276 #ifdef CONFIG_EBU_BUSCON2
277 (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
279 #ifdef CONFIG_EBU_BUSCON3
280 (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
285 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
287 #ifdef CONFIG_RTL8306_SWITCH
288 #define ID_RTL8306 0x5988
289 static int external_switch_rtl8306(void)
291 unsigned short chipid;
292 static char * const name = "lq_cpe_eth";
296 puts("\nsearching for rtl8306 switch ... ");
297 if (miiphy_read(name, 4, 30, &chipid) == 0) {
298 if (chipid == ID_RTL8306) {
301 miiphy_write(name, 0, 19, 0xffff);
303 miiphy_write(name, 4, 22, 0x877f);
309 puts("\nno known switch found ... \n");
315 #ifdef CONFIG_RTL8306G_SWITCH
316 #define ID_RTL8306 0x5988
318 static int external_switch_rtl8306G(void)
320 unsigned short chipid,val;
322 static char * const name = "lq_cpe_eth";
323 unsigned int chipid2, chipver, chiptype;
325 int cpu_mask = 1 << 5;
328 puts("\nsearching for rtl8306 switch ... ");
329 if (miiphy_read(name, 4, 30, &chipid) == 0) {
330 if (chipid == ID_RTL8306) {
331 puts("found\nReset Hard\n");
332 #ifdef CONFIG_ARV752DPW
334 //reset reset ping to high
335 *DANUBE_GPIO_P1_DIR |= 8;
336 *DANUBE_GPIO_P1_OUT |= 8;
338 *DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
340 *DANUBE_GPIO_P1_OUT |= 8;
346 miiphy_write(name, 0, 0, 0x3100);
347 miiphy_write(name, 0, 18, 0x7fff);
348 miiphy_write(name, 0, 19, 0xffff);
349 miiphy_write(name, 0, 22, 0x877f);
350 miiphy_write(name, 0, 24, 0x0ed1);
352 miiphy_write(name, 1, 0, 0x3100);
353 miiphy_write(name, 1, 22, 0x877f);
354 miiphy_write(name, 1, 24, 0x1ed2);
356 miiphy_write(name, 2, 0, 0x3100);
357 miiphy_write(name, 2, 22, 0x877f);
358 miiphy_write(name, 2, 23, 0x0020);
359 miiphy_write(name, 2, 24, 0x2ed4);
361 miiphy_write(name, 3, 0, 0x3100);
362 miiphy_write(name, 3, 22, 0x877f);
363 miiphy_write(name, 3, 24, 0x3ed8);
365 miiphy_write(name, 4, 0, 0x3100);
366 miiphy_write(name, 4, 22, 0x877f);
367 miiphy_write(name, 4, 24, 0x4edf);
369 miiphy_write(name, 5, 0, 0x3100);
370 miiphy_write(name, 6, 0, 0x2100);
372 //important. enable phy 5 link status, for rmii
373 miiphy_write(name, 6, 22, 0x873f);
375 miiphy_write(name, 6, 24, 0x8eff);
378 miiphy_read(name, 0, 24, &val);
381 miiphy_write(name, 0, 24, val);
384 puts("Reset Soft\n");
385 miiphy_write(name,0 ,0 ,1<<15);
388 miiphy_read(name,0 ,0 ,&val);
398 for (i=0;i<5;i++) // enable ports
400 miiphy_read(name, 0, 24, &val);
403 miiphy_write(name, 0, 24, val);
410 puts("\nno known switch found ... \n");
416 #ifdef CONFIG_AR8216_SWITCH
417 static int external_switch_ar8216(void)
419 puts("initializing ar8216 switch... ");
420 if (athrs26_phy_setup(0)==0) {
421 printf("initialized\n");
424 puts("failed ... \n");
429 int board_eth_init(bd_t *bis)
433 #if defined(CONFIG_IFX_ETOP)
435 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
436 eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
438 *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
439 *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
441 if (lq_eth_initialize(bis))
444 *DANUBE_RCU_RST_REQ |=1;
446 *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
449 #ifdef CONFIG_RTL8306G_SWITCH
450 if (external_switch_rtl8306G()<0)
453 #ifdef CONFIG_RTL8306_SWITCH
454 if (external_switch_rtl8306()<0)
457 #ifdef CONFIG_AR8216_SWITCH
458 if (external_switch_ar8216()<0)
465 #if defined(CONFIG_CMD_HTTPD)
466 int do_http_upgrade(const unsigned char *data, const ulong size)
470 if(getenv ("ram_addr") == NULL)
472 if(getenv ("kernel_addr") == NULL)
474 /* check the image */
475 if(run_command("imi ${ram_addr}", 0) < 0) {
478 /* write the image to the flash */
479 puts("http ugrade ...\n");
480 sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
481 return run_command(buf, 0);
484 int do_http_progress(const int state)
486 /* toggle LED's here */
488 case HTTP_PROGRESS_START:
489 puts("http start\n");
491 case HTTP_PROGRESS_TIMEOUT:
494 case HTTP_PROGRESS_UPLOAD_READY:
495 puts("http upload ready\n");
497 case HTTP_PROGRESS_UGRADE_READY:
498 puts("http ugrade ready\n");
500 case HTTP_PROGRESS_UGRADE_FAILED:
501 puts("http ugrade failed\n");
507 unsigned long do_http_tmp_address(void)
509 char *s = getenv ("ram_addr");
511 ulong tmp = simple_strtoul (s, NULL, 16);
514 return 0 /*0x80a00000*/;