2 * ADMTEK Adm6996 switch configuration module
4 * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
6 * Partially based on Broadcom Home Networking Division 10/100 Mbit/s
7 * Ethernet Device Driver (from Montavista 2.4.20_mvl31 Kernel).
8 * Copyright (C) 2004 Broadcom Corporation
10 * adm_rreg function from adm6996
11 * Copyright (C) 2004 Nikki Chumakov <nikki@gattaca.ru>
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
29 #include <linux/module.h>
30 #include <linux/init.h>
32 #include <linux/if_arp.h>
33 #include <linux/sockios.h>
34 #include <linux/delay.h>
35 #include <asm/uaccess.h>
37 #include "switch-core.h"
40 #define DRIVER_NAME "adm6996"
41 #define DRIVER_VERSION "0.01"
49 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
50 MODULE_LICENSE("GPL");
51 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
52 module_param(eecs, int, 0);
53 module_param(eesk, int, 0);
54 module_param(eedi, int, 0);
55 module_param(eerc, int, 0);
56 module_param(force, int, 0);
58 MODULE_PARM(eecs, "i");
59 MODULE_PARM(eesk, "i");
60 MODULE_PARM(eedi, "i");
61 MODULE_PARM(eerc, "i");
62 MODULE_PARM(force, "i");
65 /* Minimum timing constants */
66 #define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
67 #define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */
68 #define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */
70 /* Handy macros for writing fixed length values */
71 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
72 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
73 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
75 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
78 extern char *nvram_get(char *name);
80 /* Return gpio pin number assigned to the named pin */
82 * Variable should be in format:
86 * 'def_pin' is returned if there is no such variable found.
88 static unsigned int get_gpiopin(char *pin_name, unsigned int def_pin)
90 char name[] = "gpioXXXX";
94 /* Go thru all possibilities till a match in pin name */
95 for (pin = 0; pin < 16; pin ++) {
96 sprintf(name, "gpio%d", pin);
97 val = nvram_get(name);
98 if (val && !strcmp(val, pin_name))
106 static void adm_write(int cs, char *buf, unsigned int bits)
108 int i, len = (bits + 7) / 8;
111 gpio_out(eecs, (cs ? eecs : 0));
112 udelay(EECK_EDGE_TIME);
114 /* Byte assemble from MSB to LSB */
115 for (i = 0; i < len; i++) {
116 /* Bit bang from MSB to LSB */
117 for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
120 udelay(EECK_EDGE_TIME);
122 /* Output on rising edge */
123 gpio_out(eedi, ((mask & buf[i]) ? eedi : 0));
124 udelay(EEDI_SETUP_TIME);
127 gpio_out(eesk, eesk);
128 udelay(EECK_EDGE_TIME);
134 udelay(EECK_EDGE_TIME);
141 static void adm_read(int cs, char *buf, unsigned int bits)
143 int i, len = (bits + 7) / 8;
146 gpio_out(eecs, (cs ? eecs : 0));
147 udelay(EECK_EDGE_TIME);
149 /* Byte assemble from MSB to LSB */
150 for (i = 0; i < len; i++) {
153 /* Bit bang from MSB to LSB */
154 for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
159 udelay(EECK_EDGE_TIME);
161 /* Input on rising edge */
167 gpio_out(eesk, eesk);
168 udelay(EECK_EDGE_TIME);
176 udelay(EECK_EDGE_TIME);
183 /* Enable outputs with specified value to the chip */
184 static void adm_enout(__u8 pins, __u8 val)
186 /* Prepare GPIO output value */
189 /* Enable GPIO outputs */
190 gpio_outen(pins, pins);
191 udelay(EECK_EDGE_TIME);
195 /* Disable outputs to the chip */
196 static void adm_disout(__u8 pins)
198 /* Disable GPIO outputs */
200 udelay(EECK_EDGE_TIME);
204 /* Advance clock(s) */
205 static void adm_adclk(int clocks)
208 for (i = 0; i < clocks; i++) {
210 gpio_out(eesk, eesk);
211 udelay(EECK_EDGE_TIME);
215 udelay(EECK_EDGE_TIME);
219 static __u32 adm_rreg(__u8 table, __u8 addr)
221 /* cmd: 01 10 T DD R RRRRRR */
223 0xFF, 0xFF, 0xFF, 0xFF,
224 (0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
230 /* Enable GPIO outputs with all pins to 0 */
231 adm_enout((__u8)(eecs | eesk | eedi), 0);
233 adm_write(0, bits, 46);
234 adm_disout((__u8)(eedi));
236 adm_read (0, rbits, 32);
238 /* Extra clock(s) required per datasheet */
241 /* Disable GPIO outputs */
242 adm_disout((__u8)(eecs | eesk));
244 if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
245 return (addr & 0x01 ? (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
247 return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
252 /* Write chip configuration register */
253 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
255 adm_wreg(__u8 addr, __u16 val)
257 /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
259 (0x05 << 5) | (addr >> 3),
260 (addr << 5) | (__u8)(val >> 11),
265 /* Enable GPIO outputs with all pins to 0 */
266 adm_enout((__u8)(eecs | eesk | eedi), 0);
268 /* Write cmd. Total 27 bits */
269 adm_write(1, bits, 27);
271 /* Extra clock(s) required per datasheet */
274 /* Disable GPIO outputs */
275 adm_disout((__u8)(eecs | eesk | eedi));
279 /* Port configuration registers */
280 static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
282 /* Bits in VLAN port mapping */
283 static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
285 static int handle_vlan_port_read(void *driver, char *buf, int nr)
287 int ports, i, c, len = 0;
289 if ((nr < 0) || (nr > 15))
292 /* Get VLAN port map */
293 ports = adm_rreg(0, 0x13 + nr);
295 for (i = 0; i <= 5; i++) {
296 if (ports & vlan_ports[i]) {
297 c = adm_rreg(0, port_conf[i]);
299 len += sprintf(buf + len, "%d", i);
302 if (((c & (0xf << 10)) >> 10) == nr)
310 len += sprintf(buf + len, "\n");
315 static int handle_vlan_port_write(void *driver, char *buf, int nr)
318 switch_driver *d = (switch_driver *) driver;
319 switch_vlan_config *c = switch_parse_vlan(d, buf);
324 ports = adm_rreg(0, 0x13 + nr);
325 for (i = 0; i < d->ports; i++) {
326 if (c->port & (1 << i)) {
327 ports |= vlan_ports[i];
329 cfg = adm_rreg(0, port_conf[i]);
332 if (c->untag & (1 << i))
337 if ((c->untag | c->pvid) & (1 << i)) {
338 cfg = (cfg & ~(0xf << 10)) | (nr << 10);
341 adm_wreg(port_conf[i], (__u16) cfg);
343 ports &= ~(vlan_ports[i]);
346 adm_wreg(0x13 + nr, (__u16) ports);
351 static int handle_port_enable_read(void *driver, char *buf, int nr)
353 return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
356 static int handle_port_enable_write(void *driver, char *buf, int nr)
358 int reg = adm_rreg(0, port_conf[nr]);
362 else if (buf[0] == '1')
366 adm_wreg(port_conf[nr], (__u16) reg);
370 static int handle_port_media_read(void *driver, char *buf, int nr)
374 int reg = adm_rreg(0, port_conf[nr]);
377 media |= SWITCH_MEDIA_AUTO;
379 media |= SWITCH_MEDIA_100;
381 media |= SWITCH_MEDIA_FD;
383 len = switch_print_media(buf, media);
384 return len + sprintf(buf + len, "\n");
387 static int handle_port_media_write(void *driver, char *buf, int nr)
389 int media = switch_parse_media(buf);
390 int reg = adm_rreg(0, port_conf[nr]);
395 reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
396 if (media & SWITCH_MEDIA_AUTO)
398 if (media & SWITCH_MEDIA_100)
400 if (media & SWITCH_MEDIA_FD)
403 adm_wreg(port_conf[nr], reg);
408 static int handle_vlan_enable_read(void *driver, char *buf, int nr)
410 return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
413 static int handle_vlan_enable_write(void *driver, char *buf, int nr)
415 int reg = adm_rreg(0, 0x11);
419 else if (buf[0] == '0')
423 adm_wreg(0x11, (__u16) reg);
427 static int handle_reset(void *driver, char *buf, int nr)
433 * Reset sequence: RC high->low(100ms)->high(30ms)
435 * WAR: Certain boards don't have the correct power on
436 * reset logic therefore we must explicitly perform the
437 * sequence in software.
440 /* Keep RC high for at least 20ms */
441 adm_enout(eerc, eerc);
442 for (i = 0; i < 20; i ++)
444 /* Keep RC low for at least 100ms */
446 for (i = 0; i < 100; i++)
448 /* Set default configuration */
449 adm_enout((__u8)(eesk | eedi), eesk);
450 /* Keep RC high for at least 30ms */
451 adm_enout(eerc, eerc);
452 for (i = 0; i < 30; i++)
454 /* Leave RC high and disable GPIO outputs */
455 adm_disout((__u8)(eecs | eesk | eedi));
459 /* set up initial configuration for cpu port */
460 cfg = (0x8000 | /* Auto MDIX */
461 (0xf << 10) | /* PVID */
462 (1 << 4) | /* Tagging */
463 0xf); /* full duplex, 100Mbps, auto neg, flow ctrl */
464 adm_wreg(port_conf[5], cfg);
466 /* vlan mode select register (0x11): vlan on, mac clone */
467 adm_wreg(0x11, 0xff30);
472 static int handle_registers(void *driver, char *buf, int nr)
476 for (i = 0; i <= 0x33; i++) {
477 len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
483 static int handle_counters(void *driver, char *buf, int nr)
487 for (i = 0; i <= 0x3c; i++) {
488 len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
494 static int detect_adm(void)
499 int boardflags = atoi(nvram_get("boardflags"));
500 int boardnum = atoi(nvram_get("boardnum"));
502 if ((boardnum == 44) && (boardflags == 0x0388)) { /* Trendware TEW-411BRP+ */
505 eecs = get_gpiopin("adm_eecs", 2);
506 eesk = get_gpiopin("adm_eesk", 3);
507 eedi = get_gpiopin("adm_eedi", 4);
508 eerc = get_gpiopin("adm_rc", 5);
510 } else if ((boardflags & 0x80) || force) {
513 eecs = get_gpiopin("adm_eecs", 2);
514 eesk = get_gpiopin("adm_eesk", 3);
515 eedi = get_gpiopin("adm_eedi", 4);
516 eerc = get_gpiopin("adm_rc", 0);
518 } else if ((strcmp(nvram_get("boardtype") ?: "", "bcm94710dev") == 0) &&
519 (strncmp(nvram_get("boardnum") ?: "", "42", 2) == 0)) {
520 /* WRT54G v1.1 hack */
543 static int __init adm_init(void)
545 switch_config cfg[] = {
546 {"registers", handle_registers, NULL},
547 {"counters", handle_counters, NULL},
548 {"reset", NULL, handle_reset},
549 {"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
552 switch_config port[] = {
553 {"enable", handle_port_enable_read, handle_port_enable_write},
554 {"media", handle_port_media_read, handle_port_media_write},
557 switch_config vlan[] = {
558 {"ports", handle_vlan_port_read, handle_vlan_port_write},
561 switch_driver driver = {
563 version: DRIVER_VERSION,
568 driver_handlers: cfg,
576 return switch_register_driver(&driver);
579 static void __exit adm_exit(void)
581 switch_unregister_driver(DRIVER_NAME);
585 module_init(adm_init);
586 module_exit(adm_exit);