package/mac80211/patches/860-brcmsmac-backport.patch

   1 --- a/drivers/net/wireless/brcm80211/brcmsmac/Makefile
   2 +++ b/drivers/net/wireless/brcm80211/brcmsmac/Makefile
   3 @@ -39,10 +39,7 @@ BRCMSMAC_OFILES := \
   4         phy/phytbl_lcn.o \
   5         phy/phytbl_n.o \
   6         phy/phy_qmath.o \
   7 -       otp.o \
   8 -       srom.o \
   9         dma.o \
  10 -       nicpci.o \
  11         brcms_trace_events.o
  12
  13  MODULEPFX := brcmsmac
  14 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
  15 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
  16 @@ -22,7 +22,6 @@
  17  #include <linux/kernel.h>
  18  #include <linux/printk.h>
  19  #include <linux/delay.h>
  20 -#include <linux/pci.h>
  21
  22  #include <defs.h>
  23  #include <chipcommon.h>
  24 @@ -32,8 +31,6 @@
  25  #include "types.h"
  26  #include "pub.h"
  27  #include "pmu.h"
  28 -#include "srom.h"
  29 -#include "nicpci.h"
  30  #include "aiutils.h"
  31
  32  /* slow_clk_ctl */
  33 @@ -324,7 +321,6 @@
  34  #define        IS_SIM(chippkg) \
  35         ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  36
  37 -#define PCI(sih)       (ai_get_buscoretype(sih) == PCI_CORE_ID)
  38  #define PCIE(sih)      (ai_get_buscoretype(sih) == PCIE_CORE_ID)
  39
  40  #define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
  41 @@ -457,36 +453,9 @@ struct aidmp {
  42         u32 componentid3;       /* 0xffc */
  43  };
  44
  45 -/* return true if PCIE capability exists in the pci config space */
  46 -static bool ai_ispcie(struct si_info *sii)
  47 -{
  48 -       u8 cap_ptr;
  49 -
  50 -       cap_ptr =
  51 -           pcicore_find_pci_capability(sii->pcibus, PCI_CAP_ID_EXP, NULL,
  52 -                                       NULL);
  53 -       if (!cap_ptr)
  54 -               return false;
  55 -
  56 -       return true;
  57 -}
  58 -
  59 -static bool ai_buscore_prep(struct si_info *sii)
  60 -{
  61 -       /* kludge to enable the clock on the 4306 which lacks a slowclock */
  62 -       if (!ai_ispcie(sii))
  63 -               ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
  64 -       return true;
  65 -}
  66 -
  67  static bool
  68  ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
  69  {
  70 -       struct bcma_device *pci = NULL;
  71 -       struct bcma_device *pcie = NULL;
  72 -       struct bcma_device *core;
  73 -
  74 -
  75         /* no cores found, bail out */
  76         if (cc->bus->nr_cores == 0)
  77                 return false;
  78 @@ -495,8 +464,7 @@ ai_buscore_setup(struct si_info *sii, st
  79         sii->pub.ccrev = cc->id.rev;
  80
  81         /* get chipcommon chipstatus */
  82 -       if (ai_get_ccrev(&sii->pub) >= 11)
  83 -               sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
  84 +       sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
  85
  86         /* get chipcommon capabilites */
  87         sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
  88 @@ -509,64 +477,18 @@ ai_buscore_setup(struct si_info *sii, st
  89         }
  90
  91         /* figure out buscore */
  92 -       list_for_each_entry(core, &cc->bus->cores, list) {
  93 -               uint cid, crev;
  94 -
  95 -               cid = core->id.id;
  96 -               crev = core->id.rev;
  97 -
  98 -               if (cid == PCI_CORE_ID) {
  99 -                       pci = core;
 100 -               } else if (cid == PCIE_CORE_ID) {
 101 -                       pcie = core;
 102 -               }
 103 -       }
 104 -
 105 -       if (pci && pcie) {
 106 -               if (ai_ispcie(sii))
 107 -                       pci = NULL;
 108 -               else
 109 -                       pcie = NULL;
 110 -       }
 111 -       if (pci) {
 112 -               sii->buscore = pci;
 113 -       } else if (pcie) {
 114 -               sii->buscore = pcie;
 115 -       }
 116 -
 117 -       /* fixup necessary chip/core configurations */
 118 -       if (!sii->pch) {
 119 -               sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
 120 -               if (sii->pch == NULL)
 121 -                       return false;
 122 -       }
 123 -       if (ai_pci_fixcfg(&sii->pub))
 124 -               return false;
 125 +       sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
 126
 127         return true;
 128  }
 129
 130 -/*
 131 - * get boardtype and boardrev
 132 - */
 133 -static __used void ai_nvram_process(struct si_info *sii)
 134 -{
 135 -       uint w = 0;
 136 -
 137 -       /* do a pci config read to get subsystem id and subvendor id */
 138 -       pci_read_config_dword(sii->pcibus, PCI_SUBSYSTEM_VENDOR_ID, &w);
 139 -
 140 -       sii->pub.boardvendor = w & 0xffff;
 141 -       sii->pub.boardtype = (w >> 16) & 0xffff;
 142 -}
 143 -
 144  static struct si_info *ai_doattach(struct si_info *sii,
 145                                    struct bcma_bus *pbus)
 146  {
 147         struct si_pub *sih = &sii->pub;
 148         u32 w, savewin;
 149         struct bcma_device *cc;
 150 -       uint socitype;
 151 +       struct ssb_sprom *sprom = &pbus->sprom;
 152
 153         savewin = 0;
 154
 155 @@ -576,38 +498,15 @@ static struct si_info *ai_doattach(struc
 156         /* switch to Chipcommon core */
 157         cc = pbus->drv_cc.core;
 158
 159 -       /* bus/core/clk setup for register access */
 160 -       if (!ai_buscore_prep(sii))
 161 -               return NULL;
 162 +       sih->chip = pbus->chipinfo.id;
 163 +       sih->chiprev = pbus->chipinfo.rev;
 164 +       sih->chippkg = pbus->chipinfo.pkg;
 165 +       sih->boardvendor = pbus->boardinfo.vendor;
 166 +       sih->boardtype = pbus->boardinfo.type;
 167
 168 -       /*
 169 -        * ChipID recognition.
 170 -        *   We assume we can read chipid at offset 0 from the regs arg.
 171 -        *   If we add other chiptypes (or if we need to support old sdio
 172 -        *   hosts w/o chipcommon), some way of recognizing them needs to
 173 -        *   be added here.
 174 -        */
 175 -       w = bcma_read32(cc, CHIPCREGOFFS(chipid));
 176 -       socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
 177 -       /* Might as wll fill in chip id rev & pkg */
 178 -       sih->chip = w & CID_ID_MASK;
 179 -       sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
 180 -       sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
 181 -
 182 -       /* scan for cores */
 183 -       if (socitype != SOCI_AI)
 184 -               return NULL;
 185 -
 186 -       SI_MSG("Found chip type AI (0x%08x)\n", w);
 187         if (!ai_buscore_setup(sii, cc))
 188                 goto exit;
 189
 190 -       /* Init nvram from sprom/otp if they exist */
 191 -       if (srom_var_init(&sii->pub))
 192 -               goto exit;
 193 -
 194 -       ai_nvram_process(sii);
 195 -
 196         /* === NVRAM, clock is ready === */
 197         bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
 198         bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
 199 @@ -620,15 +519,13 @@ static struct si_info *ai_doattach(struc
 200         }
 201
 202         /* setup the GPIO based LED powersave register */
 203 -       w = getintvar(sih, BRCMS_SROM_LEDDC);
 204 +       w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
 205 +                (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
 206         if (w == 0)
 207                 w = DEFAULT_GPIOTIMERVAL;
 208         ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
 209                   ~0, w);
 210
 211 -       if (PCIE(sih))
 212 -               pcicore_attach(sii->pch, SI_DOATTACH);
 213 -
 214         if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
 215                 /*
 216                  * enable 12 mA drive strenth for 43224 and
 217 @@ -662,9 +559,6 @@ static struct si_info *ai_doattach(struc
 218         return sii;
 219
 220   exit:
 221 -       if (sii->pch)
 222 -               pcicore_deinit(sii->pch);
 223 -       sii->pch = NULL;
 224
 225         return NULL;
 226  }
 227 @@ -703,11 +597,6 @@ void ai_detach(struct si_pub *sih)
 228         if (sii == NULL)
 229                 return;
 230
 231 -       if (sii->pch)
 232 -               pcicore_deinit(sii->pch);
 233 -       sii->pch = NULL;
 234 -
 235 -       srom_free_vars(sih);
 236         kfree(sii);
 237  }
 238
 239 @@ -758,21 +647,7 @@ uint ai_cc_reg(struct si_pub *sih, uint
 240  /* return the slow clock source - LPO, XTAL, or PCI */
 241  static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
 242  {
 243 -       struct si_info *sii;
 244 -       u32 val;
 245 -
 246 -       sii = (struct si_info *)sih;
 247 -       if (ai_get_ccrev(&sii->pub) < 6) {
 248 -               pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
 249 -                                     &val);
 250 -               if (val & PCI_CFG_GPIO_SCS)
 251 -                       return SCC_SS_PCI;
 252 -               return SCC_SS_XTAL;
 253 -       } else if (ai_get_ccrev(&sii->pub) < 10) {
 254 -               return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
 255 -                      SCC_SS_MASK;
 256 -       } else                  /* Insta-clock */
 257 -               return SCC_SS_XTAL;
 258 +       return SCC_SS_XTAL;
 259  }
 260
 261  /*
 262 @@ -782,36 +657,12 @@ static uint ai_slowclk_src(struct si_pub
 263  static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
 264                             struct bcma_device *cc)
 265  {
 266 -       u32 slowclk;
 267         uint div;
 268
 269 -       slowclk = ai_slowclk_src(sih, cc);
 270 -       if (ai_get_ccrev(sih) < 6) {
 271 -               if (slowclk == SCC_SS_PCI)
 272 -                       return max_freq ? (PCIMAXFREQ / 64)
 273 -                               : (PCIMINFREQ / 64);
 274 -               else
 275 -                       return max_freq ? (XTALMAXFREQ / 32)
 276 -                               : (XTALMINFREQ / 32);
 277 -       } else if (ai_get_ccrev(sih) < 10) {
 278 -               div = 4 *
 279 -                   (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
 280 -                     SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
 281 -               if (slowclk == SCC_SS_LPO)
 282 -                       return max_freq ? LPOMAXFREQ : LPOMINFREQ;
 283 -               else if (slowclk == SCC_SS_XTAL)
 284 -                       return max_freq ? (XTALMAXFREQ / div)
 285 -                               : (XTALMINFREQ / div);
 286 -               else if (slowclk == SCC_SS_PCI)
 287 -                       return max_freq ? (PCIMAXFREQ / div)
 288 -                               : (PCIMINFREQ / div);
 289 -       } else {
 290 -               /* Chipc rev 10 is InstaClock */
 291 -               div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
 292 -               div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
 293 -               return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
 294 -       }
 295 -       return 0;
 296 +       /* Chipc rev 10 is InstaClock */
 297 +       div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
 298 +       div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
 299 +       return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
 300  }
 301
 302  static void
 303 @@ -834,8 +685,7 @@ ai_clkctl_setdelay(struct si_pub *sih, s
 304
 305         /* Starting with 4318 it is ILP that is used for the delays */
 306         slowmaxfreq =
 307 -           ai_slowclk_freq(sih,
 308 -                           (ai_get_ccrev(sih) >= 10) ? false : true, cc);
 309 +           ai_slowclk_freq(sih, false, cc);
 310
 311         pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
 312         fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
 313 @@ -857,9 +707,8 @@ void ai_clkctl_init(struct si_pub *sih)
 314                 return;
 315
 316         /* set all Instaclk chip ILP to 1 MHz */
 317 -       if (ai_get_ccrev(sih) >= 10)
 318 -               bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
 319 -                              (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
 320 +       bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
 321 +                      (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
 322
 323         ai_clkctl_setdelay(sih, cc);
 324  }
 325 @@ -894,140 +743,6 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
 326         return fpdelay;
 327  }
 328
 329 -/* turn primary xtal and/or pll off/on */
 330 -int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
 331 -{
 332 -       struct si_info *sii;
 333 -       u32 in, out, outen;
 334 -
 335 -       sii = (struct si_info *)sih;
 336 -
 337 -       /* pcie core doesn't have any mapping to control the xtal pu */
 338 -       if (PCIE(sih))
 339 -               return -1;
 340 -
 341 -       pci_read_config_dword(sii->pcibus, PCI_GPIO_IN, &in);
 342 -       pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, &out);
 343 -       pci_read_config_dword(sii->pcibus, PCI_GPIO_OUTEN, &outen);
 344 -
 345 -       /*
 346 -        * Avoid glitching the clock if GPRS is already using it.
 347 -        * We can't actually read the state of the PLLPD so we infer it
 348 -        * by the value of XTAL_PU which *is* readable via gpioin.
 349 -        */
 350 -       if (on && (in & PCI_CFG_GPIO_XTAL))
 351 -               return 0;
 352 -
 353 -       if (what & XTAL)
 354 -               outen |= PCI_CFG_GPIO_XTAL;
 355 -       if (what & PLL)
 356 -               outen |= PCI_CFG_GPIO_PLL;
 357 -
 358 -       if (on) {
 359 -               /* turn primary xtal on */
 360 -               if (what & XTAL) {
 361 -                       out |= PCI_CFG_GPIO_XTAL;
 362 -                       if (what & PLL)
 363 -                               out |= PCI_CFG_GPIO_PLL;
 364 -                       pci_write_config_dword(sii->pcibus,
 365 -                                              PCI_GPIO_OUT, out);
 366 -                       pci_write_config_dword(sii->pcibus,
 367 -                                              PCI_GPIO_OUTEN, outen);
 368 -                       udelay(XTAL_ON_DELAY);
 369 -               }
 370 -
 371 -               /* turn pll on */
 372 -               if (what & PLL) {
 373 -                       out &= ~PCI_CFG_GPIO_PLL;
 374 -                       pci_write_config_dword(sii->pcibus,
 375 -                                              PCI_GPIO_OUT, out);
 376 -                       mdelay(2);
 377 -               }
 378 -       } else {
 379 -               if (what & XTAL)
 380 -                       out &= ~PCI_CFG_GPIO_XTAL;
 381 -               if (what & PLL)
 382 -                       out |= PCI_CFG_GPIO_PLL;
 383 -               pci_write_config_dword(sii->pcibus,
 384 -                                      PCI_GPIO_OUT, out);
 385 -               pci_write_config_dword(sii->pcibus,
 386 -                                      PCI_GPIO_OUTEN, outen);
 387 -       }
 388 -
 389 -       return 0;
 390 -}
 391 -
 392 -/* clk control mechanism through chipcommon, no policy checking */
 393 -static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
 394 -{
 395 -       struct bcma_device *cc;
 396 -       u32 scc;
 397 -
 398 -       /* chipcommon cores prior to rev6 don't support dynamic clock control */
 399 -       if (ai_get_ccrev(&sii->pub) < 6)
 400 -               return false;
 401 -
 402 -       cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
 403 -
 404 -       if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
 405 -           (ai_get_ccrev(&sii->pub) < 20))
 406 -               return mode == CLK_FAST;
 407 -
 408 -       switch (mode) {
 409 -       case CLK_FAST:          /* FORCEHT, fast (pll) clock */
 410 -               if (ai_get_ccrev(&sii->pub) < 10) {
 411 -                       /*
 412 -                        * don't forget to force xtal back
 413 -                        * on before we clear SCC_DYN_XTAL..
 414 -                        */
 415 -                       ai_clkctl_xtal(&sii->pub, XTAL, ON);
 416 -                       bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
 417 -                                      (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
 418 -               } else if (ai_get_ccrev(&sii->pub) < 20) {
 419 -                       bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
 420 -               } else {
 421 -                       bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
 422 -               }
 423 -
 424 -               /* wait for the PLL */
 425 -               if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
 426 -                       u32 htavail = CCS_HTAVAIL;
 427 -                       SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) &
 428 -                                  htavail) == 0), PMU_MAX_TRANSITION_DLY);
 429 -               } else {
 430 -                       udelay(PLL_DELAY);
 431 -               }
 432 -               break;
 433 -
 434 -       case CLK_DYNAMIC:       /* enable dynamic clock control */
 435 -               if (ai_get_ccrev(&sii->pub) < 10) {
 436 -                       scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
 437 -                       scc &= ~(SCC_FS | SCC_IP | SCC_XC);
 438 -                       if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
 439 -                               scc |= SCC_XC;
 440 -                       bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
 441 -
 442 -                       /*
 443 -                        * for dynamic control, we have to
 444 -                        * release our xtal_pu "force on"
 445 -                        */
 446 -                       if (scc & SCC_XC)
 447 -                               ai_clkctl_xtal(&sii->pub, XTAL, OFF);
 448 -               } else if (ai_get_ccrev(&sii->pub) < 20) {
 449 -                       /* Instaclock */
 450 -                       bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
 451 -               } else {
 452 -                       bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
 453 -               }
 454 -               break;
 455 -
 456 -       default:
 457 -               break;
 458 -       }
 459 -
 460 -       return mode == CLK_FAST;
 461 -}
 462 -
 463  /*
 464   *  clock control policy function throught chipcommon
 465   *
 466 @@ -1036,133 +751,53 @@ static bool _ai_clkctl_cc(struct si_info
 467   *    this is a wrapper over the next internal function
 468   *      to allow flexible policy settings for outside caller
 469   */
 470 -bool ai_clkctl_cc(struct si_pub *sih, uint mode)
 471 +bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode)
 472  {
 473         struct si_info *sii;
 474 +       struct bcma_device *cc;
 475
 476         sii = (struct si_info *)sih;
 477
 478 -       /* chipcommon cores prior to rev6 don't support dynamic clock control */
 479 -       if (ai_get_ccrev(sih) < 6)
 480 -               return false;
 481 -
 482         if (PCI_FORCEHT(sih))
 483 -               return mode == CLK_FAST;
 484 +               return mode == BCMA_CLKMODE_FAST;
 485
 486 -       return _ai_clkctl_cc(sii, mode);
 487 +       cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
 488 +       bcma_core_set_clockmode(cc, mode);
 489 +       return mode == BCMA_CLKMODE_FAST;
 490  }
 491
 492  void ai_pci_up(struct si_pub *sih)
 493  {
 494         struct si_info *sii;
 495 +       struct bcma_device *cc;
 496
 497         sii = (struct si_info *)sih;
 498
 499 -       if (PCI_FORCEHT(sih))
 500 -               _ai_clkctl_cc(sii, CLK_FAST);
 501 +       if (PCI_FORCEHT(sih)) {
 502 +               cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
 503 +               bcma_core_set_clockmode(cc, BCMA_CLKMODE_FAST);
 504 +       }
 505
 506         if (PCIE(sih))
 507 -               pcicore_up(sii->pch, SI_PCIUP);
 508 -
 509 -}
 510 -
 511 -/* Unconfigure and/or apply various WARs when system is going to sleep mode */
 512 -void ai_pci_sleep(struct si_pub *sih)
 513 -{
 514 -       struct si_info *sii;
 515 -
 516 -       sii = (struct si_info *)sih;
 517 -
 518 -       pcicore_sleep(sii->pch);
 519 +               bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
 520  }
 521
 522  /* Unconfigure and/or apply various WARs when going down */
 523  void ai_pci_down(struct si_pub *sih)
 524  {
 525         struct si_info *sii;
 526 +       struct bcma_device *cc;
 527
 528         sii = (struct si_info *)sih;
 529
 530         /* release FORCEHT since chip is going to "down" state */
 531 -       if (PCI_FORCEHT(sih))
 532 -               _ai_clkctl_cc(sii, CLK_DYNAMIC);
 533 -
 534 -       pcicore_down(sii->pch, SI_PCIDOWN);
 535 -}
 536 -
 537 -/*
 538 - * Configure the pci core for pci client (NIC) action
 539 - * coremask is the bitvec of cores by index to be enabled.
 540 - */
 541 -void ai_pci_setup(struct si_pub *sih, uint coremask)
 542 -{
 543 -       struct si_info *sii;
 544 -       u32 w;
 545 -
 546 -       sii = (struct si_info *)sih;
 547 -
 548 -       /*
 549 -        * Enable sb->pci interrupts.  Assume
 550 -        * PCI rev 2.3 support was added in pci core rev 6 and things changed..
 551 -        */
 552 -       if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
 553 -               /* pci config write to set this core bit in PCIIntMask */
 554 -               pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
 555 -               w |= (coremask << PCI_SBIM_SHIFT);
 556 -               pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
 557 -       }
 558 -
 559 -       if (PCI(sih)) {
 560 -               pcicore_pci_setup(sii->pch);
 561 +       if (PCI_FORCEHT(sih)) {
 562 +               cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
 563 +               bcma_core_set_clockmode(cc, BCMA_CLKMODE_DYNAMIC);
 564         }
 565 -}
 566 -
 567 -/*
 568 - * Fixup SROMless PCI device's configuration.
 569 - * The current core may be changed upon return.
 570 - */
 571 -int ai_pci_fixcfg(struct si_pub *sih)
 572 -{
 573 -       struct si_info *sii = (struct si_info *)sih;
 574 -
 575 -       /* Fixup PI in SROM shadow area to enable the correct PCI core access */
 576 -       /* check 'pi' is correct and fix it if not */
 577 -       pcicore_fixcfg(sii->pch);
 578 -       pcicore_hwup(sii->pch);
 579 -       return 0;
 580 -}
 581 -
 582 -/* mask&set gpiocontrol bits */
 583 -u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
 584 -{
 585 -       uint regoff;
 586 -
 587 -       regoff = offsetof(struct chipcregs, gpiocontrol);
 588 -       return ai_cc_reg(sih, regoff, mask, val);
 589 -}
 590 -
 591 -void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
 592 -{
 593 -       struct bcma_device *cc;
 594 -       u32 val;
 595 -
 596 -       cc = ai_findcore(sih, CC_CORE_ID, 0);
 597
 598 -       if (on) {
 599 -               if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
 600 -                       /* Ext PA Controls for 4331 12x9 Package */
 601 -                       bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
 602 -                                  CCTRL4331_EXTPA_EN |
 603 -                                  CCTRL4331_EXTPA_ON_GPIO2_5);
 604 -               else
 605 -                       /* Ext PA Controls for 4331 12x12 Package */
 606 -                       bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
 607 -                                  CCTRL4331_EXTPA_EN);
 608 -       } else {
 609 -               val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
 610 -               bcma_mask32(cc, CHIPCREGOFFS(chipcontrol),
 611 -                           ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5));
 612 -       }
 613 +       if (PCIE(sih))
 614 +               bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
 615  }
 616
 617  /* Enable BT-COEX & Ex-PA for 4313 */
 618 @@ -1184,6 +819,9 @@ bool ai_deviceremoved(struct si_pub *sih
 619
 620         sii = (struct si_info *)sih;
 621
 622 +       if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
 623 +               return false;
 624 +
 625         pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);
 626         if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
 627                 return true;
 628 @@ -1191,45 +829,6 @@ bool ai_deviceremoved(struct si_pub *sih
 629         return false;
 630  }
 631
 632 -bool ai_is_sprom_available(struct si_pub *sih)
 633 -{
 634 -       struct si_info *sii = (struct si_info *)sih;
 635 -
 636 -       if (ai_get_ccrev(sih) >= 31) {
 637 -               struct bcma_device *cc;
 638 -               u32 sromctrl;
 639 -
 640 -               if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
 641 -                       return false;
 642 -
 643 -               cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
 644 -               sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol));
 645 -               return sromctrl & SRC_PRESENT;
 646 -       }
 647 -
 648 -       switch (ai_get_chip_id(sih)) {
 649 -       case BCM4313_CHIP_ID:
 650 -               return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
 651 -       default:
 652 -               return true;
 653 -       }
 654 -}
 655 -
 656 -bool ai_is_otp_disabled(struct si_pub *sih)
 657 -{
 658 -       struct si_info *sii = (struct si_info *)sih;
 659 -
 660 -       switch (ai_get_chip_id(sih)) {
 661 -       case BCM4313_CHIP_ID:
 662 -               return (sii->chipst & CST4313_OTP_PRESENT) == 0;
 663 -               /* These chips always have their OTP on */
 664 -       case BCM43224_CHIP_ID:
 665 -       case BCM43225_CHIP_ID:
 666 -       default:
 667 -               return false;
 668 -       }
 669 -}
 670 -
 671  uint ai_get_buscoretype(struct si_pub *sih)
 672  {
 673         struct si_info *sii = (struct si_info *)sih;
 674 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
 675 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
 676 @@ -113,10 +113,6 @@
 677  #define        XTAL                    0x1     /* primary crystal oscillator (2050) */
 678  #define        PLL                     0x2     /* main chip pll */
 679
 680 -/* clkctl clk mode */
 681 -#define        CLK_FAST                0       /* force fast (pll) clock */
 682 -#define        CLK_DYNAMIC             2       /* enable dynamic clock control */
 683 -
 684  /* GPIO usage priorities */
 685  #define GPIO_DRV_PRIORITY      0       /* Driver */
 686  #define GPIO_APP_PRIORITY      1       /* Application */
 687 @@ -172,9 +168,7 @@ struct si_info {
 688         struct si_pub pub;      /* back plane public state (must be first) */
 689         struct bcma_bus *icbus; /* handle to soc interconnect bus */
 690         struct pci_dev *pcibus; /* handle to pci bus */
 691 -       struct pcicore_info *pch; /* PCI/E core handle */
 692         struct bcma_device *buscore;
 693 -       struct list_head var_list; /* list of srom variables */
 694
 695         u32 chipst;             /* chip status */
 696  };
 697 @@ -197,38 +191,20 @@ extern u32 ai_core_cflags(struct bcma_de
 698  extern struct si_pub *ai_attach(struct bcma_bus *pbus);
 699  extern void ai_detach(struct si_pub *sih);
 700  extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
 701 -extern void ai_pci_setup(struct si_pub *sih, uint coremask);
 702  extern void ai_clkctl_init(struct si_pub *sih);
 703  extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
 704  extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
 705 -extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
 706  extern bool ai_deviceremoved(struct si_pub *sih);
 707 -extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
 708 -                            u8 priority);
 709 -
 710 -/* OTP status */
 711 -extern bool ai_is_otp_disabled(struct si_pub *sih);
 712 -
 713 -/* SPROM availability */
 714 -extern bool ai_is_sprom_available(struct si_pub *sih);
 715
 716 -extern void ai_pci_sleep(struct si_pub *sih);
 717  extern void ai_pci_down(struct si_pub *sih);
 718  extern void ai_pci_up(struct si_pub *sih);
 719 -extern int ai_pci_fixcfg(struct si_pub *sih);
 720
 721 -extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
 722  /* Enable Ex-PA for 4313 */
 723  extern void ai_epa_4313war(struct si_pub *sih);
 724
 725  extern uint ai_get_buscoretype(struct si_pub *sih);
 726  extern uint ai_get_buscorerev(struct si_pub *sih);
 727
 728 -static inline int ai_get_ccrev(struct si_pub *sih)
 729 -{
 730 -       return sih->ccrev;
 731 -}
 732 -
 733  static inline u32 ai_get_cccaps(struct si_pub *sih)
 734  {
 735         return sih->cccaps;
 736 --- a/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
 737 +++ b/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
 738 @@ -108,7 +108,7 @@ brcms_c_antsel_init_cfg(struct antsel_in
 739  struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
 740  {
 741         struct antsel_info *asi;
 742 -       struct si_pub *sih = wlc->hw->sih;
 743 +       struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
 744
 745         asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
 746         if (!asi)
 747 @@ -118,7 +118,7 @@ struct antsel_info *brcms_c_antsel_attac
 748         asi->pub = wlc->pub;
 749         asi->antsel_type = ANTSEL_NA;
 750         asi->antsel_avail = false;
 751 -       asi->antsel_antswitch = (u8) getintvar(sih, BRCMS_SROM_ANTSWITCH);
 752 +       asi->antsel_antswitch = sprom->antswitch;
 753
 754         if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
 755                 switch (asi->antsel_antswitch) {
 756 @@ -128,12 +128,12 @@ struct antsel_info *brcms_c_antsel_attac
 757                         /* 4321/2 board with 2x3 switch logic */
 758                         asi->antsel_type = ANTSEL_2x3;
 759                         /* Antenna selection availability */
 760 -                       if (((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) ||
 761 -                           ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 7)) {
 762 +                       if ((sprom->ant_available_bg == 7) ||
 763 +                           (sprom->ant_available_a == 7)) {
 764                                 asi->antsel_avail = true;
 765                         } else if (
 766 -                               (u16) getintvar(sih, BRCMS_SROM_AA2G) == 3 ||
 767 -                               (u16) getintvar(sih, BRCMS_SROM_AA5G) == 3) {
 768 +                               sprom->ant_available_bg == 3 ||
 769 +                               sprom->ant_available_a == 3) {
 770                                 asi->antsel_avail = false;
 771                         } else {
 772                                 asi->antsel_avail = false;
 773 @@ -146,8 +146,8 @@ struct antsel_info *brcms_c_antsel_attac
 774                         break;
 775                 }
 776         } else if ((asi->pub->sromrev == 4) &&
 777 -                  ((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) &&
 778 -                  ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 0)) {
 779 +                  (sprom->ant_available_bg == 7) &&
 780 +                  (sprom->ant_available_a == 0)) {
 781                 /* hack to match old 4321CB2 cards with 2of3 antenna switch */
 782                 asi->antsel_type = ANTSEL_2x3;
 783                 asi->antsel_avail = true;
 784 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
 785 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
 786 @@ -1110,7 +1110,7 @@ struct brcms_cm_info *brcms_c_channel_mg
 787         char country_abbrev[BRCM_CNTRY_BUF_SZ];
 788         const struct country_info *country;
 789         struct brcms_pub *pub = wlc->pub;
 790 -       char *ccode;
 791 +       struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
 792
 793         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
 794
 795 @@ -1122,9 +1122,8 @@ struct brcms_cm_info *brcms_c_channel_mg
 796         wlc->cmi = wlc_cm;
 797
 798         /* store the country code for passing up as a regulatory hint */
 799 -       ccode = getvar(wlc->hw->sih, BRCMS_SROM_CCODE);
 800 -       if (ccode && brcms_c_country_valid(ccode))
 801 -               strncpy(wlc->pub->srom_ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
 802 +       if (sprom->alpha2 && brcms_c_country_valid(sprom->alpha2))
 803 +               strncpy(wlc->pub->srom_ccode, sprom->alpha2, sizeof(sprom->alpha2));
 804
 805         /*
 806          * internal country information which must match
 807 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
 808 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
 809 @@ -28,7 +28,6 @@
 810  #include <linux/bcma/bcma.h>
 811  #include <net/mac80211.h>
 812  #include <defs.h>
 813 -#include "nicpci.h"
 814  #include "phy/phy_int.h"
 815  #include "d11.h"
 816  #include "channel.h"
 817 @@ -773,7 +772,7 @@ void brcms_dpc(unsigned long data)
 818   * Precondition: Since this function is called in brcms_pci_probe() context,
 819   * no locking is required.
 820   */
 821 -static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev)
 822 +static int brcms_request_fw(struct brcms_info *wl, struct bcma_device *pdev)
 823  {
 824         int status;
 825         struct device *device = &pdev->dev;
 826 @@ -1025,7 +1024,7 @@ static struct brcms_info *brcms_attach(s
 827         spin_lock_init(&wl->isr_lock);
 828
 829         /* prepare ucode */
 830 -       if (brcms_request_fw(wl, pdev->bus->host_pci) < 0) {
 831 +       if (brcms_request_fw(wl, pdev) < 0) {
 832                 wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
 833                           "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
 834                 brcms_release_fw(wl);
 835 @@ -1046,12 +1045,12 @@ static struct brcms_info *brcms_attach(s
 836         wl->pub->ieee_hw = hw;
 837
 838         /* register our interrupt handler */
 839 -       if (request_irq(pdev->bus->host_pci->irq, brcms_isr,
 840 +       if (request_irq(pdev->irq, brcms_isr,
 841                         IRQF_SHARED, KBUILD_MODNAME, wl)) {
 842                 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
 843                 goto fail;
 844         }
 845 -       wl->irq = pdev->bus->host_pci->irq;
 846 +       wl->irq = pdev->irq;
 847
 848         /* register module */
 849         brcms_c_module_register(wl->pub, "linux", wl, NULL);
 850 @@ -1101,7 +1100,7 @@ static int __devinit brcms_bcma_probe(st
 851
 852         dev_info(&pdev->dev, "mfg %x core %x rev %d class %d irq %d\n",
 853                  pdev->id.manuf, pdev->id.id, pdev->id.rev, pdev->id.class,
 854 -                pdev->bus->host_pci->irq);
 855 +                pdev->irq);
 856
 857         if ((pdev->id.manuf != BCMA_MANUF_BCM) ||
 858             (pdev->id.id != BCMA_CORE_80211))
 859 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
 860 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
 861 @@ -850,8 +850,7 @@ brcms_c_dotxstatus(struct brcms_c_info *
 862          */
 863         if (!(txs->status & TX_STATUS_AMPDU)
 864             && (txs->status & TX_STATUS_INTERMEDIATE)) {
 865 -               wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
 866 -                         __func__);
 867 +               BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
 868                 return false;
 869         }
 870
 871 @@ -1223,7 +1222,7 @@ static void brcms_b_wait_for_wake(struct
 872  }
 873
 874  /* control chip clock to save power, enable dynamic clock or force fast clock */
 875 -static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
 876 +static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
 877  {
 878         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
 879                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
 880 @@ -1233,7 +1232,7 @@ static void brcms_b_clkctl_clk(struct br
 881                  */
 882
 883                 if (wlc_hw->clk) {
 884 -                       if (mode == CLK_FAST) {
 885 +                       if (mode == BCMA_CLKMODE_FAST) {
 886                                 bcma_set32(wlc_hw->d11core,
 887                                            D11REGOFFS(clk_ctl_st),
 888                                            CCS_FORCEHT);
 889 @@ -1264,7 +1263,7 @@ static void brcms_b_clkctl_clk(struct br
 890                                         ~CCS_FORCEHT);
 891                         }
 892                 }
 893 -               wlc_hw->forcefastclk = (mode == CLK_FAST);
 894 +               wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
 895         } else {
 896
 897                 /* old chips w/o PMU, force HT through cc,
 898 @@ -1571,7 +1570,7 @@ void brcms_b_bw_set(struct brcms_hardwar
 899         /* request FAST clock if not on */
 900         fastclk = wlc_hw->forcefastclk;
 901         if (!fastclk)
 902 -               brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
 903 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
 904
 905         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
 906
 907 @@ -1580,7 +1579,7 @@ void brcms_b_bw_set(struct brcms_hardwar
 908
 909         /* restore the clk */
 910         if (!fastclk)
 911 -               brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
 912 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
 913  }
 914
 915  static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
 916 @@ -1886,27 +1885,20 @@ static bool brcms_c_validboardtype(struc
 917         return true;
 918  }
 919
 920 -static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
 921 +static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
 922  {
 923 -       enum brcms_srom_id var_id = BRCMS_SROM_MACADDR;
 924 -       char *macaddr;
 925 +       struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
 926
 927         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
 928 -       macaddr = getvar(wlc_hw->sih, var_id);
 929 -       if (macaddr != NULL)
 930 -               return macaddr;
 931 +       if (!is_zero_ether_addr(sprom->il0mac)) {
 932 +               memcpy(etheraddr, sprom->il0mac, 6);
 933 +               return;
 934 +       }
 935
 936         if (wlc_hw->_nbands > 1)
 937 -               var_id = BRCMS_SROM_ET1MACADDR;
 938 +               memcpy(etheraddr, sprom->et1mac, 6);
 939         else
 940 -               var_id = BRCMS_SROM_IL0MACADDR;
 941 -
 942 -       macaddr = getvar(wlc_hw->sih, var_id);
 943 -       if (macaddr == NULL)
 944 -               wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
 945 -                         "getvar(%d) not found\n", wlc_hw->unit, var_id);
 946 -
 947 -       return macaddr;
 948 +               memcpy(etheraddr, sprom->il0mac, 6);
 949  }
 950
 951  /* power both the pll and external oscillator on/off */
 952 @@ -1921,9 +1913,6 @@ static void brcms_b_xtal(struct brcms_ha
 953         if (!want && wlc_hw->pllreq)
 954                 return;
 955
 956 -       if (wlc_hw->sih)
 957 -               ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
 958 -
 959         wlc_hw->sbclk = want;
 960         if (!wlc_hw->sbclk) {
 961                 wlc_hw->clk = false;
 962 @@ -2008,7 +1997,7 @@ void brcms_b_corereset(struct brcms_hard
 963         /* request FAST clock if not on  */
 964         fastclk = wlc_hw->forcefastclk;
 965         if (!fastclk)
 966 -               brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
 967 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
 968
 969         /* reset the dma engines except first time thru */
 970         if (bcma_core_is_enabled(wlc_hw->d11core)) {
 971 @@ -2057,7 +2046,7 @@ void brcms_b_corereset(struct brcms_hard
 972         brcms_c_mctrl_reset(wlc_hw);
 973
 974         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
 975 -               brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
 976 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
 977
 978         brcms_b_phy_reset(wlc_hw);
 979
 980 @@ -2069,7 +2058,7 @@ void brcms_b_corereset(struct brcms_hard
 981
 982         /* restore the clk setting */
 983         if (!fastclk)
 984 -               brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
 985 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
 986  }
 987
 988  /* txfifo sizes needs to be modified(increased) since the newer cores
 989 @@ -2222,7 +2211,7 @@ static void brcms_c_gpio_init(struct brc
 990                 gm |= gc |= BOARD_GPIO_PACTRL;
 991
 992         /* apply to gpiocontrol register */
 993 -       ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
 994 +       bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
 995  }
 996
 997  static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
 998 @@ -3375,7 +3364,7 @@ static brcms_b_init(struct brcms_hardwar
 999         /* request FAST clock if not on */
1000         fastclk = wlc_hw->forcefastclk;
1001         if (!fastclk)
1002 -               brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1003 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1004
1005         /* disable interrupts */
1006         macintmask = brcms_intrsoff(wlc->wl);
1007 @@ -3409,7 +3398,7 @@ static brcms_b_init(struct brcms_hardwar
1008
1009         /* restore the clk */
1010         if (!fastclk)
1011 -               brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1012 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1013  }
1014
1015  static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
1016 @@ -4440,17 +4429,22 @@ static int brcms_b_attach(struct brcms_c
1017                           uint unit, bool piomode)
1018  {
1019         struct brcms_hardware *wlc_hw;
1020 -       char *macaddr = NULL;
1021         uint err = 0;
1022         uint j;
1023         bool wme = false;
1024         struct shared_phy_params sha_params;
1025         struct wiphy *wiphy = wlc->wiphy;
1026         struct pci_dev *pcidev = core->bus->host_pci;
1027 +       struct ssb_sprom *sprom = &core->bus->sprom;
1028
1029 -       BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
1030 -              pcidev->vendor,
1031 -              pcidev->device);
1032 +       if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
1033 +               BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
1034 +                      pcidev->vendor,
1035 +                      pcidev->device);
1036 +       else
1037 +               BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
1038 +                      core->bus->boardinfo.vendor,
1039 +                      core->bus->boardinfo.type);
1040
1041         wme = true;
1042
1043 @@ -4476,7 +4470,8 @@ static int brcms_b_attach(struct brcms_c
1044         }
1045
1046         /* verify again the device is supported */
1047 -       if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
1048 +       if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
1049 +           !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
1050                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
1051                         "vendor/device (0x%x/0x%x)\n",
1052                          unit, pcidev->vendor, pcidev->device);
1053 @@ -4484,8 +4479,13 @@ static int brcms_b_attach(struct brcms_c
1054                 goto fail;
1055         }
1056
1057 -       wlc_hw->vendorid = pcidev->vendor;
1058 -       wlc_hw->deviceid = pcidev->device;
1059 +       if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1060 +               wlc_hw->vendorid = pcidev->vendor;
1061 +               wlc_hw->deviceid = pcidev->device;
1062 +       } else {
1063 +               wlc_hw->vendorid = core->bus->boardinfo.vendor;
1064 +               wlc_hw->deviceid = core->bus->boardinfo.type;
1065 +       }
1066
1067         wlc_hw->d11core = core;
1068         wlc_hw->corerev = core->id.rev;
1069 @@ -4505,7 +4505,7 @@ static int brcms_b_attach(struct brcms_c
1070          *   is still false; But it will be called again inside wlc_corereset,
1071          *   after d11 is out of reset.
1072          */
1073 -       brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1074 +       brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1075         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1076
1077         if (!brcms_b_validate_chip_access(wlc_hw)) {
1078 @@ -4516,7 +4516,7 @@ static int brcms_b_attach(struct brcms_c
1079         }
1080
1081         /* get the board rev, used just below */
1082 -       j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV);
1083 +       j = sprom->board_rev;
1084         /* promote srom boardrev of 0xFF to 1 */
1085         if (j == BOARDREV_PROMOTABLE)
1086                 j = BOARDREV_PROMOTED;
1087 @@ -4529,11 +4529,9 @@ static int brcms_b_attach(struct brcms_c
1088                 err = 15;
1089                 goto fail;
1090         }
1091 -       wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV);
1092 -       wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih,
1093 -                                            BRCMS_SROM_BOARDFLAGS);
1094 -       wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
1095 -                                             BRCMS_SROM_BOARDFLAGS2);
1096 +       wlc_hw->sromrev = sprom->revision;
1097 +       wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
1098 +       wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
1099
1100         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1101                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
1102 @@ -4706,25 +4704,18 @@ static int brcms_b_attach(struct brcms_c
1103          */
1104
1105         /* init etheraddr state variables */
1106 -       macaddr = brcms_c_get_macaddr(wlc_hw);
1107 -       if (macaddr == NULL) {
1108 -               wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
1109 -                         unit);
1110 -               err = 21;
1111 -               goto fail;
1112 -       }
1113 -       if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
1114 -           is_broadcast_ether_addr(wlc_hw->etheraddr) ||
1115 +       brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
1116 +
1117 +       if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
1118             is_zero_ether_addr(wlc_hw->etheraddr)) {
1119 -               wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
1120 -                         unit, macaddr);
1121 +               wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
1122 +                         unit);
1123                 err = 22;
1124                 goto fail;
1125         }
1126
1127 -       BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1128 -              wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih),
1129 -              macaddr);
1130 +       BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
1131 +              wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
1132
1133         return err;
1134
1135 @@ -4774,16 +4765,16 @@ static bool brcms_c_attach_stf_ant_init(
1136         int aa;
1137         uint unit;
1138         int bandtype;
1139 -       struct si_pub *sih = wlc->hw->sih;
1140 +       struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
1141
1142         unit = wlc->pub->unit;
1143         bandtype = wlc->band->bandtype;
1144
1145         /* get antennas available */
1146         if (bandtype == BRCM_BAND_5G)
1147 -               aa = (s8) getintvar(sih, BRCMS_SROM_AA5G);
1148 +               aa = sprom->ant_available_a;
1149         else
1150 -               aa = (s8) getintvar(sih, BRCMS_SROM_AA2G);
1151 +               aa = sprom->ant_available_bg;
1152
1153         if ((aa < 1) || (aa > 15)) {
1154                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
1155 @@ -4803,9 +4794,9 @@ static bool brcms_c_attach_stf_ant_init(
1156
1157         /* Compute Antenna Gain */
1158         if (bandtype == BRCM_BAND_5G)
1159 -               wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1);
1160 +               wlc->band->antgain = sprom->antenna_gain.a1;
1161         else
1162 -               wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0);
1163 +               wlc->band->antgain = sprom->antenna_gain.a0;
1164
1165         brcms_c_attach_antgain_init(wlc);
1166
1167 @@ -4956,15 +4947,6 @@ static int brcms_b_detach(struct brcms_c
1168
1169         callbacks = 0;
1170
1171 -       if (wlc_hw->sih) {
1172 -               /*
1173 -                * detach interrupt sync mechanism since interrupt is disabled
1174 -                * and per-port interrupt object may has been freed. this must
1175 -                * be done before sb core switch
1176 -                */
1177 -               ai_pci_sleep(wlc_hw->sih);
1178 -       }
1179 -
1180         brcms_b_detach_dmapio(wlc_hw);
1181
1182         band = wlc_hw->band;
1183 @@ -5051,9 +5033,7 @@ static void brcms_b_hw_up(struct brcms_h
1184          */
1185         brcms_b_xtal(wlc_hw, ON);
1186         ai_clkctl_init(wlc_hw->sih);
1187 -       brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1188 -
1189 -       ai_pci_fixcfg(wlc_hw->sih);
1190 +       brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1191
1192         /*
1193          * TODO: test suspend/resume
1194 @@ -5082,8 +5062,6 @@ static void brcms_b_hw_up(struct brcms_h
1195
1196  static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
1197  {
1198 -       uint coremask;
1199 -
1200         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1201
1202         /*
1203 @@ -5092,15 +5070,14 @@ static int brcms_b_up_prep(struct brcms_
1204          */
1205         brcms_b_xtal(wlc_hw, ON);
1206         ai_clkctl_init(wlc_hw->sih);
1207 -       brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1208 +       brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1209
1210         /*
1211          * Configure pci/pcmcia here instead of in brcms_c_attach()
1212          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1213          */
1214 -       coremask = (1 << wlc_hw->wlc->core->coreidx);
1215 -
1216 -       ai_pci_setup(wlc_hw->sih, coremask);
1217 +       bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1218 +                             true);
1219
1220         /*
1221          * Need to read the hwradio status here to cover the case where the
1222 @@ -5130,7 +5107,7 @@ static int brcms_b_up_finish(struct brcm
1223         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1224
1225         /* FULLY enable dynamic power control and d11 core interrupt */
1226 -       brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1227 +       brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1228         brcms_intrson(wlc_hw->wlc->wl);
1229         return 0;
1230  }
1231 @@ -5271,7 +5248,7 @@ static int brcms_b_bmac_down_prep(struct
1232                 brcms_intrsoff(wlc_hw->wlc->wl);
1233
1234                 /* ensure we're running on the pll clock again */
1235 -               brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1236 +               brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1237         }
1238         /* down phy at the last of this stage */
1239         callbacks += wlc_phy_down(wlc_hw->band->pi);
1240 --- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
1241 +++ /dev/null
1242 @@ -1,826 +0,0 @@
1243 -/*
1244 - * Copyright (c) 2010 Broadcom Corporation
1245 - *
1246 - * Permission to use, copy, modify, and/or distribute this software for any
1247 - * purpose with or without fee is hereby granted, provided that the above
1248 - * copyright notice and this permission notice appear in all copies.
1249 - *
1250 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1251 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1252 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
1253 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1254 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
1255 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
1256 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1257 - */
1258 -
1259 -#include <linux/slab.h>
1260 -#include <linux/delay.h>
1261 -#include <linux/pci.h>
1262 -
1263 -#include <defs.h>
1264 -#include <soc.h>
1265 -#include <chipcommon.h>
1266 -#include "aiutils.h"
1267 -#include "pub.h"
1268 -#include "nicpci.h"
1269 -
1270 -/* SPROM offsets */
1271 -#define SRSH_ASPM_OFFSET               4       /* word 4 */
1272 -#define SRSH_ASPM_ENB                  0x18    /* bit 3, 4 */
1273 -#define SRSH_ASPM_L1_ENB               0x10    /* bit 4 */
1274 -#define SRSH_ASPM_L0s_ENB              0x8     /* bit 3 */
1275 -
1276 -#define SRSH_PCIE_MISC_CONFIG          5       /* word 5 */
1277 -#define SRSH_L23READY_EXIT_NOPERST     0x8000  /* bit 15 */
1278 -#define SRSH_CLKREQ_OFFSET_REV5                20      /* word 20 for srom rev <= 5 */
1279 -#define SRSH_CLKREQ_ENB                        0x0800  /* bit 11 */
1280 -#define SRSH_BD_OFFSET                  6      /* word 6 */
1281 -
1282 -/* chipcontrol */
1283 -#define CHIPCTRL_4321_PLL_DOWN         0x800000/* serdes PLL down override */
1284 -
1285 -/* MDIO control */
1286 -#define MDIOCTL_DIVISOR_MASK           0x7f    /* clock to be used on MDIO */
1287 -#define MDIOCTL_DIVISOR_VAL            0x2
1288 -#define MDIOCTL_PREAM_EN               0x80    /* Enable preamble sequnce */
1289 -#define MDIOCTL_ACCESS_DONE            0x100   /* Transaction complete */
1290 -
1291 -/* MDIO Data */
1292 -#define MDIODATA_MASK                  0x0000ffff      /* data 2 bytes */
1293 -#define MDIODATA_TA                    0x00020000      /* Turnaround */
1294 -
1295 -#define MDIODATA_REGADDR_SHF           18              /* Regaddr shift */
1296 -#define MDIODATA_REGADDR_MASK          0x007c0000      /* Regaddr Mask */
1297 -#define MDIODATA_DEVADDR_SHF           23      /* Physmedia devaddr shift */
1298 -#define MDIODATA_DEVADDR_MASK          0x0f800000
1299 -                                               /* Physmedia devaddr Mask */
1300 -
1301 -/* MDIO Data for older revisions < 10 */
1302 -#define MDIODATA_REGADDR_SHF_OLD       18      /* Regaddr shift */
1303 -#define MDIODATA_REGADDR_MASK_OLD      0x003c0000
1304 -                                               /* Regaddr Mask */
1305 -#define MDIODATA_DEVADDR_SHF_OLD       22      /* Physmedia devaddr shift  */
1306 -#define MDIODATA_DEVADDR_MASK_OLD      0x0fc00000
1307 -                                               /* Physmedia devaddr Mask */
1308 -
1309 -/* Transactions flags */
1310 -#define MDIODATA_WRITE                 0x10000000
1311 -#define MDIODATA_READ                  0x20000000
1312 -#define MDIODATA_START                 0x40000000
1313 -
1314 -#define MDIODATA_DEV_ADDR              0x0     /* dev address for serdes */
1315 -#define        MDIODATA_BLK_ADDR               0x1F    /* blk address for serdes */
1316 -
1317 -/* serdes regs (rev < 10) */
1318 -#define MDIODATA_DEV_PLL               0x1d    /* SERDES PLL Dev */
1319 -#define MDIODATA_DEV_TX                        0x1e    /* SERDES TX Dev */
1320 -#define MDIODATA_DEV_RX                        0x1f    /* SERDES RX Dev */
1321 -
1322 -/* SERDES RX registers */
1323 -#define SERDES_RX_CTRL                 1       /* Rx cntrl */
1324 -#define SERDES_RX_TIMER1               2       /* Rx Timer1 */
1325 -#define SERDES_RX_CDR                  6       /* CDR */
1326 -#define SERDES_RX_CDRBW                        7       /* CDR BW */
1327 -/* SERDES RX control register */
1328 -#define SERDES_RX_CTRL_FORCE           0x80    /* rxpolarity_force */
1329 -#define SERDES_RX_CTRL_POLARITY                0x40    /* rxpolarity_value */
1330 -
1331 -/* SERDES PLL registers */
1332 -#define SERDES_PLL_CTRL                 1      /* PLL control reg */
1333 -#define PLL_CTRL_FREQDET_EN             0x4000 /* bit 14 is FREQDET on */
1334 -
1335 -/* Linkcontrol reg offset in PCIE Cap */
1336 -#define PCIE_CAP_LINKCTRL_OFFSET       16      /* offset in pcie cap */
1337 -#define PCIE_CAP_LCREG_ASPML0s         0x01    /* ASPM L0s in linkctrl */
1338 -#define PCIE_CAP_LCREG_ASPML1          0x02    /* ASPM L1 in linkctrl */
1339 -#define PCIE_CLKREQ_ENAB               0x100   /* CLKREQ Enab in linkctrl */
1340 -
1341 -#define PCIE_ASPM_ENAB                 3       /* ASPM L0s & L1 in linkctrl */
1342 -#define PCIE_ASPM_L1_ENAB              2       /* ASPM L0s & L1 in linkctrl */
1343 -#define PCIE_ASPM_L0s_ENAB             1       /* ASPM L0s & L1 in linkctrl */
1344 -#define PCIE_ASPM_DISAB                        0       /* ASPM L0s & L1 in linkctrl */
1345 -
1346 -/* Power management threshold */
1347 -#define PCIE_L1THRESHOLDTIME_MASK       0xFF00 /* bits 8 - 15 */
1348 -#define PCIE_L1THRESHOLDTIME_SHIFT      8      /* PCIE_L1THRESHOLDTIME_SHIFT */
1349 -#define PCIE_L1THRESHOLD_WARVAL         0x72   /* WAR value */
1350 -#define PCIE_ASPMTIMER_EXTEND          0x01000000
1351 -                                               /* > rev7:
1352 -                                                * enable extend ASPM timer
1353 -                                                */
1354 -
1355 -/* different register spaces to access thru pcie indirect access */
1356 -#define PCIE_CONFIGREGS                1       /* Access to config space */
1357 -#define PCIE_PCIEREGS          2       /* Access to pcie registers */
1358 -
1359 -/* PCIE protocol PHY diagnostic registers */
1360 -#define        PCIE_PLP_STATUSREG              0x204   /* Status */
1361 -
1362 -/* Status reg PCIE_PLP_STATUSREG */
1363 -#define PCIE_PLP_POLARITYINV_STAT      0x10
1364 -
1365 -/* PCIE protocol DLLP diagnostic registers */
1366 -#define PCIE_DLLP_LCREG                        0x100   /* Link Control */
1367 -#define PCIE_DLLP_PMTHRESHREG          0x128   /* Power Management Threshold */
1368 -
1369 -/* PCIE protocol TLP diagnostic registers */
1370 -#define PCIE_TLP_WORKAROUNDSREG                0x004   /* TLP Workarounds */
1371 -
1372 -/* Sonics to PCI translation types */
1373 -#define        SBTOPCI_PREF    0x4             /* prefetch enable */
1374 -#define        SBTOPCI_BURST   0x8             /* burst enable */
1375 -#define        SBTOPCI_RC_READMULTI    0x20    /* memory read multiple */
1376 -
1377 -#define PCI_CLKRUN_DSBL        0x8000  /* Bit 15 forceClkrun */
1378 -
1379 -/* PCI core index in SROM shadow area */
1380 -#define SRSH_PI_OFFSET 0       /* first word */
1381 -#define SRSH_PI_MASK   0xf000  /* bit 15:12 */
1382 -#define SRSH_PI_SHIFT  12      /* bit 15:12 */
1383 -
1384 -#define PCIREGOFFS(field)      offsetof(struct sbpciregs, field)
1385 -#define PCIEREGOFFS(field)     offsetof(struct sbpcieregs, field)
1386 -
1387 -/* Sonics side: PCI core and host control registers */
1388 -struct sbpciregs {
1389 -       u32 control;            /* PCI control */
1390 -       u32 PAD[3];
1391 -       u32 arbcontrol;         /* PCI arbiter control */
1392 -       u32 clkrun;             /* Clkrun Control (>=rev11) */
1393 -       u32 PAD[2];
1394 -       u32 intstatus;          /* Interrupt status */
1395 -       u32 intmask;            /* Interrupt mask */
1396 -       u32 sbtopcimailbox;     /* Sonics to PCI mailbox */
1397 -       u32 PAD[9];
1398 -       u32 bcastaddr;          /* Sonics broadcast address */
1399 -       u32 bcastdata;          /* Sonics broadcast data */
1400 -       u32 PAD[2];
1401 -       u32 gpioin;             /* ro: gpio input (>=rev2) */
1402 -       u32 gpioout;            /* rw: gpio output (>=rev2) */
1403 -       u32 gpioouten;          /* rw: gpio output enable (>= rev2) */
1404 -       u32 gpiocontrol;        /* rw: gpio control (>= rev2) */
1405 -       u32 PAD[36];
1406 -       u32 sbtopci0;           /* Sonics to PCI translation 0 */
1407 -       u32 sbtopci1;           /* Sonics to PCI translation 1 */
1408 -       u32 sbtopci2;           /* Sonics to PCI translation 2 */
1409 -       u32 PAD[189];
1410 -       u32 pcicfg[4][64];      /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
1411 -       u16 sprom[36];          /* SPROM shadow Area */
1412 -       u32 PAD[46];
1413 -};
1414 -
1415 -/* SB side: PCIE core and host control registers */
1416 -struct sbpcieregs {
1417 -       u32 control;            /* host mode only */
1418 -       u32 PAD[2];
1419 -       u32 biststatus;         /* bist Status: 0x00C */
1420 -       u32 gpiosel;            /* PCIE gpio sel: 0x010 */
1421 -       u32 gpioouten;          /* PCIE gpio outen: 0x14 */
1422 -       u32 PAD[2];
1423 -       u32 intstatus;          /* Interrupt status: 0x20 */
1424 -       u32 intmask;            /* Interrupt mask: 0x24 */
1425 -       u32 sbtopcimailbox;     /* sb to pcie mailbox: 0x028 */
1426 -       u32 PAD[53];
1427 -       u32 sbtopcie0;          /* sb to pcie translation 0: 0x100 */
1428 -       u32 sbtopcie1;          /* sb to pcie translation 1: 0x104 */
1429 -       u32 sbtopcie2;          /* sb to pcie translation 2: 0x108 */
1430 -       u32 PAD[5];
1431 -
1432 -       /* pcie core supports in direct access to config space */
1433 -       u32 configaddr; /* pcie config space access: Address field: 0x120 */
1434 -       u32 configdata; /* pcie config space access: Data field: 0x124 */
1435 -
1436 -       /* mdio access to serdes */
1437 -       u32 mdiocontrol;        /* controls the mdio access: 0x128 */
1438 -       u32 mdiodata;           /* Data to the mdio access: 0x12c */
1439 -
1440 -       /* pcie protocol phy/dllp/tlp register indirect access mechanism */
1441 -       u32 pcieindaddr;        /* indirect access to
1442 -                                * the internal register: 0x130
1443 -                                */
1444 -       u32 pcieinddata;        /* Data to/from the internal regsiter: 0x134 */
1445 -
1446 -       u32 clkreqenctrl;       /* >= rev 6, Clkreq rdma control : 0x138 */
1447 -       u32 PAD[177];
1448 -       u32 pciecfg[4][64];     /* 0x400 - 0x7FF, PCIE Cfg Space */
1449 -       u16 sprom[64];          /* SPROM shadow Area */
1450 -};
1451 -
1452 -struct pcicore_info {
1453 -       struct bcma_device *core;
1454 -       struct si_pub *sih;     /* System interconnect handle */
1455 -       struct pci_dev *dev;
1456 -       u8 pciecap_lcreg_offset;/* PCIE capability LCreg offset
1457 -                                * in the config space
1458 -                                */
1459 -       bool pcie_pr42767;
1460 -       u8 pcie_polarity;
1461 -       u8 pcie_war_aspm_ovr;   /* Override ASPM/Clkreq settings */
1462 -
1463 -       u8 pmecap_offset;       /* PM Capability offset in the config space */
1464 -       bool pmecap;            /* Capable of generating PME */
1465 -};
1466 -
1467 -#define PCIE_ASPM(sih)                                                 \
1468 -       ((ai_get_buscoretype(sih) == PCIE_CORE_ID) &&                   \
1469 -        ((ai_get_buscorerev(sih) >= 3) &&                              \
1470 -         (ai_get_buscorerev(sih) <= 5)))
1471 -
1472 -
1473 -/* delay needed between the mdio control/ mdiodata register data access */
1474 -static void pr28829_delay(void)
1475 -{
1476 -       udelay(10);
1477 -}
1478 -
1479 -/* Initialize the PCI core.
1480 - * It's caller's responsibility to make sure that this is done only once
1481 - */
1482 -struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
1483 -{
1484 -       struct pcicore_info *pi;
1485 -
1486 -       /* alloc struct pcicore_info */
1487 -       pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
1488 -       if (pi == NULL)
1489 -               return NULL;
1490 -
1491 -       pi->sih = sih;
1492 -       pi->dev = core->bus->host_pci;
1493 -       pi->core = core;
1494 -
1495 -       if (core->id.id == PCIE_CORE_ID) {
1496 -               u8 cap_ptr;
1497 -               cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
1498 -                                                     NULL, NULL);
1499 -               pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
1500 -       }
1501 -       return pi;
1502 -}
1503 -
1504 -void pcicore_deinit(struct pcicore_info *pch)
1505 -{
1506 -       kfree(pch);
1507 -}
1508 -
1509 -/* return cap_offset if requested capability exists in the PCI config space */
1510 -/* Note that it's caller's responsibility to make sure it's a pci bus */
1511 -u8
1512 -pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
1513 -                           unsigned char *buf, u32 *buflen)
1514 -{
1515 -       u8 cap_id;
1516 -       u8 cap_ptr = 0;
1517 -       u32 bufsize;
1518 -       u8 byte_val;
1519 -
1520 -       /* check for Header type 0 */
1521 -       pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
1522 -       if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1523 -               goto end;
1524 -
1525 -       /* check if the capability pointer field exists */
1526 -       pci_read_config_byte(dev, PCI_STATUS, &byte_val);
1527 -       if (!(byte_val & PCI_STATUS_CAP_LIST))
1528 -               goto end;
1529 -
1530 -       pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
1531 -       /* check if the capability pointer is 0x00 */
1532 -       if (cap_ptr == 0x00)
1533 -               goto end;
1534 -
1535 -       /* loop thru the capability list
1536 -        * and see if the pcie capability exists
1537 -        */
1538 -
1539 -       pci_read_config_byte(dev, cap_ptr, &cap_id);
1540 -
1541 -       while (cap_id != req_cap_id) {
1542 -               pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
1543 -               if (cap_ptr == 0x00)
1544 -                       break;
1545 -               pci_read_config_byte(dev, cap_ptr, &cap_id);
1546 -       }
1547 -       if (cap_id != req_cap_id)
1548 -               goto end;
1549 -
1550 -       /* found the caller requested capability */
1551 -       if (buf != NULL && buflen != NULL) {
1552 -               u8 cap_data;
1553 -
1554 -               bufsize = *buflen;
1555 -               if (!bufsize)
1556 -                       goto end;
1557 -               *buflen = 0;
1558 -               /* copy the capability data excluding cap ID and next ptr */
1559 -               cap_data = cap_ptr + 2;
1560 -               if ((bufsize + cap_data) > PCI_SZPCR)
1561 -                       bufsize = PCI_SZPCR - cap_data;
1562 -               *buflen = bufsize;
1563 -               while (bufsize--) {
1564 -                       pci_read_config_byte(dev, cap_data, buf);
1565 -                       cap_data++;
1566 -                       buf++;
1567 -               }
1568 -       }
1569 -end:
1570 -       return cap_ptr;
1571 -}
1572 -
1573 -/* ***** Register Access API */
1574 -static uint
1575 -pcie_readreg(struct bcma_device *core, uint addrtype, uint offset)
1576 -{
1577 -       uint retval = 0xFFFFFFFF;
1578 -
1579 -       switch (addrtype) {
1580 -       case PCIE_CONFIGREGS:
1581 -               bcma_write32(core, PCIEREGOFFS(configaddr), offset);
1582 -               (void)bcma_read32(core, PCIEREGOFFS(configaddr));
1583 -               retval = bcma_read32(core, PCIEREGOFFS(configdata));
1584 -               break;
1585 -       case PCIE_PCIEREGS:
1586 -               bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
1587 -               (void)bcma_read32(core, PCIEREGOFFS(pcieindaddr));
1588 -               retval = bcma_read32(core, PCIEREGOFFS(pcieinddata));
1589 -               break;
1590 -       }
1591 -
1592 -       return retval;
1593 -}
1594 -
1595 -static uint pcie_writereg(struct bcma_device *core, uint addrtype,
1596 -                         uint offset, uint val)
1597 -{
1598 -       switch (addrtype) {
1599 -       case PCIE_CONFIGREGS:
1600 -               bcma_write32(core, PCIEREGOFFS(configaddr), offset);
1601 -               bcma_write32(core, PCIEREGOFFS(configdata), val);
1602 -               break;
1603 -       case PCIE_PCIEREGS:
1604 -               bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
1605 -               bcma_write32(core, PCIEREGOFFS(pcieinddata), val);
1606 -               break;
1607 -       default:
1608 -               break;
1609 -       }
1610 -       return 0;
1611 -}
1612 -
1613 -static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
1614 -{
1615 -       uint mdiodata, i = 0;
1616 -       uint pcie_serdes_spinwait = 200;
1617 -
1618 -       mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
1619 -                   (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
1620 -                   (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
1621 -                   (blk << 4));
1622 -       bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
1623 -
1624 -       pr28829_delay();
1625 -       /* retry till the transaction is complete */
1626 -       while (i < pcie_serdes_spinwait) {
1627 -               if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
1628 -                   MDIOCTL_ACCESS_DONE)
1629 -                       break;
1630 -
1631 -               udelay(1000);
1632 -               i++;
1633 -       }
1634 -
1635 -       if (i >= pcie_serdes_spinwait)
1636 -               return false;
1637 -
1638 -       return true;
1639 -}
1640 -
1641 -static int
1642 -pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
1643 -           uint *val)
1644 -{
1645 -       uint mdiodata;
1646 -       uint i = 0;
1647 -       uint pcie_serdes_spinwait = 10;
1648 -
1649 -       /* enable mdio access to SERDES */
1650 -       bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol),
1651 -                    MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
1652 -
1653 -       if (ai_get_buscorerev(pi->sih) >= 10) {
1654 -               /* new serdes is slower in rw,
1655 -                * using two layers of reg address mapping
1656 -                */
1657 -               if (!pcie_mdiosetblock(pi, physmedia))
1658 -                       return 1;
1659 -               mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
1660 -                           (regaddr << MDIODATA_REGADDR_SHF));
1661 -               pcie_serdes_spinwait *= 20;
1662 -       } else {
1663 -               mdiodata = ((physmedia << MDIODATA_DEVADDR_SHF_OLD) |
1664 -                           (regaddr << MDIODATA_REGADDR_SHF_OLD));
1665 -       }
1666 -
1667 -       if (!write)
1668 -               mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
1669 -       else
1670 -               mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
1671 -                            *val);
1672 -
1673 -       bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
1674 -
1675 -       pr28829_delay();
1676 -
1677 -       /* retry till the transaction is complete */
1678 -       while (i < pcie_serdes_spinwait) {
1679 -               if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
1680 -                   MDIOCTL_ACCESS_DONE) {
1681 -                       if (!write) {
1682 -                               pr28829_delay();
1683 -                               *val = (bcma_read32(pi->core,
1684 -                                                   PCIEREGOFFS(mdiodata)) &
1685 -                                       MDIODATA_MASK);
1686 -                       }
1687 -                       /* Disable mdio access to SERDES */
1688 -                       bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
1689 -                       return 0;
1690 -               }
1691 -               udelay(1000);
1692 -               i++;
1693 -       }
1694 -
1695 -       /* Timed out. Disable mdio access to SERDES. */
1696 -       bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
1697 -       return 1;
1698 -}
1699 -
1700 -/* use the mdio interface to read from mdio slaves */
1701 -static int
1702 -pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint regaddr,
1703 -             uint *regval)
1704 -{
1705 -       return pcie_mdioop(pi, physmedia, regaddr, false, regval);
1706 -}
1707 -
1708 -/* use the mdio interface to write to mdio slaves */
1709 -static int
1710 -pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
1711 -{
1712 -       return pcie_mdioop(pi, physmedia, regaddr, true, &val);
1713 -}
1714 -
1715 -/* ***** Support functions ***** */
1716 -static u8 pcie_clkreq(struct pcicore_info *pi, u32 mask, u32 val)
1717 -{
1718 -       u32 reg_val;
1719 -       u8 offset;
1720 -
1721 -       offset = pi->pciecap_lcreg_offset;
1722 -       if (!offset)
1723 -               return 0;
1724 -
1725 -       pci_read_config_dword(pi->dev, offset, &reg_val);
1726 -       /* set operation */
1727 -       if (mask) {
1728 -               if (val)
1729 -                       reg_val |= PCIE_CLKREQ_ENAB;
1730 -               else
1731 -                       reg_val &= ~PCIE_CLKREQ_ENAB;
1732 -               pci_write_config_dword(pi->dev, offset, reg_val);
1733 -               pci_read_config_dword(pi->dev, offset, &reg_val);
1734 -       }
1735 -       if (reg_val & PCIE_CLKREQ_ENAB)
1736 -               return 1;
1737 -       else
1738 -               return 0;
1739 -}
1740 -
1741 -static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
1742 -{
1743 -       u32 w;
1744 -       struct si_pub *sih = pi->sih;
1745 -
1746 -       if (ai_get_buscoretype(sih) != PCIE_CORE_ID ||
1747 -           ai_get_buscorerev(sih) < 7)
1748 -               return;
1749 -
1750 -       w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
1751 -       if (extend)
1752 -               w |= PCIE_ASPMTIMER_EXTEND;
1753 -       else
1754 -               w &= ~PCIE_ASPMTIMER_EXTEND;
1755 -       pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
1756 -       w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
1757 -}
1758 -
1759 -/* centralized clkreq control policy */
1760 -static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
1761 -{
1762 -       struct si_pub *sih = pi->sih;
1763 -
1764 -       switch (state) {
1765 -       case SI_DOATTACH:
1766 -               if (PCIE_ASPM(sih))
1767 -                       pcie_clkreq(pi, 1, 0);
1768 -               break;
1769 -       case SI_PCIDOWN:
1770 -               /* turn on serdes PLL down */
1771 -               if (ai_get_buscorerev(sih) == 6) {
1772 -                       ai_cc_reg(sih,
1773 -                                 offsetof(struct chipcregs, chipcontrol_addr),
1774 -                                 ~0, 0);
1775 -                       ai_cc_reg(sih,
1776 -                                 offsetof(struct chipcregs, chipcontrol_data),
1777 -                                 ~0x40, 0);
1778 -               } else if (pi->pcie_pr42767) {
1779 -                       pcie_clkreq(pi, 1, 1);
1780 -               }
1781 -               break;
1782 -       case SI_PCIUP:
1783 -               /* turn off serdes PLL down */
1784 -               if (ai_get_buscorerev(sih) == 6) {
1785 -                       ai_cc_reg(sih,
1786 -                                 offsetof(struct chipcregs, chipcontrol_addr),
1787 -                                 ~0, 0);
1788 -                       ai_cc_reg(sih,
1789 -                                 offsetof(struct chipcregs, chipcontrol_data),
1790 -                                 ~0x40, 0x40);
1791 -               } else if (PCIE_ASPM(sih)) {    /* disable clkreq */
1792 -                       pcie_clkreq(pi, 1, 0);
1793 -               }
1794 -               break;
1795 -       }
1796 -}
1797 -
1798 -/* ***** PCI core WARs ***** */
1799 -/* Done only once at attach time */
1800 -static void pcie_war_polarity(struct pcicore_info *pi)
1801 -{
1802 -       u32 w;
1803 -
1804 -       if (pi->pcie_polarity != 0)
1805 -               return;
1806 -
1807 -       w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
1808 -
1809 -       /* Detect the current polarity at attach and force that polarity and
1810 -        * disable changing the polarity
1811 -        */
1812 -       if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
1813 -               pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
1814 -       else
1815 -               pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
1816 -                                    SERDES_RX_CTRL_POLARITY);
1817 -}
1818 -
1819 -/* enable ASPM and CLKREQ if srom doesn't have it */
1820 -/* Needs to happen when update to shadow SROM is needed
1821 - *   : Coming out of 'standby'/'hibernate'
1822 - *   : If pcie_war_aspm_ovr state changed
1823 - */
1824 -static void pcie_war_aspm_clkreq(struct pcicore_info *pi)
1825 -{
1826 -       struct si_pub *sih = pi->sih;
1827 -       u16 val16;
1828 -       u32 w;
1829 -
1830 -       if (!PCIE_ASPM(sih))
1831 -               return;
1832 -
1833 -       /* bypass this on QT or VSIM */
1834 -       val16 = bcma_read16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]));
1835 -
1836 -       val16 &= ~SRSH_ASPM_ENB;
1837 -       if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
1838 -               val16 |= SRSH_ASPM_ENB;
1839 -       else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
1840 -               val16 |= SRSH_ASPM_L1_ENB;
1841 -       else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
1842 -               val16 |= SRSH_ASPM_L0s_ENB;
1843 -
1844 -       bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]), val16);
1845 -
1846 -       pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
1847 -       w &= ~PCIE_ASPM_ENAB;
1848 -       w |= pi->pcie_war_aspm_ovr;
1849 -       pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
1850 -
1851 -       val16 = bcma_read16(pi->core,
1852 -                           PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]));
1853 -
1854 -       if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
1855 -               val16 |= SRSH_CLKREQ_ENB;
1856 -               pi->pcie_pr42767 = true;
1857 -       } else
1858 -               val16 &= ~SRSH_CLKREQ_ENB;
1859 -
1860 -       bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]),
1861 -                    val16);
1862 -}
1863 -
1864 -/* Apply the polarity determined at the start */
1865 -/* Needs to happen when coming out of 'standby'/'hibernate' */
1866 -static void pcie_war_serdes(struct pcicore_info *pi)
1867 -{
1868 -       u32 w = 0;
1869 -
1870 -       if (pi->pcie_polarity != 0)
1871 -               pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
1872 -                              pi->pcie_polarity);
1873 -
1874 -       pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
1875 -       if (w & PLL_CTRL_FREQDET_EN) {
1876 -               w &= ~PLL_CTRL_FREQDET_EN;
1877 -               pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
1878 -       }
1879 -}
1880 -
1881 -/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
1882 -/* Needs to happen when coming out of 'standby'/'hibernate' */
1883 -static void pcie_misc_config_fixup(struct pcicore_info *pi)
1884 -{
1885 -       u16 val16;
1886 -
1887 -       val16 = bcma_read16(pi->core,
1888 -                           PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]));
1889 -
1890 -       if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
1891 -               val16 |= SRSH_L23READY_EXIT_NOPERST;
1892 -               bcma_write16(pi->core,
1893 -                            PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]), val16);
1894 -       }
1895 -}
1896 -
1897 -/* quick hack for testing */
1898 -/* Needs to happen when coming out of 'standby'/'hibernate' */
1899 -static void pcie_war_noplldown(struct pcicore_info *pi)
1900 -{
1901 -       /* turn off serdes PLL down */
1902 -       ai_cc_reg(pi->sih, offsetof(struct chipcregs, chipcontrol),
1903 -                 CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
1904 -
1905 -       /* clear srom shadow backdoor */
1906 -       bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_BD_OFFSET]), 0);
1907 -}
1908 -
1909 -/* Needs to happen when coming out of 'standby'/'hibernate' */
1910 -static void pcie_war_pci_setup(struct pcicore_info *pi)
1911 -{
1912 -       struct si_pub *sih = pi->sih;
1913 -       u32 w;
1914 -
1915 -       if (ai_get_buscorerev(sih) == 0 || ai_get_buscorerev(sih) == 1) {
1916 -               w = pcie_readreg(pi->core, PCIE_PCIEREGS,
1917 -                                PCIE_TLP_WORKAROUNDSREG);
1918 -               w |= 0x8;
1919 -               pcie_writereg(pi->core, PCIE_PCIEREGS,
1920 -                             PCIE_TLP_WORKAROUNDSREG, w);
1921 -       }
1922 -
1923 -       if (ai_get_buscorerev(sih) == 1) {
1924 -               w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
1925 -               w |= 0x40;
1926 -               pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
1927 -       }
1928 -
1929 -       if (ai_get_buscorerev(sih) == 0) {
1930 -               pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
1931 -               pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
1932 -               pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
1933 -       } else if (PCIE_ASPM(sih)) {
1934 -               /* Change the L1 threshold for better performance */
1935 -               w = pcie_readreg(pi->core, PCIE_PCIEREGS,
1936 -                                PCIE_DLLP_PMTHRESHREG);
1937 -               w &= ~PCIE_L1THRESHOLDTIME_MASK;
1938 -               w |= PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT;
1939 -               pcie_writereg(pi->core, PCIE_PCIEREGS,
1940 -                             PCIE_DLLP_PMTHRESHREG, w);
1941 -
1942 -               pcie_war_serdes(pi);
1943 -
1944 -               pcie_war_aspm_clkreq(pi);
1945 -       } else if (ai_get_buscorerev(pi->sih) == 7)
1946 -               pcie_war_noplldown(pi);
1947 -
1948 -       /* Note that the fix is actually in the SROM,
1949 -        * that's why this is open-ended
1950 -        */
1951 -       if (ai_get_buscorerev(pi->sih) >= 6)
1952 -               pcie_misc_config_fixup(pi);
1953 -}
1954 -
1955 -/* ***** Functions called during driver state changes ***** */
1956 -void pcicore_attach(struct pcicore_info *pi, int state)
1957 -{
1958 -       struct si_pub *sih = pi->sih;
1959 -       u32 bfl2 = (u32)getintvar(sih, BRCMS_SROM_BOARDFLAGS2);
1960 -
1961 -       /* Determine if this board needs override */
1962 -       if (PCIE_ASPM(sih)) {
1963 -               if (bfl2 & BFL2_PCIEWAR_OVR)
1964 -                       pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
1965 -               else
1966 -                       pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
1967 -       }
1968 -
1969 -       /* These need to happen in this order only */
1970 -       pcie_war_polarity(pi);
1971 -
1972 -       pcie_war_serdes(pi);
1973 -
1974 -       pcie_war_aspm_clkreq(pi);
1975 -
1976 -       pcie_clkreq_upd(pi, state);
1977 -
1978 -}
1979 -
1980 -void pcicore_hwup(struct pcicore_info *pi)
1981 -{
1982 -       if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
1983 -               return;
1984 -
1985 -       pcie_war_pci_setup(pi);
1986 -}
1987 -
1988 -void pcicore_up(struct pcicore_info *pi, int state)
1989 -{
1990 -       if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
1991 -               return;
1992 -
1993 -       /* Restore L1 timer for better performance */
1994 -       pcie_extendL1timer(pi, true);
1995 -
1996 -       pcie_clkreq_upd(pi, state);
1997 -}
1998 -
1999 -/* When the device is going to enter D3 state
2000 - * (or the system is going to enter S3/S4 states)
2001 - */
2002 -void pcicore_sleep(struct pcicore_info *pi)
2003 -{
2004 -       u32 w;
2005 -
2006 -       if (!pi || !PCIE_ASPM(pi->sih))
2007 -               return;
2008 -
2009 -       pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
2010 -       w &= ~PCIE_CAP_LCREG_ASPML1;
2011 -       pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
2012 -
2013 -       pi->pcie_pr42767 = false;
2014 -}
2015 -
2016 -void pcicore_down(struct pcicore_info *pi, int state)
2017 -{
2018 -       if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
2019 -               return;
2020 -
2021 -       pcie_clkreq_upd(pi, state);
2022 -
2023 -       /* Reduce L1 timer for better power savings */
2024 -       pcie_extendL1timer(pi, false);
2025 -}
2026 -
2027 -void pcicore_fixcfg(struct pcicore_info *pi)
2028 -{
2029 -       struct bcma_device *core = pi->core;
2030 -       u16 val16;
2031 -       uint regoff;
2032 -
2033 -       switch (pi->core->id.id) {
2034 -       case BCMA_CORE_PCI:
2035 -               regoff = PCIREGOFFS(sprom[SRSH_PI_OFFSET]);
2036 -               break;
2037 -
2038 -       case BCMA_CORE_PCIE:
2039 -               regoff = PCIEREGOFFS(sprom[SRSH_PI_OFFSET]);
2040 -               break;
2041 -
2042 -       default:
2043 -               return;
2044 -       }
2045 -
2046 -       val16 = bcma_read16(pi->core, regoff);
2047 -       if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) !=
2048 -           (u16)core->core_index) {
2049 -               val16 = ((u16)core->core_index << SRSH_PI_SHIFT) |
2050 -                       (val16 & ~SRSH_PI_MASK);
2051 -               bcma_write16(pi->core, regoff, val16);
2052 -       }
2053 -}
2054 -
2055 -/* precondition: current core is pci core */
2056 -void
2057 -pcicore_pci_setup(struct pcicore_info *pi)
2058 -{
2059 -       bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
2060 -                  SBTOPCI_PREF | SBTOPCI_BURST);
2061 -
2062 -       if (pi->core->id.rev >= 11) {
2063 -               bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
2064 -                          SBTOPCI_RC_READMULTI);
2065 -               bcma_set32(pi->core, PCIREGOFFS(clkrun), PCI_CLKRUN_DSBL);
2066 -               (void)bcma_read32(pi->core, PCIREGOFFS(clkrun));
2067 -       }
2068 -}
2069 --- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
2070 +++ /dev/null
2071 @@ -1,77 +0,0 @@
2072 -/*
2073 - * Copyright (c) 2010 Broadcom Corporation
2074 - *
2075 - * Permission to use, copy, modify, and/or distribute this software for any
2076 - * purpose with or without fee is hereby granted, provided that the above
2077 - * copyright notice and this permission notice appear in all copies.
2078 - *
2079 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
2080 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
2081 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
2082 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
2083 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
2084 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
2085 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2086 - */
2087 -
2088 -#ifndef        _BRCM_NICPCI_H_
2089 -#define        _BRCM_NICPCI_H_
2090 -
2091 -#include "types.h"
2092 -
2093 -/* PCI configuration address space size */
2094 -#define PCI_SZPCR              256
2095 -
2096 -/* Brcm PCI configuration registers */
2097 -/* backplane address space accessed by BAR0 */
2098 -#define PCI_BAR0_WIN           0x80
2099 -/* sprom property control */
2100 -#define PCI_SPROM_CONTROL      0x88
2101 -/* mask of PCI and other cores interrupts */
2102 -#define PCI_INT_MASK           0x94
2103 -/* backplane core interrupt mask bits offset */
2104 -#define  PCI_SBIM_SHIFT                8
2105 -/* backplane address space accessed by second 4KB of BAR0 */
2106 -#define PCI_BAR0_WIN2          0xac
2107 -/* pci config space gpio input (>=rev3) */
2108 -#define PCI_GPIO_IN            0xb0
2109 -/* pci config space gpio output (>=rev3) */
2110 -#define PCI_GPIO_OUT           0xb4
2111 -/* pci config space gpio output enable (>=rev3) */
2112 -#define PCI_GPIO_OUTEN         0xb8
2113 -
2114 -/* bar0 + 4K accesses external sprom */
2115 -#define PCI_BAR0_SPROM_OFFSET  (4 * 1024)
2116 -/* bar0 + 6K accesses pci core registers */
2117 -#define PCI_BAR0_PCIREGS_OFFSET        (6 * 1024)
2118 -/*
2119 - * pci core SB registers are at the end of the
2120 - * 8KB window, so their address is the "regular"
2121 - * address plus 4K
2122 - */
2123 -#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
2124 -/* bar0 window size Match with corerev 13 */
2125 -#define PCI_BAR0_WINSZ         (16 * 1024)
2126 -/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
2127 -/* bar0 + 8K accesses pci/pcie core registers */
2128 -#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
2129 -/* bar0 + 12K accesses chipc core registers */
2130 -#define PCI_16KB0_CCREGS_OFFSET        (12 * 1024)
2131 -
2132 -struct sbpciregs;
2133 -struct sbpcieregs;
2134 -
2135 -extern struct pcicore_info *pcicore_init(struct si_pub *sih,
2136 -                                        struct bcma_device *core);
2137 -extern void pcicore_deinit(struct pcicore_info *pch);
2138 -extern void pcicore_attach(struct pcicore_info *pch, int state);
2139 -extern void pcicore_hwup(struct pcicore_info *pch);
2140 -extern void pcicore_up(struct pcicore_info *pch, int state);
2141 -extern void pcicore_sleep(struct pcicore_info *pch);
2142 -extern void pcicore_down(struct pcicore_info *pch, int state);
2143 -extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
2144 -                                     unsigned char *buf, u32 *buflen);
2145 -extern void pcicore_fixcfg(struct pcicore_info *pch);
2146 -extern void pcicore_pci_setup(struct pcicore_info *pch);
2147 -
2148 -#endif /* _BRCM_NICPCI_H_ */
2149 --- a/drivers/net/wireless/brcm80211/brcmsmac/otp.c
2150 +++ /dev/null
2151 @@ -1,410 +0,0 @@
2152 -/*
2153 - * Copyright (c) 2010 Broadcom Corporation
2154 - *
2155 - * Permission to use, copy, modify, and/or distribute this software for any
2156 - * purpose with or without fee is hereby granted, provided that the above
2157 - * copyright notice and this permission notice appear in all copies.
2158 - *
2159 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
2160 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
2161 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
2162 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
2163 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
2164 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
2165 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2166 - */
2167 -
2168 -#include <linux/io.h>
2169 -#include <linux/errno.h>
2170 -#include <linux/string.h>
2171 -
2172 -#include <brcm_hw_ids.h>
2173 -#include <chipcommon.h>
2174 -#include "aiutils.h"
2175 -#include "otp.h"
2176 -
2177 -#define OTPS_GUP_MASK          0x00000f00
2178 -#define OTPS_GUP_SHIFT         8
2179 -/* h/w subregion is programmed */
2180 -#define OTPS_GUP_HW            0x00000100
2181 -/* s/w subregion is programmed */
2182 -#define OTPS_GUP_SW            0x00000200
2183 -/* chipid/pkgopt subregion is programmed */
2184 -#define OTPS_GUP_CI            0x00000400
2185 -/* fuse subregion is programmed */
2186 -#define OTPS_GUP_FUSE          0x00000800
2187 -
2188 -/* Fields in otpprog in rev >= 21 */
2189 -#define OTPP_COL_MASK          0x000000ff
2190 -#define OTPP_COL_SHIFT         0
2191 -#define OTPP_ROW_MASK          0x0000ff00
2192 -#define OTPP_ROW_SHIFT         8
2193 -#define OTPP_OC_MASK           0x0f000000
2194 -#define OTPP_OC_SHIFT          24
2195 -#define OTPP_READERR           0x10000000
2196 -#define OTPP_VALUE_MASK                0x20000000
2197 -#define OTPP_VALUE_SHIFT       29
2198 -#define OTPP_START_BUSY                0x80000000
2199 -#define        OTPP_READ               0x40000000
2200 -
2201 -/* Opcodes for OTPP_OC field */
2202 -#define OTPPOC_READ            0
2203 -#define OTPPOC_BIT_PROG                1
2204 -#define OTPPOC_VERIFY          3
2205 -#define OTPPOC_INIT            4
2206 -#define OTPPOC_SET             5
2207 -#define OTPPOC_RESET           6
2208 -#define OTPPOC_OCST            7
2209 -#define OTPPOC_ROW_LOCK                8
2210 -#define OTPPOC_PRESCN_TEST     9
2211 -
2212 -#define OTPTYPE_IPX(ccrev)     ((ccrev) == 21 || (ccrev) >= 23)
2213 -
2214 -#define OTPP_TRIES     10000000        /* # of tries for OTPP */
2215 -
2216 -#define MAXNUMRDES             9       /* Maximum OTP redundancy entries */
2217 -
2218 -/* Fixed size subregions sizes in words */
2219 -#define OTPGU_CI_SZ            2
2220 -
2221 -struct otpinfo;
2222 -
2223 -/* OTP function struct */
2224 -struct otp_fn_s {
2225 -       int (*init)(struct si_pub *sih, struct otpinfo *oi);
2226 -       int (*read_region)(struct otpinfo *oi, int region, u16 *data,
2227 -                          uint *wlen);
2228 -};
2229 -
2230 -struct otpinfo {
2231 -       struct bcma_device *core; /* chipc core */
2232 -       const struct otp_fn_s *fn;      /* OTP functions */
2233 -       struct si_pub *sih;             /* Saved sb handle */
2234 -
2235 -       /* IPX OTP section */
2236 -       u16 wsize;              /* Size of otp in words */
2237 -       u16 rows;               /* Geometry */
2238 -       u16 cols;               /* Geometry */
2239 -       u32 status;             /* Flag bits (lock/prog/rv).
2240 -                                * (Reflected only when OTP is power cycled)
2241 -                                */
2242 -       u16 hwbase;             /* hardware subregion offset */
2243 -       u16 hwlim;              /* hardware subregion boundary */
2244 -       u16 swbase;             /* software subregion offset */
2245 -       u16 swlim;              /* software subregion boundary */
2246 -       u16 fbase;              /* fuse subregion offset */
2247 -       u16 flim;               /* fuse subregion boundary */
2248 -       int otpgu_base;         /* offset to General Use Region */
2249 -};
2250 -
2251 -/* OTP layout */
2252 -/* CC revs 21, 24 and 27 OTP General Use Region word offset */
2253 -#define REVA4_OTPGU_BASE       12
2254 -
2255 -/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
2256 -#define REVB8_OTPGU_BASE       20
2257 -
2258 -/* CC rev 36 OTP General Use Region word offset */
2259 -#define REV36_OTPGU_BASE       12
2260 -
2261 -/* Subregion word offsets in General Use region */
2262 -#define OTPGU_HSB_OFF          0
2263 -#define OTPGU_SFB_OFF          1
2264 -#define OTPGU_CI_OFF           2
2265 -#define OTPGU_P_OFF            3
2266 -#define OTPGU_SROM_OFF         4
2267 -
2268 -/* Flag bit offsets in General Use region  */
2269 -#define OTPGU_HWP_OFF          60
2270 -#define OTPGU_SWP_OFF          61
2271 -#define OTPGU_CIP_OFF          62
2272 -#define OTPGU_FUSEP_OFF                63
2273 -#define OTPGU_CIP_MSK          0x4000
2274 -#define OTPGU_P_MSK            0xf000
2275 -#define OTPGU_P_SHIFT          (OTPGU_HWP_OFF % 16)
2276 -
2277 -/* OTP Size */
2278 -#define OTP_SZ_FU_324          ((roundup(324, 8))/8)   /* 324 bits */
2279 -#define OTP_SZ_FU_288          (288/8) /* 288 bits */
2280 -#define OTP_SZ_FU_216          (216/8) /* 216 bits */
2281 -#define OTP_SZ_FU_72           (72/8)  /* 72 bits */
2282 -#define OTP_SZ_CHECKSUM                (16/8)  /* 16 bits */
2283 -#define OTP4315_SWREG_SZ       178     /* 178 bytes */
2284 -#define OTP_SZ_FU_144          (144/8) /* 144 bits */
2285 -
2286 -static u16
2287 -ipxotp_otpr(struct otpinfo *oi, uint wn)
2288 -{
2289 -       return bcma_read16(oi->core,
2290 -                          CHIPCREGOFFS(sromotp[wn]));
2291 -}
2292 -
2293 -/*
2294 - * Calculate max HW/SW region byte size by subtracting fuse region
2295 - * and checksum size, osizew is oi->wsize (OTP size - GU size) in words
2296 - */
2297 -static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
2298 -{
2299 -       int ret = 0;
2300 -
2301 -       switch (ai_get_chip_id(sih)) {
2302 -       case BCM43224_CHIP_ID:
2303 -       case BCM43225_CHIP_ID:
2304 -               ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
2305 -               break;
2306 -       case BCM4313_CHIP_ID:
2307 -               ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
2308 -               break;
2309 -       default:
2310 -               break;  /* Don't know about this chip */
2311 -       }
2312 -
2313 -       return ret;
2314 -}
2315 -
2316 -static void _ipxotp_init(struct otpinfo *oi)
2317 -{
2318 -       uint k;
2319 -       u32 otpp, st;
2320 -       int ccrev = ai_get_ccrev(oi->sih);
2321 -
2322 -
2323 -       /*
2324 -        * record word offset of General Use Region
2325 -        * for various chipcommon revs
2326 -        */
2327 -       if (ccrev == 21 || ccrev == 24
2328 -           || ccrev == 27) {
2329 -               oi->otpgu_base = REVA4_OTPGU_BASE;
2330 -       } else if (ccrev == 36) {
2331 -               /*
2332 -                * OTP size greater than equal to 2KB (128 words),
2333 -                * otpgu_base is similar to rev23
2334 -                */
2335 -               if (oi->wsize >= 128)
2336 -                       oi->otpgu_base = REVB8_OTPGU_BASE;
2337 -               else
2338 -                       oi->otpgu_base = REV36_OTPGU_BASE;
2339 -       } else if (ccrev == 23 || ccrev >= 25) {
2340 -               oi->otpgu_base = REVB8_OTPGU_BASE;
2341 -       }
2342 -
2343 -       /* First issue an init command so the status is up to date */
2344 -       otpp =
2345 -           OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
2346 -
2347 -       bcma_write32(oi->core, CHIPCREGOFFS(otpprog), otpp);
2348 -       st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
2349 -       for (k = 0; (st & OTPP_START_BUSY) && (k < OTPP_TRIES); k++)
2350 -               st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
2351 -       if (k >= OTPP_TRIES)
2352 -               return;
2353 -
2354 -       /* Read OTP lock bits and subregion programmed indication bits */
2355 -       oi->status = bcma_read32(oi->core, CHIPCREGOFFS(otpstatus));
2356 -
2357 -       if ((ai_get_chip_id(oi->sih) == BCM43224_CHIP_ID)
2358 -           || (ai_get_chip_id(oi->sih) == BCM43225_CHIP_ID)) {
2359 -               u32 p_bits;
2360 -               p_bits = (ipxotp_otpr(oi, oi->otpgu_base + OTPGU_P_OFF) &
2361 -                         OTPGU_P_MSK) >> OTPGU_P_SHIFT;
2362 -               oi->status |= (p_bits << OTPS_GUP_SHIFT);
2363 -       }
2364 -
2365 -       /*
2366 -        * h/w region base and fuse region limit are fixed to
2367 -        * the top and the bottom of the general use region.
2368 -        * Everything else can be flexible.
2369 -        */
2370 -       oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
2371 -       oi->hwlim = oi->wsize;
2372 -       if (oi->status & OTPS_GUP_HW) {
2373 -               oi->hwlim =
2374 -                   ipxotp_otpr(oi, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
2375 -               oi->swbase = oi->hwlim;
2376 -       } else
2377 -               oi->swbase = oi->hwbase;
2378 -
2379 -       /* subtract fuse and checksum from beginning */
2380 -       oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
2381 -
2382 -       if (oi->status & OTPS_GUP_SW) {
2383 -               oi->swlim =
2384 -                   ipxotp_otpr(oi, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
2385 -               oi->fbase = oi->swlim;
2386 -       } else
2387 -               oi->fbase = oi->swbase;
2388 -
2389 -       oi->flim = oi->wsize;
2390 -}
2391 -
2392 -static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
2393 -{
2394 -       /* Make sure we're running IPX OTP */
2395 -       if (!OTPTYPE_IPX(ai_get_ccrev(sih)))
2396 -               return -EBADE;
2397 -
2398 -       /* Make sure OTP is not disabled */
2399 -       if (ai_is_otp_disabled(sih))
2400 -               return -EBADE;
2401 -
2402 -       /* Check for otp size */
2403 -       switch ((ai_get_cccaps(sih) & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
2404 -       case 0:
2405 -               /* Nothing there */
2406 -               return -EBADE;
2407 -       case 1:         /* 32x64 */
2408 -               oi->rows = 32;
2409 -               oi->cols = 64;
2410 -               oi->wsize = 128;
2411 -               break;
2412 -       case 2:         /* 64x64 */
2413 -               oi->rows = 64;
2414 -               oi->cols = 64;
2415 -               oi->wsize = 256;
2416 -               break;
2417 -       case 5:         /* 96x64 */
2418 -               oi->rows = 96;
2419 -               oi->cols = 64;
2420 -               oi->wsize = 384;
2421 -               break;
2422 -       case 7:         /* 16x64 *//* 1024 bits */
2423 -               oi->rows = 16;
2424 -               oi->cols = 64;
2425 -               oi->wsize = 64;
2426 -               break;
2427 -       default:
2428 -               /* Don't know the geometry */
2429 -               return -EBADE;
2430 -       }
2431 -
2432 -       /* Retrieve OTP region info */
2433 -       _ipxotp_init(oi);
2434 -       return 0;
2435 -}
2436 -
2437 -static int
2438 -ipxotp_read_region(struct otpinfo *oi, int region, u16 *data, uint *wlen)
2439 -{
2440 -       uint base, i, sz;
2441 -
2442 -       /* Validate region selection */
2443 -       switch (region) {
2444 -       case OTP_HW_RGN:
2445 -               sz = (uint) oi->hwlim - oi->hwbase;
2446 -               if (!(oi->status & OTPS_GUP_HW)) {
2447 -                       *wlen = sz;
2448 -                       return -ENODATA;
2449 -               }
2450 -               if (*wlen < sz) {
2451 -                       *wlen = sz;
2452 -                       return -EOVERFLOW;
2453 -               }
2454 -               base = oi->hwbase;
2455 -               break;
2456 -       case OTP_SW_RGN:
2457 -               sz = ((uint) oi->swlim - oi->swbase);
2458 -               if (!(oi->status & OTPS_GUP_SW)) {
2459 -                       *wlen = sz;
2460 -                       return -ENODATA;
2461 -               }
2462 -               if (*wlen < sz) {
2463 -                       *wlen = sz;
2464 -                       return -EOVERFLOW;
2465 -               }
2466 -               base = oi->swbase;
2467 -               break;
2468 -       case OTP_CI_RGN:
2469 -               sz = OTPGU_CI_SZ;
2470 -               if (!(oi->status & OTPS_GUP_CI)) {
2471 -                       *wlen = sz;
2472 -                       return -ENODATA;
2473 -               }
2474 -               if (*wlen < sz) {
2475 -                       *wlen = sz;
2476 -                       return -EOVERFLOW;
2477 -               }
2478 -               base = oi->otpgu_base + OTPGU_CI_OFF;
2479 -               break;
2480 -       case OTP_FUSE_RGN:
2481 -               sz = (uint) oi->flim - oi->fbase;
2482 -               if (!(oi->status & OTPS_GUP_FUSE)) {
2483 -                       *wlen = sz;
2484 -                       return -ENODATA;
2485 -               }
2486 -               if (*wlen < sz) {
2487 -                       *wlen = sz;
2488 -                       return -EOVERFLOW;
2489 -               }
2490 -               base = oi->fbase;
2491 -               break;
2492 -       case OTP_ALL_RGN:
2493 -               sz = ((uint) oi->flim - oi->hwbase);
2494 -               if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
2495 -                       *wlen = sz;
2496 -                       return -ENODATA;
2497 -               }
2498 -               if (*wlen < sz) {
2499 -                       *wlen = sz;
2500 -                       return -EOVERFLOW;
2501 -               }
2502 -               base = oi->hwbase;
2503 -               break;
2504 -       default:
2505 -               return -EINVAL;
2506 -       }
2507 -
2508 -       /* Read the data */
2509 -       for (i = 0; i < sz; i++)
2510 -               data[i] = ipxotp_otpr(oi, base + i);
2511 -
2512 -       *wlen = sz;
2513 -       return 0;
2514 -}
2515 -
2516 -static const struct otp_fn_s ipxotp_fn = {
2517 -       (int (*)(struct si_pub *, struct otpinfo *)) ipxotp_init,
2518 -       (int (*)(struct otpinfo *, int, u16 *, uint *)) ipxotp_read_region,
2519 -};
2520 -
2521 -static int otp_init(struct si_pub *sih, struct otpinfo *oi)
2522 -{
2523 -       int ret;
2524 -
2525 -       memset(oi, 0, sizeof(struct otpinfo));
2526 -
2527 -       oi->core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
2528 -
2529 -       if (OTPTYPE_IPX(ai_get_ccrev(sih)))
2530 -               oi->fn = &ipxotp_fn;
2531 -
2532 -       if (oi->fn == NULL)
2533 -               return -EBADE;
2534 -
2535 -       oi->sih = sih;
2536 -
2537 -       ret = (oi->fn->init)(sih, oi);
2538 -
2539 -       return ret;
2540 -}
2541 -
2542 -int
2543 -otp_read_region(struct si_pub *sih, int region, u16 *data, uint *wlen) {
2544 -       struct otpinfo otpinfo;
2545 -       struct otpinfo *oi = &otpinfo;
2546 -       int err = 0;
2547 -
2548 -       if (ai_is_otp_disabled(sih)) {
2549 -               err = -EPERM;
2550 -               goto out;
2551 -       }
2552 -
2553 -       err = otp_init(sih, oi);
2554 -       if (err)
2555 -               goto out;
2556 -
2557 -       err = ((oi)->fn->read_region)(oi, region, data, wlen);
2558 -
2559 - out:
2560 -       return err;
2561 -}
2562 --- a/drivers/net/wireless/brcm80211/brcmsmac/otp.h
2563 +++ /dev/null
2564 @@ -1,36 +0,0 @@
2565 -/*
2566 - * Copyright (c) 2010 Broadcom Corporation
2567 - *
2568 - * Permission to use, copy, modify, and/or distribute this software for any
2569 - * purpose with or without fee is hereby granted, provided that the above
2570 - * copyright notice and this permission notice appear in all copies.
2571 - *
2572 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
2573 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
2574 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
2575 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
2576 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
2577 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
2578 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2579 - */
2580 -
2581 -#ifndef        _BRCM_OTP_H_
2582 -#define        _BRCM_OTP_H_
2583 -
2584 -#include "types.h"
2585 -
2586 -/* OTP regions */
2587 -#define OTP_HW_RGN     1
2588 -#define OTP_SW_RGN     2
2589 -#define OTP_CI_RGN     4
2590 -#define OTP_FUSE_RGN   8
2591 -/* From h/w region to end of OTP including checksum */
2592 -#define OTP_ALL_RGN    0xf
2593 -
2594 -/* OTP Size */
2595 -#define OTP_SZ_MAX             (6144/8)        /* maximum bytes in one CIS */
2596 -
2597 -extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
2598 -                          uint *wlen);
2599 -
2600 -#endif                         /* _BRCM_OTP_H_ */
2601 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
2602 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
2603 @@ -4817,28 +4817,23 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2604         s8 txpwr = 0;
2605         int i;
2606         struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2607 -       struct phy_shim_info *shim = pi->sh->physhim;
2608 +       struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
2609
2610         if (CHSPEC_IS2G(pi->radio_chanspec)) {
2611                 u16 cckpo = 0;
2612                 u32 offset_ofdm, offset_mcs;
2613
2614 -               pi_lcn->lcnphy_tr_isolation_mid =
2615 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
2616 +               pi_lcn->lcnphy_tr_isolation_mid = sprom->fem.ghz2.tr_iso;
2617
2618 -               pi_lcn->lcnphy_rx_power_offset =
2619 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_RXPO2G);
2620 +               pi_lcn->lcnphy_rx_power_offset = sprom->rxpo2g;
2621
2622 -               pi->txpa_2g[0] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B0);
2623 -               pi->txpa_2g[1] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B1);
2624 -               pi->txpa_2g[2] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B2);
2625 -
2626 -               pi_lcn->lcnphy_rssi_vf =
2627 -                               (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMF2G);
2628 -               pi_lcn->lcnphy_rssi_vc =
2629 -                               (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMC2G);
2630 -               pi_lcn->lcnphy_rssi_gs =
2631 -                               (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISAV2G);
2632 +               pi->txpa_2g[0] = sprom->pa0b0;
2633 +               pi->txpa_2g[1] = sprom->pa0b1;
2634 +               pi->txpa_2g[2] = sprom->pa0b2;
2635 +
2636 +               pi_lcn->lcnphy_rssi_vf = sprom->rssismf2g;
2637 +               pi_lcn->lcnphy_rssi_vc = sprom->rssismc2g;
2638 +               pi_lcn->lcnphy_rssi_gs = sprom->rssisav2g;
2639
2640                 pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
2641                 pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
2642 @@ -4848,7 +4843,7 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2643                 pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc;
2644                 pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs;
2645
2646 -               txpwr = (s8)wlapi_getintvar(shim, BRCMS_SROM_MAXP2GA0);
2647 +               txpwr = sprom->core_pwr_info[0].maxpwr_2g;
2648                 pi->tx_srom_max_2g = txpwr;
2649
2650                 for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
2651 @@ -4856,8 +4851,8 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2652                         pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
2653                 }
2654
2655 -               cckpo = (u16)wlapi_getintvar(shim, BRCMS_SROM_CCK2GPO);
2656 -               offset_ofdm = (u32)wlapi_getintvar(shim, BRCMS_SROM_OFDM2GPO);
2657 +               cckpo = sprom->cck2gpo;
2658 +               offset_ofdm = sprom->ofdm2gpo;
2659                 if (cckpo) {
2660                         uint max_pwr_chan = txpwr;
2661
2662 @@ -4876,7 +4871,7 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2663                 } else {
2664                         u8 opo = 0;
2665
2666 -                       opo = (u8)wlapi_getintvar(shim, BRCMS_SROM_OPO);
2667 +                       opo = sprom->opo;
2668
2669                         for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++)
2670                                 pi->tx_srom_max_rate_2g[i] = txpwr;
2671 @@ -4886,12 +4881,8 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2672                                                 ((offset_ofdm & 0xf) * 2);
2673                                 offset_ofdm >>= 4;
2674                         }
2675 -                       offset_mcs =
2676 -                               wlapi_getintvar(shim,
2677 -                                               BRCMS_SROM_MCS2GPO1) << 16;
2678 -                       offset_mcs |=
2679 -                               (u16) wlapi_getintvar(shim,
2680 -                                                     BRCMS_SROM_MCS2GPO0);
2681 +                       offset_mcs = sprom->mcs2gpo[1] << 16;
2682 +                       offset_mcs |= sprom->mcs2gpo[0];
2683                         pi_lcn->lcnphy_mcs20_po = offset_mcs;
2684                         for (i = TXP_FIRST_SISO_MCS_20;
2685                              i <= TXP_LAST_SISO_MCS_20; i++) {
2686 @@ -4901,25 +4892,17 @@ static bool wlc_phy_txpwr_srom_read_lcnp
2687                         }
2688                 }
2689
2690 -               pi_lcn->lcnphy_rawtempsense =
2691 -                       (u16)wlapi_getintvar(shim, BRCMS_SROM_RAWTEMPSENSE);
2692 -               pi_lcn->lcnphy_measPower =
2693 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_MEASPOWER);
2694 -               pi_lcn->lcnphy_tempsense_slope =
2695 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_SLOPE);
2696 -               pi_lcn->lcnphy_hw_iqcal_en =
2697 -                       (bool)wlapi_getintvar(shim, BRCMS_SROM_HW_IQCAL_EN);
2698 -               pi_lcn->lcnphy_iqcal_swp_dis =
2699 -                       (bool)wlapi_getintvar(shim, BRCMS_SROM_IQCAL_SWP_DIS);
2700 -               pi_lcn->lcnphy_tempcorrx =
2701 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPCORRX);
2702 -               pi_lcn->lcnphy_tempsense_option =
2703 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_OPTION);
2704 -               pi_lcn->lcnphy_freqoffset_corr =
2705 -                       (u8)wlapi_getintvar(shim, BRCMS_SROM_FREQOFFSET_CORR);
2706 -               if ((u8)wlapi_getintvar(shim, BRCMS_SROM_AA2G) > 1)
2707 +               pi_lcn->lcnphy_rawtempsense = sprom->rawtempsense;
2708 +               pi_lcn->lcnphy_measPower = sprom->measpower;
2709 +               pi_lcn->lcnphy_tempsense_slope = sprom->tempsense_slope;
2710 +               pi_lcn->lcnphy_hw_iqcal_en = sprom->hw_iqcal_en;
2711 +               pi_lcn->lcnphy_iqcal_swp_dis = sprom->iqcal_swp_dis;
2712 +               pi_lcn->lcnphy_tempcorrx = sprom->tempcorrx;
2713 +               pi_lcn->lcnphy_tempsense_option = sprom->tempsense_option;
2714 +               pi_lcn->lcnphy_freqoffset_corr = sprom->freqoffset_corr;
2715 +               if (sprom->ant_available_bg > 1)
2716                         wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi,
2717 -                               (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G));
2718 +                               sprom->ant_available_bg);
2719         }
2720         pi_lcn->lcnphy_cck_dig_filt_type = -1;
2721
2722 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
2723 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
2724 @@ -14388,30 +14388,30 @@ static void wlc_phy_txpwr_srom_read_ppr_
2725  {
2726         u16 bw40po, cddpo, stbcpo, bwduppo;
2727         uint band_num;
2728 -       struct phy_shim_info *shim = pi->sh->physhim;
2729 +       struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
2730
2731         if (pi->sh->sromrev >= 9)
2732                 return;
2733
2734 -       bw40po = (u16) wlapi_getintvar(shim, BRCMS_SROM_BW40PO);
2735 +       bw40po = sprom->bw40po;
2736         pi->bw402gpo = bw40po & 0xf;
2737         pi->bw405gpo = (bw40po & 0xf0) >> 4;
2738         pi->bw405glpo = (bw40po & 0xf00) >> 8;
2739         pi->bw405ghpo = (bw40po & 0xf000) >> 12;
2740
2741 -       cddpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_CDDPO);
2742 +       cddpo = sprom->cddpo;
2743         pi->cdd2gpo = cddpo & 0xf;
2744         pi->cdd5gpo = (cddpo & 0xf0) >> 4;
2745         pi->cdd5glpo = (cddpo & 0xf00) >> 8;
2746         pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
2747
2748 -       stbcpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_STBCPO);
2749 +       stbcpo = sprom->stbcpo;
2750         pi->stbc2gpo = stbcpo & 0xf;
2751         pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
2752         pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
2753         pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
2754
2755 -       bwduppo = (u16) wlapi_getintvar(shim, BRCMS_SROM_BWDUPPO);
2756 +       bwduppo = sprom->bwduppo;
2757         pi->bwdup2gpo = bwduppo & 0xf;
2758         pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
2759         pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
2760 @@ -14421,242 +14421,137 @@ static void wlc_phy_txpwr_srom_read_ppr_
2761              band_num++) {
2762                 switch (band_num) {
2763                 case 0:
2764 -
2765                         pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
2766 -                               (s8) wlapi_getintvar(shim,
2767 -                                                    BRCMS_SROM_MAXP2GA0);
2768 +                               sprom->core_pwr_info[0].maxpwr_2g;
2769                         pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
2770 -                               (s8) wlapi_getintvar(shim,
2771 -                                                    BRCMS_SROM_MAXP2GA1);
2772 +                               sprom->core_pwr_info[1].maxpwr_2g;
2773                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
2774 -                               (s16) wlapi_getintvar(shim,
2775 -                                                     BRCMS_SROM_PA2GW0A0);
2776 +                               sprom->core_pwr_info[0].pa_2g[0];
2777                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
2778 -                               (s16) wlapi_getintvar(shim,
2779 -                                                     BRCMS_SROM_PA2GW0A1);
2780 +                               sprom->core_pwr_info[1].pa_2g[0];
2781                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
2782 -                               (s16) wlapi_getintvar(shim,
2783 -                                                     BRCMS_SROM_PA2GW1A0);
2784 +                               sprom->core_pwr_info[0].pa_2g[1];
2785                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
2786 -                               (s16) wlapi_getintvar(shim,
2787 -                                                     BRCMS_SROM_PA2GW1A1);
2788 +                               sprom->core_pwr_info[1].pa_2g[1];
2789                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
2790 -                               (s16) wlapi_getintvar(shim,
2791 -                                                     BRCMS_SROM_PA2GW2A0);
2792 +                               sprom->core_pwr_info[0].pa_2g[2];
2793                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
2794 -                               (s16) wlapi_getintvar(shim,
2795 -                                                     BRCMS_SROM_PA2GW2A1);
2796 +                               sprom->core_pwr_info[1].pa_2g[2];
2797                         pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
2798 -                               (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA0);
2799 +                               sprom->core_pwr_info[0].itssi_2g;
2800                         pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
2801 -                               (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA1);
2802 +                               sprom->core_pwr_info[1].itssi_2g;
2803 +
2804 +                       pi->cck2gpo = sprom->cck2gpo;
2805
2806 -                       pi->cck2gpo = (u16) wlapi_getintvar(shim,
2807 -                                                           BRCMS_SROM_CCK2GPO);
2808 +                       pi->ofdm2gpo = sprom->ofdm2gpo;
2809
2810 -                       pi->ofdm2gpo =
2811 -                               (u32) wlapi_getintvar(shim,
2812 -                                                     BRCMS_SROM_OFDM2GPO);
2813 -
2814 -                       pi->mcs2gpo[0] =
2815 -                               (u16) wlapi_getintvar(shim,
2816 -                                                     BRCMS_SROM_MCS2GPO0);
2817 -                       pi->mcs2gpo[1] =
2818 -                               (u16) wlapi_getintvar(shim,
2819 -                                                     BRCMS_SROM_MCS2GPO1);
2820 -                       pi->mcs2gpo[2] =
2821 -                               (u16) wlapi_getintvar(shim,
2822 -                                                     BRCMS_SROM_MCS2GPO2);
2823 -                       pi->mcs2gpo[3] =
2824 -                               (u16) wlapi_getintvar(shim,
2825 -                                                     BRCMS_SROM_MCS2GPO3);
2826 -                       pi->mcs2gpo[4] =
2827 -                               (u16) wlapi_getintvar(shim,
2828 -                                                     BRCMS_SROM_MCS2GPO4);
2829 -                       pi->mcs2gpo[5] =
2830 -                               (u16) wlapi_getintvar(shim,
2831 -                                                     BRCMS_SROM_MCS2GPO5);
2832 -                       pi->mcs2gpo[6] =
2833 -                               (u16) wlapi_getintvar(shim,
2834 -                                                     BRCMS_SROM_MCS2GPO6);
2835 -                       pi->mcs2gpo[7] =
2836 -                               (u16) wlapi_getintvar(shim,
2837 -                                                     BRCMS_SROM_MCS2GPO7);
2838 +                       pi->mcs2gpo[0] = sprom->mcs2gpo[0];
2839 +                       pi->mcs2gpo[1] = sprom->mcs2gpo[1];
2840 +                       pi->mcs2gpo[2] = sprom->mcs2gpo[2];
2841 +                       pi->mcs2gpo[3] = sprom->mcs2gpo[3];
2842 +                       pi->mcs2gpo[4] = sprom->mcs2gpo[4];
2843 +                       pi->mcs2gpo[5] = sprom->mcs2gpo[5];
2844 +                       pi->mcs2gpo[6] = sprom->mcs2gpo[6];
2845 +                       pi->mcs2gpo[7] = sprom->mcs2gpo[7];
2846                         break;
2847                 case 1:
2848
2849                         pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
2850 -                               (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0);
2851 +                               sprom->core_pwr_info[0].maxpwr_5g;
2852                         pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
2853 -                               (s8) wlapi_getintvar(shim,
2854 -                                                    BRCMS_SROM_MAXP5GA1);
2855 +                               sprom->core_pwr_info[1].maxpwr_5g;
2856                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
2857 -                               (s16) wlapi_getintvar(shim,
2858 -                                                     BRCMS_SROM_PA5GW0A0);
2859 +                               sprom->core_pwr_info[0].pa_5g[0];
2860                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
2861 -                               (s16) wlapi_getintvar(shim,
2862 -                                                     BRCMS_SROM_PA5GW0A1);
2863 +                               sprom->core_pwr_info[1].pa_5g[0];
2864                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
2865 -                               (s16) wlapi_getintvar(shim,
2866 -                                                     BRCMS_SROM_PA5GW1A0);
2867 +                               sprom->core_pwr_info[0].pa_5g[1];
2868                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
2869 -                               (s16) wlapi_getintvar(shim,
2870 -                                                     BRCMS_SROM_PA5GW1A1);
2871 +                               sprom->core_pwr_info[1].pa_5g[1];
2872                         pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
2873 -                               (s16) wlapi_getintvar(shim,
2874 -                                                     BRCMS_SROM_PA5GW2A0);
2875 +                               sprom->core_pwr_info[0].pa_5g[2];
2876                         pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
2877 -                               (s16) wlapi_getintvar(shim,
2878 -                                                     BRCMS_SROM_PA5GW2A1);
2879 +                               sprom->core_pwr_info[1].pa_5g[2];
2880                         pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
2881 -                               (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA0);
2882 +                               sprom->core_pwr_info[0].itssi_5g;
2883                         pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
2884 -                               (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA1);
2885 +                               sprom->core_pwr_info[1].itssi_5g;
2886 +
2887 +                       pi->ofdm5gpo = sprom->ofdm5gpo;
2888
2889 -                       pi->ofdm5gpo =
2890 -                               (u32) wlapi_getintvar(shim,
2891 -                                                     BRCMS_SROM_OFDM5GPO);
2892 -
2893 -                       pi->mcs5gpo[0] =
2894 -                               (u16) wlapi_getintvar(shim,
2895 -                                                     BRCMS_SROM_MCS5GPO0);
2896 -                       pi->mcs5gpo[1] =
2897 -                               (u16) wlapi_getintvar(shim,
2898 -                                                     BRCMS_SROM_MCS5GPO1);
2899 -                       pi->mcs5gpo[2] =
2900 -                               (u16) wlapi_getintvar(shim,
2901 -                                                     BRCMS_SROM_MCS5GPO2);
2902 -                       pi->mcs5gpo[3] =
2903 -                               (u16) wlapi_getintvar(shim,
2904 -                                                     BRCMS_SROM_MCS5GPO3);
2905 -                       pi->mcs5gpo[4] =
2906 -                               (u16) wlapi_getintvar(shim,
2907 -                                                     BRCMS_SROM_MCS5GPO4);
2908 -                       pi->mcs5gpo[5] =
2909 -                               (u16) wlapi_getintvar(shim,
2910 -                                                     BRCMS_SROM_MCS5GPO5);
2911 -                       pi->mcs5gpo[6] =
2912 -                               (u16) wlapi_getintvar(shim,
2913 -                                                     BRCMS_SROM_MCS5GPO6);
2914 -                       pi->mcs5gpo[7] =
2915 -                               (u16) wlapi_getintvar(shim,
2916 -                                                     BRCMS_SROM_MCS5GPO7);
2917 +                       pi->mcs5gpo[0] = sprom->mcs5gpo[0];
2918 +                       pi->mcs5gpo[1] = sprom->mcs5gpo[1];
2919 +                       pi->mcs5gpo[2] = sprom->mcs5gpo[2];
2920 +                       pi->mcs5gpo[3] = sprom->mcs5gpo[3];
2921 +                       pi->mcs5gpo[4] = sprom->mcs5gpo[4];
2922 +                       pi->mcs5gpo[5] = sprom->mcs5gpo[5];
2923 +                       pi->mcs5gpo[6] = sprom->mcs5gpo[6];
2924 +                       pi->mcs5gpo[7] = sprom->mcs5gpo[7];
2925                         break;
2926                 case 2:
2927
2928                         pi->nphy_pwrctrl_info[0].max_pwr_5gl =
2929 -                               (s8) wlapi_getintvar(shim,
2930 -                                                    BRCMS_SROM_MAXP5GLA0);
2931 +                               sprom->core_pwr_info[0].maxpwr_5gl;
2932                         pi->nphy_pwrctrl_info[1].max_pwr_5gl =
2933 -                               (s8) wlapi_getintvar(shim,
2934 -                                                    BRCMS_SROM_MAXP5GLA1);
2935 +                               sprom->core_pwr_info[1].maxpwr_5gl;
2936                         pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
2937 -                               (s16) wlapi_getintvar(shim,
2938 -                                                     BRCMS_SROM_PA5GLW0A0);
2939 +                               sprom->core_pwr_info[0].pa_5gl[0];
2940                         pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
2941 -                               (s16) wlapi_getintvar(shim,
2942 -                                                     BRCMS_SROM_PA5GLW0A1);
2943 +                               sprom->core_pwr_info[1].pa_5gl[0];
2944                         pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
2945 -                               (s16) wlapi_getintvar(shim,
2946 -                                                     BRCMS_SROM_PA5GLW1A0);
2947 +                               sprom->core_pwr_info[0].pa_5gl[1];
2948                         pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
2949 -                               (s16) wlapi_getintvar(shim,
2950 -                                                     BRCMS_SROM_PA5GLW1A1);
2951 +                               sprom->core_pwr_info[1].pa_5gl[1];
2952                         pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
2953 -                               (s16) wlapi_getintvar(shim,
2954 -                                                     BRCMS_SROM_PA5GLW2A0);
2955 +                               sprom->core_pwr_info[0].pa_5gl[2];
2956                         pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
2957 -                               (s16) wlapi_getintvar(shim,
2958 -                                                     BRCMS_SROM_PA5GLW2A1);
2959 +                               sprom->core_pwr_info[1].pa_5gl[2];
2960                         pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
2961                         pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
2962
2963 -                       pi->ofdm5glpo =
2964 -                               (u32) wlapi_getintvar(shim,
2965 -                                                     BRCMS_SROM_OFDM5GLPO);
2966 -
2967 -                       pi->mcs5glpo[0] =
2968 -                               (u16) wlapi_getintvar(shim,
2969 -                                                     BRCMS_SROM_MCS5GLPO0);
2970 -                       pi->mcs5glpo[1] =
2971 -                               (u16) wlapi_getintvar(shim,
2972 -                                                     BRCMS_SROM_MCS5GLPO1);
2973 -                       pi->mcs5glpo[2] =
2974 -                               (u16) wlapi_getintvar(shim,
2975 -                                                     BRCMS_SROM_MCS5GLPO2);
2976 -                       pi->mcs5glpo[3] =
2977 -                               (u16) wlapi_getintvar(shim,
2978 -                                                     BRCMS_SROM_MCS5GLPO3);
2979 -                       pi->mcs5glpo[4] =
2980 -                               (u16) wlapi_getintvar(shim,
2981 -                                                     BRCMS_SROM_MCS5GLPO4);
2982 -                       pi->mcs5glpo[5] =
2983 -                               (u16) wlapi_getintvar(shim,
2984 -                                                     BRCMS_SROM_MCS5GLPO5);
2985 -                       pi->mcs5glpo[6] =
2986 -                               (u16) wlapi_getintvar(shim,
2987 -                                                     BRCMS_SROM_MCS5GLPO6);
2988 -                       pi->mcs5glpo[7] =
2989 -                               (u16) wlapi_getintvar(shim,
2990 -                                                     BRCMS_SROM_MCS5GLPO7);
2991 +                       pi->ofdm5glpo = sprom->ofdm5glpo;
2992 +
2993 +                       pi->mcs5glpo[0] = sprom->mcs5glpo[0];
2994 +                       pi->mcs5glpo[1] = sprom->mcs5glpo[1];
2995 +                       pi->mcs5glpo[2] = sprom->mcs5glpo[2];
2996 +                       pi->mcs5glpo[3] = sprom->mcs5glpo[3];
2997 +                       pi->mcs5glpo[4] = sprom->mcs5glpo[4];
2998 +                       pi->mcs5glpo[5] = sprom->mcs5glpo[5];
2999 +                       pi->mcs5glpo[6] = sprom->mcs5glpo[6];
3000 +                       pi->mcs5glpo[7] = sprom->mcs5glpo[7];
3001                         break;
3002                 case 3:
3003
3004                         pi->nphy_pwrctrl_info[0].max_pwr_5gh =
3005 -                               (s8) wlapi_getintvar(shim,
3006 -                                                    BRCMS_SROM_MAXP5GHA0);
3007 +                               sprom->core_pwr_info[0].maxpwr_5gh;
3008                         pi->nphy_pwrctrl_info[1].max_pwr_5gh =
3009 -                               (s8) wlapi_getintvar(shim,
3010 -                                                    BRCMS_SROM_MAXP5GHA1);
3011 +                               sprom->core_pwr_info[1].maxpwr_5gh;
3012                         pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
3013 -                               (s16) wlapi_getintvar(shim,
3014 -                                                     BRCMS_SROM_PA5GHW0A0);
3015 +                               sprom->core_pwr_info[0].pa_5gh[0];
3016                         pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
3017 -                               (s16) wlapi_getintvar(shim,
3018 -                                                     BRCMS_SROM_PA5GHW0A1);
3019 +                               sprom->core_pwr_info[1].pa_5gh[0];
3020                         pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
3021 -                               (s16) wlapi_getintvar(shim,
3022 -                                                     BRCMS_SROM_PA5GHW1A0);
3023 +                               sprom->core_pwr_info[0].pa_5gh[1];
3024                         pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
3025 -                               (s16) wlapi_getintvar(shim,
3026 -                                                     BRCMS_SROM_PA5GHW1A1);
3027 +                               sprom->core_pwr_info[1].pa_5gh[1];
3028                         pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
3029 -                               (s16) wlapi_getintvar(shim,
3030 -                                                     BRCMS_SROM_PA5GHW2A0);
3031 +                               sprom->core_pwr_info[0].pa_5gh[2];
3032                         pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
3033 -                               (s16) wlapi_getintvar(shim,
3034 -                                                     BRCMS_SROM_PA5GHW2A1);
3035 +                               sprom->core_pwr_info[1].pa_5gh[2];
3036                         pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
3037                         pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
3038
3039 -                       pi->ofdm5ghpo =
3040 -                               (u32) wlapi_getintvar(shim,
3041 -                                                     BRCMS_SROM_OFDM5GHPO);
3042 -
3043 -                       pi->mcs5ghpo[0] =
3044 -                               (u16) wlapi_getintvar(shim,
3045 -                                                     BRCMS_SROM_MCS5GHPO0);
3046 -                       pi->mcs5ghpo[1] =
3047 -                               (u16) wlapi_getintvar(shim,
3048 -                                                     BRCMS_SROM_MCS5GHPO1);
3049 -                       pi->mcs5ghpo[2] =
3050 -                               (u16) wlapi_getintvar(shim,
3051 -                                                     BRCMS_SROM_MCS5GHPO2);
3052 -                       pi->mcs5ghpo[3] =
3053 -                               (u16) wlapi_getintvar(shim,
3054 -                                                     BRCMS_SROM_MCS5GHPO3);
3055 -                       pi->mcs5ghpo[4] =
3056 -                               (u16) wlapi_getintvar(shim,
3057 -                                                     BRCMS_SROM_MCS5GHPO4);
3058 -                       pi->mcs5ghpo[5] =
3059 -                               (u16) wlapi_getintvar(shim,
3060 -                                                     BRCMS_SROM_MCS5GHPO5);
3061 -                       pi->mcs5ghpo[6] =
3062 -                               (u16) wlapi_getintvar(shim,
3063 -                                                     BRCMS_SROM_MCS5GHPO6);
3064 -                       pi->mcs5ghpo[7] =
3065 -                               (u16) wlapi_getintvar(shim,
3066 -                                                     BRCMS_SROM_MCS5GHPO7);
3067 +                       pi->ofdm5ghpo = sprom->ofdm5ghpo;
3068 +
3069 +                       pi->mcs5ghpo[0] = sprom->mcs5ghpo[0];
3070 +                       pi->mcs5ghpo[1] = sprom->mcs5ghpo[1];
3071 +                       pi->mcs5ghpo[2] = sprom->mcs5ghpo[2];
3072 +                       pi->mcs5ghpo[3] = sprom->mcs5ghpo[3];
3073 +                       pi->mcs5ghpo[4] = sprom->mcs5ghpo[4];
3074 +                       pi->mcs5ghpo[5] = sprom->mcs5ghpo[5];
3075 +                       pi->mcs5ghpo[6] = sprom->mcs5ghpo[6];
3076 +                       pi->mcs5ghpo[7] = sprom->mcs5ghpo[7];
3077                         break;
3078                 }
3079         }
3080 @@ -14666,45 +14561,34 @@ static void wlc_phy_txpwr_srom_read_ppr_
3081
3082  static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
3083  {
3084 -       struct phy_shim_info *shim = pi->sh->physhim;
3085 +       struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
3086
3087 -       pi->antswitch = (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWITCH);
3088 -       pi->aa2g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G);
3089 -       pi->aa5g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA5G);
3090 -
3091 -       pi->srom_fem2g.tssipos = (u8) wlapi_getintvar(shim,
3092 -                                                     BRCMS_SROM_TSSIPOS2G);
3093 -       pi->srom_fem2g.extpagain = (u8) wlapi_getintvar(shim,
3094 -                                                       BRCMS_SROM_EXTPAGAIN2G);
3095 -       pi->srom_fem2g.pdetrange = (u8) wlapi_getintvar(shim,
3096 -                                                       BRCMS_SROM_PDETRANGE2G);
3097 -       pi->srom_fem2g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
3098 -       pi->srom_fem2g.antswctrllut =
3099 -                       (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
3100 -
3101 -       pi->srom_fem5g.tssipos = (u8) wlapi_getintvar(shim,
3102 -                                                     BRCMS_SROM_TSSIPOS5G);
3103 -       pi->srom_fem5g.extpagain = (u8) wlapi_getintvar(shim,
3104 -                                                       BRCMS_SROM_EXTPAGAIN5G);
3105 -       pi->srom_fem5g.pdetrange = (u8) wlapi_getintvar(shim,
3106 -                                                       BRCMS_SROM_PDETRANGE5G);
3107 -       pi->srom_fem5g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO5G);
3108 -       if (wlapi_getvar(shim, BRCMS_SROM_ANTSWCTL5G))
3109 -               pi->srom_fem5g.antswctrllut =
3110 -                       (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL5G);
3111 +       pi->antswitch = sprom->antswitch;
3112 +       pi->aa2g = sprom->ant_available_bg;
3113 +       pi->aa5g = sprom->ant_available_a;
3114 +
3115 +       pi->srom_fem2g.tssipos = sprom->fem.ghz2.tssipos;
3116 +       pi->srom_fem2g.extpagain = sprom->fem.ghz2.extpa_gain;
3117 +       pi->srom_fem2g.pdetrange = sprom->fem.ghz2.pdet_range;
3118 +       pi->srom_fem2g.triso = sprom->fem.ghz2.tr_iso;
3119 +       pi->srom_fem2g.antswctrllut = sprom->fem.ghz2.antswlut;
3120 +
3121 +       pi->srom_fem5g.tssipos = sprom->fem.ghz5.tssipos;
3122 +       pi->srom_fem5g.extpagain = sprom->fem.ghz5.extpa_gain;
3123 +       pi->srom_fem5g.pdetrange = sprom->fem.ghz5.pdet_range;
3124 +       pi->srom_fem5g.triso = sprom->fem.ghz5.tr_iso;
3125 +       if (sprom->fem.ghz5.antswlut)
3126 +               pi->srom_fem5g.antswctrllut = sprom->fem.ghz5.antswlut;
3127         else
3128 -               pi->srom_fem5g.antswctrllut =
3129 -                       (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
3130 +               pi->srom_fem5g.antswctrllut = sprom->fem.ghz2.antswlut;
3131
3132         wlc_phy_txpower_ipa_upd(pi);
3133
3134 -       pi->phy_txcore_disable_temp =
3135 -                       (s16) wlapi_getintvar(shim, BRCMS_SROM_TEMPTHRESH);
3136 +       pi->phy_txcore_disable_temp = sprom->tempthresh;
3137         if (pi->phy_txcore_disable_temp == 0)
3138                 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
3139
3140 -       pi->phy_tempsense_offset = (s8) wlapi_getintvar(shim,
3141 -                                                       BRCMS_SROM_TEMPOFFSET);
3142 +       pi->phy_tempsense_offset = sprom->tempoffset;
3143         if (pi->phy_tempsense_offset != 0) {
3144                 if (pi->phy_tempsense_offset >
3145                     (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET))
3146 @@ -14719,8 +14603,7 @@ static bool wlc_phy_txpwr_srom_read_nphy
3147         pi->phy_txcore_enable_temp =
3148                 pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
3149
3150 -       pi->phycal_tempdelta =
3151 -                       (u8) wlapi_getintvar(shim, BRCMS_SROM_PHYCAL_TEMPDELTA);
3152 +       pi->phycal_tempdelta = sprom->phycal_tempdelta;
3153         if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA)
3154                 pi->phycal_tempdelta = 0;
3155
3156 @@ -21462,7 +21345,7 @@ void wlc_phy_antsel_init(struct brcms_ph
3157                 write_phy_reg(pi, 0xc8, 0x0);
3158                 write_phy_reg(pi, 0xc9, 0x0);
3159
3160 -               ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
3161 +               bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc, mask, mask);
3162
3163                 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
3164                 mc &= ~MCTL_GPOUT_SEL_MASK;
3165 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
3166 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
3167 @@ -214,12 +214,3 @@ wlapi_copyto_objmem(struct phy_shim_info
3168  {
3169         brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
3170  }
3171 -
3172 -char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
3173 -{
3174 -       return getvar(physhim->wlc_hw->sih, id);
3175 -}
3176 -int wlapi_getintvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
3177 -{
3178 -       return getintvar(physhim->wlc_hw->sih, id);
3179 -}
3180 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
3181 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
3182 @@ -175,8 +175,5 @@ extern void wlapi_copyto_objmem(struct p
3183  extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim,
3184                                        u32 phy_mode);
3185  extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
3186 -extern char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id);
3187 -extern int wlapi_getintvar(struct phy_shim_info *physhim,
3188 -                          enum brcms_srom_id id);
3189
3190  #endif                         /* _BRCM_PHY_SHIM_H_ */
3191 --- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
3192 +++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
3193 @@ -22,232 +22,6 @@
3194  #include "types.h"
3195  #include "defs.h"
3196
3197 -enum brcms_srom_id {
3198 -       BRCMS_SROM_NULL,
3199 -       BRCMS_SROM_CONT,
3200 -       BRCMS_SROM_AA2G,
3201 -       BRCMS_SROM_AA5G,
3202 -       BRCMS_SROM_AG0,
3203 -       BRCMS_SROM_AG1,
3204 -       BRCMS_SROM_AG2,
3205 -       BRCMS_SROM_AG3,
3206 -       BRCMS_SROM_ANTSWCTL2G,
3207 -       BRCMS_SROM_ANTSWCTL5G,
3208 -       BRCMS_SROM_ANTSWITCH,
3209 -       BRCMS_SROM_BOARDFLAGS2,
3210 -       BRCMS_SROM_BOARDFLAGS,
3211 -       BRCMS_SROM_BOARDNUM,
3212 -       BRCMS_SROM_BOARDREV,
3213 -       BRCMS_SROM_BOARDTYPE,
3214 -       BRCMS_SROM_BW40PO,
3215 -       BRCMS_SROM_BWDUPPO,
3216 -       BRCMS_SROM_BXA2G,
3217 -       BRCMS_SROM_BXA5G,
3218 -       BRCMS_SROM_CC,
3219 -       BRCMS_SROM_CCK2GPO,
3220 -       BRCMS_SROM_CCKBW202GPO,
3221 -       BRCMS_SROM_CCKBW20UL2GPO,
3222 -       BRCMS_SROM_CCODE,
3223 -       BRCMS_SROM_CDDPO,
3224 -       BRCMS_SROM_DEVID,
3225 -       BRCMS_SROM_ET1MACADDR,
3226 -       BRCMS_SROM_EXTPAGAIN2G,
3227 -       BRCMS_SROM_EXTPAGAIN5G,
3228 -       BRCMS_SROM_FREQOFFSET_CORR,
3229 -       BRCMS_SROM_HW_IQCAL_EN,
3230 -       BRCMS_SROM_IL0MACADDR,
3231 -       BRCMS_SROM_IQCAL_SWP_DIS,
3232 -       BRCMS_SROM_LEDBH0,
3233 -       BRCMS_SROM_LEDBH1,
3234 -       BRCMS_SROM_LEDBH2,
3235 -       BRCMS_SROM_LEDBH3,
3236 -       BRCMS_SROM_LEDDC,
3237 -       BRCMS_SROM_LEGOFDM40DUPPO,
3238 -       BRCMS_SROM_LEGOFDMBW202GPO,
3239 -       BRCMS_SROM_LEGOFDMBW205GHPO,
3240 -       BRCMS_SROM_LEGOFDMBW205GLPO,
3241 -       BRCMS_SROM_LEGOFDMBW205GMPO,
3242 -       BRCMS_SROM_LEGOFDMBW20UL2GPO,
3243 -       BRCMS_SROM_LEGOFDMBW20UL5GHPO,
3244 -       BRCMS_SROM_LEGOFDMBW20UL5GLPO,
3245 -       BRCMS_SROM_LEGOFDMBW20UL5GMPO,
3246 -       BRCMS_SROM_MACADDR,
3247 -       BRCMS_SROM_MCS2GPO0,
3248 -       BRCMS_SROM_MCS2GPO1,
3249 -       BRCMS_SROM_MCS2GPO2,
3250 -       BRCMS_SROM_MCS2GPO3,
3251 -       BRCMS_SROM_MCS2GPO4,
3252 -       BRCMS_SROM_MCS2GPO5,
3253 -       BRCMS_SROM_MCS2GPO6,
3254 -       BRCMS_SROM_MCS2GPO7,
3255 -       BRCMS_SROM_MCS32PO,
3256 -       BRCMS_SROM_MCS5GHPO0,
3257 -       BRCMS_SROM_MCS5GHPO1,
3258 -       BRCMS_SROM_MCS5GHPO2,
3259 -       BRCMS_SROM_MCS5GHPO3,
3260 -       BRCMS_SROM_MCS5GHPO4,
3261 -       BRCMS_SROM_MCS5GHPO5,
3262 -       BRCMS_SROM_MCS5GHPO6,
3263 -       BRCMS_SROM_MCS5GHPO7,
3264 -       BRCMS_SROM_MCS5GLPO0,
3265 -       BRCMS_SROM_MCS5GLPO1,
3266 -       BRCMS_SROM_MCS5GLPO2,
3267 -       BRCMS_SROM_MCS5GLPO3,
3268 -       BRCMS_SROM_MCS5GLPO4,
3269 -       BRCMS_SROM_MCS5GLPO5,
3270 -       BRCMS_SROM_MCS5GLPO6,
3271 -       BRCMS_SROM_MCS5GLPO7,
3272 -       BRCMS_SROM_MCS5GPO0,
3273 -       BRCMS_SROM_MCS5GPO1,
3274 -       BRCMS_SROM_MCS5GPO2,
3275 -       BRCMS_SROM_MCS5GPO3,
3276 -       BRCMS_SROM_MCS5GPO4,
3277 -       BRCMS_SROM_MCS5GPO5,
3278 -       BRCMS_SROM_MCS5GPO6,
3279 -       BRCMS_SROM_MCS5GPO7,
3280 -       BRCMS_SROM_MCSBW202GPO,
3281 -       BRCMS_SROM_MCSBW205GHPO,
3282 -       BRCMS_SROM_MCSBW205GLPO,
3283 -       BRCMS_SROM_MCSBW205GMPO,
3284 -       BRCMS_SROM_MCSBW20UL2GPO,
3285 -       BRCMS_SROM_MCSBW20UL5GHPO,
3286 -       BRCMS_SROM_MCSBW20UL5GLPO,
3287 -       BRCMS_SROM_MCSBW20UL5GMPO,
3288 -       BRCMS_SROM_MCSBW402GPO,
3289 -       BRCMS_SROM_MCSBW405GHPO,
3290 -       BRCMS_SROM_MCSBW405GLPO,
3291 -       BRCMS_SROM_MCSBW405GMPO,
3292 -       BRCMS_SROM_MEASPOWER,
3293 -       BRCMS_SROM_OFDM2GPO,
3294 -       BRCMS_SROM_OFDM5GHPO,
3295 -       BRCMS_SROM_OFDM5GLPO,
3296 -       BRCMS_SROM_OFDM5GPO,
3297 -       BRCMS_SROM_OPO,
3298 -       BRCMS_SROM_PA0B0,
3299 -       BRCMS_SROM_PA0B1,
3300 -       BRCMS_SROM_PA0B2,
3301 -       BRCMS_SROM_PA0ITSSIT,
3302 -       BRCMS_SROM_PA0MAXPWR,
3303 -       BRCMS_SROM_PA1B0,
3304 -       BRCMS_SROM_PA1B1,
3305 -       BRCMS_SROM_PA1B2,
3306 -       BRCMS_SROM_PA1HIB0,
3307 -       BRCMS_SROM_PA1HIB1,
3308 -       BRCMS_SROM_PA1HIB2,
3309 -       BRCMS_SROM_PA1HIMAXPWR,
3310 -       BRCMS_SROM_PA1ITSSIT,
3311 -       BRCMS_SROM_PA1LOB0,
3312 -       BRCMS_SROM_PA1LOB1,
3313 -       BRCMS_SROM_PA1LOB2,
3314 -       BRCMS_SROM_PA1LOMAXPWR,
3315 -       BRCMS_SROM_PA1MAXPWR,
3316 -       BRCMS_SROM_PDETRANGE2G,
3317 -       BRCMS_SROM_PDETRANGE5G,
3318 -       BRCMS_SROM_PHYCAL_TEMPDELTA,
3319 -       BRCMS_SROM_RAWTEMPSENSE,
3320 -       BRCMS_SROM_REGREV,
3321 -       BRCMS_SROM_REV,
3322 -       BRCMS_SROM_RSSISAV2G,
3323 -       BRCMS_SROM_RSSISAV5G,
3324 -       BRCMS_SROM_RSSISMC2G,
3325 -       BRCMS_SROM_RSSISMC5G,
3326 -       BRCMS_SROM_RSSISMF2G,
3327 -       BRCMS_SROM_RSSISMF5G,
3328 -       BRCMS_SROM_RXCHAIN,
3329 -       BRCMS_SROM_RXPO2G,
3330 -       BRCMS_SROM_RXPO5G,
3331 -       BRCMS_SROM_STBCPO,
3332 -       BRCMS_SROM_TEMPCORRX,
3333 -       BRCMS_SROM_TEMPOFFSET,
3334 -       BRCMS_SROM_TEMPSENSE_OPTION,
3335 -       BRCMS_SROM_TEMPSENSE_SLOPE,
3336 -       BRCMS_SROM_TEMPTHRESH,
3337 -       BRCMS_SROM_TRI2G,
3338 -       BRCMS_SROM_TRI5GH,
3339 -       BRCMS_SROM_TRI5GL,
3340 -       BRCMS_SROM_TRI5G,
3341 -       BRCMS_SROM_TRISO2G,
3342 -       BRCMS_SROM_TRISO5G,
3343 -       BRCMS_SROM_TSSIPOS2G,
3344 -       BRCMS_SROM_TSSIPOS5G,
3345 -       BRCMS_SROM_TXCHAIN,
3346 -       /*
3347 -        * per-path identifiers (see srom.c)
3348 -        */
3349 -       BRCMS_SROM_ITT2GA0,
3350 -       BRCMS_SROM_ITT2GA1,
3351 -       BRCMS_SROM_ITT2GA2,
3352 -       BRCMS_SROM_ITT2GA3,
3353 -       BRCMS_SROM_ITT5GA0,
3354 -       BRCMS_SROM_ITT5GA1,
3355 -       BRCMS_SROM_ITT5GA2,
3356 -       BRCMS_SROM_ITT5GA3,
3357 -       BRCMS_SROM_MAXP2GA0,
3358 -       BRCMS_SROM_MAXP2GA1,
3359 -       BRCMS_SROM_MAXP2GA2,
3360 -       BRCMS_SROM_MAXP2GA3,
3361 -       BRCMS_SROM_MAXP5GA0,
3362 -       BRCMS_SROM_MAXP5GA1,
3363 -       BRCMS_SROM_MAXP5GA2,
3364 -       BRCMS_SROM_MAXP5GA3,
3365 -       BRCMS_SROM_MAXP5GHA0,
3366 -       BRCMS_SROM_MAXP5GHA1,
3367 -       BRCMS_SROM_MAXP5GHA2,
3368 -       BRCMS_SROM_MAXP5GHA3,
3369 -       BRCMS_SROM_MAXP5GLA0,
3370 -       BRCMS_SROM_MAXP5GLA1,
3371 -       BRCMS_SROM_MAXP5GLA2,
3372 -       BRCMS_SROM_MAXP5GLA3,
3373 -       BRCMS_SROM_PA2GW0A0,
3374 -       BRCMS_SROM_PA2GW0A1,
3375 -       BRCMS_SROM_PA2GW0A2,
3376 -       BRCMS_SROM_PA2GW0A3,
3377 -       BRCMS_SROM_PA2GW1A0,
3378 -       BRCMS_SROM_PA2GW1A1,
3379 -       BRCMS_SROM_PA2GW1A2,
3380 -       BRCMS_SROM_PA2GW1A3,
3381 -       BRCMS_SROM_PA2GW2A0,
3382 -       BRCMS_SROM_PA2GW2A1,
3383 -       BRCMS_SROM_PA2GW2A2,
3384 -       BRCMS_SROM_PA2GW2A3,
3385 -       BRCMS_SROM_PA5GHW0A0,
3386 -       BRCMS_SROM_PA5GHW0A1,
3387 -       BRCMS_SROM_PA5GHW0A2,
3388 -       BRCMS_SROM_PA5GHW0A3,
3389 -       BRCMS_SROM_PA5GHW1A0,
3390 -       BRCMS_SROM_PA5GHW1A1,
3391 -       BRCMS_SROM_PA5GHW1A2,
3392 -       BRCMS_SROM_PA5GHW1A3,
3393 -       BRCMS_SROM_PA5GHW2A0,
3394 -       BRCMS_SROM_PA5GHW2A1,
3395 -       BRCMS_SROM_PA5GHW2A2,
3396 -       BRCMS_SROM_PA5GHW2A3,
3397 -       BRCMS_SROM_PA5GLW0A0,
3398 -       BRCMS_SROM_PA5GLW0A1,
3399 -       BRCMS_SROM_PA5GLW0A2,
3400 -       BRCMS_SROM_PA5GLW0A3,
3401 -       BRCMS_SROM_PA5GLW1A0,
3402 -       BRCMS_SROM_PA5GLW1A1,
3403 -       BRCMS_SROM_PA5GLW1A2,
3404 -       BRCMS_SROM_PA5GLW1A3,
3405 -       BRCMS_SROM_PA5GLW2A0,
3406 -       BRCMS_SROM_PA5GLW2A1,
3407 -       BRCMS_SROM_PA5GLW2A2,
3408 -       BRCMS_SROM_PA5GLW2A3,
3409 -       BRCMS_SROM_PA5GW0A0,
3410 -       BRCMS_SROM_PA5GW0A1,
3411 -       BRCMS_SROM_PA5GW0A2,
3412 -       BRCMS_SROM_PA5GW0A3,
3413 -       BRCMS_SROM_PA5GW1A0,
3414 -       BRCMS_SROM_PA5GW1A1,
3415 -       BRCMS_SROM_PA5GW1A2,
3416 -       BRCMS_SROM_PA5GW1A3,
3417 -       BRCMS_SROM_PA5GW2A0,
3418 -       BRCMS_SROM_PA5GW2A1,
3419 -       BRCMS_SROM_PA5GW2A2,
3420 -       BRCMS_SROM_PA5GW2A3,
3421 -};
3422 -
3423  #define        BRCMS_NUMRATES  16      /* max # of rates in a rateset */
3424
3425  /* phy types */
3426 @@ -565,8 +339,6 @@ extern void brcms_c_ampdu_flush(struct b
3427                             struct ieee80211_sta *sta, u16 tid);
3428  extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
3429                                          u8 ba_wsize, uint max_rx_ampdu_bytes);
3430 -extern char *getvar(struct si_pub *sih, enum brcms_srom_id id);
3431 -extern int getintvar(struct si_pub *sih, enum brcms_srom_id id);
3432  extern int brcms_c_module_register(struct brcms_pub *pub,
3433                                    const char *name, struct brcms_info *hdl,
3434                                    int (*down_fn)(void *handle));
3435 --- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
3436 +++ /dev/null
3437 @@ -1,980 +0,0 @@
3438 -/*
3439 - * Copyright (c) 2010 Broadcom Corporation
3440 - *
3441 - * Permission to use, copy, modify, and/or distribute this software for any
3442 - * purpose with or without fee is hereby granted, provided that the above
3443 - * copyright notice and this permission notice appear in all copies.
3444 - *
3445 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3446 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3447 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
3448 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3449 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
3450 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
3451 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3452 - */
3453 -
3454 -#include <linux/kernel.h>
3455 -#include <linux/string.h>
3456 -#include <linux/io.h>
3457 -#include <linux/etherdevice.h>
3458 -#include <linux/crc8.h>
3459 -#include <stdarg.h>
3460 -
3461 -#include <chipcommon.h>
3462 -#include <brcmu_utils.h>
3463 -#include "pub.h"
3464 -#include "nicpci.h"
3465 -#include "aiutils.h"
3466 -#include "otp.h"
3467 -#include "srom.h"
3468 -#include "soc.h"
3469 -
3470 -/*
3471 - * SROM CRC8 polynomial value:
3472 - *
3473 - * x^8 + x^7 +x^6 + x^4 + x^2 + 1
3474 - */
3475 -#define SROM_CRC8_POLY         0xAB
3476 -
3477 -/* Maximum srom: 6 Kilobits == 768 bytes */
3478 -#define        SROM_MAX                768
3479 -
3480 -/* PCI fields */
3481 -#define PCI_F0DEVID            48
3482 -
3483 -#define        SROM_WORDS              64
3484 -
3485 -#define        SROM_SSID               2
3486 -
3487 -#define        SROM_WL1LHMAXP          29
3488 -
3489 -#define        SROM_WL1LPAB0           30
3490 -#define        SROM_WL1LPAB1           31
3491 -#define        SROM_WL1LPAB2           32
3492 -
3493 -#define        SROM_WL1HPAB0           33
3494 -#define        SROM_WL1HPAB1           34
3495 -#define        SROM_WL1HPAB2           35
3496 -
3497 -#define        SROM_MACHI_IL0          36
3498 -#define        SROM_MACMID_IL0         37
3499 -#define        SROM_MACLO_IL0          38
3500 -#define        SROM_MACHI_ET1          42
3501 -#define        SROM_MACMID_ET1         43
3502 -#define        SROM_MACLO_ET1          44
3503 -
3504 -#define        SROM_BXARSSI2G          40
3505 -#define        SROM_BXARSSI5G          41
3506 -
3507 -#define        SROM_TRI52G             42
3508 -#define        SROM_TRI5GHL            43
3509 -
3510 -#define        SROM_RXPO52G            45
3511 -
3512 -#define        SROM_AABREV             46
3513 -/* Fields in AABREV */
3514 -#define        SROM_BR_MASK            0x00ff
3515 -#define        SROM_CC_MASK            0x0f00
3516 -#define        SROM_CC_SHIFT           8
3517 -#define        SROM_AA0_MASK           0x3000
3518 -#define        SROM_AA0_SHIFT          12
3519 -#define        SROM_AA1_MASK           0xc000
3520 -#define        SROM_AA1_SHIFT          14
3521 -
3522 -#define        SROM_WL0PAB0            47
3523 -#define        SROM_WL0PAB1            48
3524 -#define        SROM_WL0PAB2            49
3525 -
3526 -#define        SROM_LEDBH10            50
3527 -#define        SROM_LEDBH32            51
3528 -
3529 -#define        SROM_WL10MAXP           52
3530 -
3531 -#define        SROM_WL1PAB0            53
3532 -#define        SROM_WL1PAB1            54
3533 -#define        SROM_WL1PAB2            55
3534 -
3535 -#define        SROM_ITT                56
3536 -
3537 -#define        SROM_BFL                57
3538 -#define        SROM_BFL2               28
3539 -
3540 -#define        SROM_AG10               58
3541 -
3542 -#define        SROM_CCODE              59
3543 -
3544 -#define        SROM_OPO                60
3545 -
3546 -#define        SROM_CRCREV             63
3547 -
3548 -#define        SROM4_WORDS             220
3549 -
3550 -#define SROM4_TXCHAIN_MASK     0x000f
3551 -#define SROM4_RXCHAIN_MASK     0x00f0
3552 -#define SROM4_SWITCH_MASK      0xff00
3553 -
3554 -/* Per-path fields */
3555 -#define        MAX_PATH_SROM           4
3556 -
3557 -#define        SROM4_CRCREV            219
3558 -
3559 -/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
3560 - * This is acombined srom for both MIMO and SISO boards, usable in
3561 - * the .130 4Kilobit OTP with hardware redundancy.
3562 - */
3563 -#define        SROM8_BREV              65
3564 -
3565 -#define        SROM8_BFL0              66
3566 -#define        SROM8_BFL1              67
3567 -#define        SROM8_BFL2              68
3568 -#define        SROM8_BFL3              69
3569 -
3570 -#define        SROM8_MACHI             70
3571 -#define        SROM8_MACMID            71
3572 -#define        SROM8_MACLO             72
3573 -
3574 -#define        SROM8_CCODE             73
3575 -#define        SROM8_REGREV            74
3576 -
3577 -#define        SROM8_LEDBH10           75
3578 -#define        SROM8_LEDBH32           76
3579 -
3580 -#define        SROM8_LEDDC             77
3581 -
3582 -#define        SROM8_AA                78
3583 -
3584 -#define        SROM8_AG10              79
3585 -#define        SROM8_AG32              80
3586 -
3587 -#define        SROM8_TXRXC             81
3588 -
3589 -#define        SROM8_BXARSSI2G         82
3590 -#define        SROM8_BXARSSI5G         83
3591 -#define        SROM8_TRI52G            84
3592 -#define        SROM8_TRI5GHL           85
3593 -#define        SROM8_RXPO52G           86
3594 -
3595 -#define SROM8_FEM2G            87
3596 -#define SROM8_FEM5G            88
3597 -#define SROM8_FEM_ANTSWLUT_MASK                0xf800
3598 -#define SROM8_FEM_ANTSWLUT_SHIFT       11
3599 -#define SROM8_FEM_TR_ISO_MASK          0x0700
3600 -#define SROM8_FEM_TR_ISO_SHIFT         8
3601 -#define SROM8_FEM_PDET_RANGE_MASK      0x00f8
3602 -#define SROM8_FEM_PDET_RANGE_SHIFT     3
3603 -#define SROM8_FEM_EXTPA_GAIN_MASK      0x0006
3604 -#define SROM8_FEM_EXTPA_GAIN_SHIFT     1
3605 -#define SROM8_FEM_TSSIPOS_MASK         0x0001
3606 -#define SROM8_FEM_TSSIPOS_SHIFT                0
3607 -
3608 -#define SROM8_THERMAL          89
3609 -
3610 -/* Temp sense related entries */
3611 -#define SROM8_MPWR_RAWTS               90
3612 -#define SROM8_TS_SLP_OPT_CORRX 91
3613 -/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
3614 - * IQSWP: IQ CAL swap disable */
3615 -#define SROM8_FOC_HWIQ_IQSWP   92
3616 -
3617 -/* Temperature delta for PHY calibration */
3618 -#define SROM8_PHYCAL_TEMPDELTA 93
3619 -
3620 -/* Per-path offsets & fields */
3621 -#define        SROM8_PATH0             96
3622 -#define        SROM8_PATH1             112
3623 -#define        SROM8_PATH2             128
3624 -#define        SROM8_PATH3             144
3625 -
3626 -#define        SROM8_2G_ITT_MAXP       0
3627 -#define        SROM8_2G_PA             1
3628 -#define        SROM8_5G_ITT_MAXP       4
3629 -#define        SROM8_5GLH_MAXP         5
3630 -#define        SROM8_5G_PA             6
3631 -#define        SROM8_5GL_PA            9
3632 -#define        SROM8_5GH_PA            12
3633 -
3634 -/* All the miriad power offsets */
3635 -#define        SROM8_2G_CCKPO          160
3636 -
3637 -#define        SROM8_2G_OFDMPO         161
3638 -#define        SROM8_5G_OFDMPO         163
3639 -#define        SROM8_5GL_OFDMPO        165
3640 -#define        SROM8_5GH_OFDMPO        167
3641 -
3642 -#define        SROM8_2G_MCSPO          169
3643 -#define        SROM8_5G_MCSPO          177
3644 -#define        SROM8_5GL_MCSPO         185
3645 -#define        SROM8_5GH_MCSPO         193
3646 -
3647 -#define        SROM8_CDDPO             201
3648 -#define        SROM8_STBCPO            202
3649 -#define        SROM8_BW40PO            203
3650 -#define        SROM8_BWDUPPO           204
3651 -
3652 -/* SISO PA parameters are in the path0 spaces */
3653 -#define        SROM8_SISO              96
3654 -
3655 -/* Legacy names for SISO PA paramters */
3656 -#define        SROM8_W0_ITTMAXP        (SROM8_SISO + SROM8_2G_ITT_MAXP)
3657 -#define        SROM8_W0_PAB0           (SROM8_SISO + SROM8_2G_PA)
3658 -#define        SROM8_W0_PAB1           (SROM8_SISO + SROM8_2G_PA + 1)
3659 -#define        SROM8_W0_PAB2           (SROM8_SISO + SROM8_2G_PA + 2)
3660 -#define        SROM8_W1_ITTMAXP        (SROM8_SISO + SROM8_5G_ITT_MAXP)
3661 -#define        SROM8_W1_MAXP_LCHC      (SROM8_SISO + SROM8_5GLH_MAXP)
3662 -#define        SROM8_W1_PAB0           (SROM8_SISO + SROM8_5G_PA)
3663 -#define        SROM8_W1_PAB1           (SROM8_SISO + SROM8_5G_PA + 1)
3664 -#define        SROM8_W1_PAB2           (SROM8_SISO + SROM8_5G_PA + 2)
3665 -#define        SROM8_W1_PAB0_LC        (SROM8_SISO + SROM8_5GL_PA)
3666 -#define        SROM8_W1_PAB1_LC        (SROM8_SISO + SROM8_5GL_PA + 1)
3667 -#define        SROM8_W1_PAB2_LC        (SROM8_SISO + SROM8_5GL_PA + 2)
3668 -#define        SROM8_W1_PAB0_HC        (SROM8_SISO + SROM8_5GH_PA)
3669 -#define        SROM8_W1_PAB1_HC        (SROM8_SISO + SROM8_5GH_PA + 1)
3670 -#define        SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
3671 -
3672 -/* SROM REV 9 */
3673 -#define SROM9_2GPO_CCKBW20     160
3674 -#define SROM9_2GPO_CCKBW20UL   161
3675 -#define SROM9_2GPO_LOFDMBW20   162
3676 -#define SROM9_2GPO_LOFDMBW20UL 164
3677 -
3678 -#define SROM9_5GLPO_LOFDMBW20  166
3679 -#define SROM9_5GLPO_LOFDMBW20UL        168
3680 -#define SROM9_5GMPO_LOFDMBW20  170
3681 -#define SROM9_5GMPO_LOFDMBW20UL        172
3682 -#define SROM9_5GHPO_LOFDMBW20  174
3683 -#define SROM9_5GHPO_LOFDMBW20UL        176
3684 -
3685 -#define SROM9_2GPO_MCSBW20     178
3686 -#define SROM9_2GPO_MCSBW20UL   180
3687 -#define SROM9_2GPO_MCSBW40     182
3688 -
3689 -#define SROM9_5GLPO_MCSBW20    184
3690 -#define SROM9_5GLPO_MCSBW20UL  186
3691 -#define SROM9_5GLPO_MCSBW40    188
3692 -#define SROM9_5GMPO_MCSBW20    190
3693 -#define SROM9_5GMPO_MCSBW20UL  192
3694 -#define SROM9_5GMPO_MCSBW40    194
3695 -#define SROM9_5GHPO_MCSBW20    196
3696 -#define SROM9_5GHPO_MCSBW20UL  198
3697 -#define SROM9_5GHPO_MCSBW40    200
3698 -
3699 -#define SROM9_PO_MCS32         202
3700 -#define SROM9_PO_LOFDM40DUP    203
3701 -
3702 -/* SROM flags (see sromvar_t) */
3703 -
3704 -/* value continues as described by the next entry */
3705 -#define SRFL_MORE      1
3706 -#define        SRFL_NOFFS      2       /* value bits can't be all one's */
3707 -#define        SRFL_PRHEX      4       /* value is in hexdecimal format */
3708 -#define        SRFL_PRSIGN     8       /* value is in signed decimal format */
3709 -#define        SRFL_CCODE      0x10    /* value is in country code format */
3710 -#define        SRFL_ETHADDR    0x20    /* value is an Ethernet address */
3711 -#define SRFL_LEDDC     0x40    /* value is an LED duty cycle */
3712 -/* do not generate a nvram param, entry is for mfgc */
3713 -#define SRFL_NOVAR     0x80
3714 -
3715 -/* Max. nvram variable table size */
3716 -#define        MAXSZ_NVRAM_VARS        4096
3717 -
3718 -/*
3719 - * indicates type of value.
3720 - */
3721 -enum brcms_srom_var_type {
3722 -       BRCMS_SROM_STRING,
3723 -       BRCMS_SROM_SNUMBER,
3724 -       BRCMS_SROM_UNUMBER
3725 -};
3726 -
3727 -/*
3728 - * storage type for srom variable.
3729 - *
3730 - * var_list: for linked list operations.
3731 - * varid: identifier of the variable.
3732 - * var_type: type of variable.
3733 - * buf: variable value when var_type == BRCMS_SROM_STRING.
3734 - * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
3735 - * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
3736 - */
3737 -struct brcms_srom_list_head {
3738 -       struct list_head var_list;
3739 -       enum brcms_srom_id varid;
3740 -       enum brcms_srom_var_type var_type;
3741 -       union {
3742 -               char buf[0];
3743 -               u32 uval;
3744 -               s32 sval;
3745 -       };
3746 -};
3747 -
3748 -struct brcms_sromvar {
3749 -       enum brcms_srom_id varid;
3750 -       u32 revmask;
3751 -       u32 flags;
3752 -       u16 off;
3753 -       u16 mask;
3754 -};
3755 -
3756 -struct brcms_varbuf {
3757 -       char *base;             /* pointer to buffer base */
3758 -       char *buf;              /* pointer to current position */
3759 -       unsigned int size;      /* current (residual) size in bytes */
3760 -};
3761 -
3762 -/*
3763 - * Assumptions:
3764 - * - Ethernet address spans across 3 consecutive words
3765 - *
3766 - * Table rules:
3767 - * - Add multiple entries next to each other if a value spans across multiple
3768 - *   words (even multiple fields in the same word) with each entry except the
3769 - *   last having it's SRFL_MORE bit set.
3770 - * - Ethernet address entry does not follow above rule and must not have
3771 - *   SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
3772 - * - The last entry's name field must be NULL to indicate the end of the table.
3773 - *   Other entries must have non-NULL name.
3774 - */
3775 -static const struct brcms_sromvar pci_sromvars[] = {
3776 -       {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
3777 -        0xffff},
3778 -       {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
3779 -       {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
3780 -        0xffff},
3781 -       {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
3782 -       {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
3783 -        0xffff},
3784 -       {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
3785 -       {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
3786 -       {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
3787 -       {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
3788 -       {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
3789 -       {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
3790 -       {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
3791 -       {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
3792 -       {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
3793 -       {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
3794 -       {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
3795 -       {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
3796 -       {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
3797 -       {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
3798 -       {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
3799 -       {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
3800 -       {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
3801 -       {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
3802 -       {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
3803 -       {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
3804 -       {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
3805 -       {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
3806 -       {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
3807 -       {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
3808 -       {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
3809 -       {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
3810 -       {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
3811 -       {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
3812 -       {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
3813 -       {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
3814 -       {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
3815 -       {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
3816 -       {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
3817 -       {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
3818 -       {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
3819 -       {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
3820 -       {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
3821 -       {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
3822 -       {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
3823 -       {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
3824 -       {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
3825 -       {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
3826 -       {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
3827 -       {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
3828 -       {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
3829 -       {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
3830 -       {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
3831 -       {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
3832 -        SROM4_TXCHAIN_MASK},
3833 -       {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
3834 -        SROM4_RXCHAIN_MASK},
3835 -       {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
3836 -        SROM4_SWITCH_MASK},
3837 -       {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
3838 -        SROM8_FEM_TSSIPOS_MASK},
3839 -       {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
3840 -        SROM8_FEM_EXTPA_GAIN_MASK},
3841 -       {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
3842 -        SROM8_FEM_PDET_RANGE_MASK},
3843 -       {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
3844 -       {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
3845 -        SROM8_FEM_ANTSWLUT_MASK},
3846 -       {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
3847 -        SROM8_FEM_TSSIPOS_MASK},
3848 -       {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
3849 -        SROM8_FEM_EXTPA_GAIN_MASK},
3850 -       {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
3851 -        SROM8_FEM_PDET_RANGE_MASK},
3852 -       {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
3853 -       {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
3854 -        SROM8_FEM_ANTSWLUT_MASK},
3855 -       {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
3856 -       {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
3857 -
3858 -       {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
3859 -       {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
3860 -       {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
3861 -        0xffff},
3862 -       {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
3863 -        0x01ff},
3864 -       {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
3865 -        0xfe00},
3866 -       {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
3867 -        SROM8_TS_SLP_OPT_CORRX, 0x00ff},
3868 -       {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
3869 -        0xfc00},
3870 -       {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
3871 -        SROM8_TS_SLP_OPT_CORRX, 0x0300},
3872 -       {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
3873 -        SROM8_FOC_HWIQ_IQSWP, 0x000f},
3874 -       {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
3875 -        0x0010},
3876 -       {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
3877 -        0x0020},
3878 -       {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
3879 -        0x00ff},
3880 -
3881 -       {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
3882 -       {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
3883 -       {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
3884 -       {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
3885 -       {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
3886 -       {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
3887 -       {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
3888 -       {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
3889 -       {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
3890 -       {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
3891 -       {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
3892 -       {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
3893 -       {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
3894 -       {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
3895 -       {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
3896 -       {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
3897 -       {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
3898 -       {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
3899 -       {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
3900 -       {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
3901 -       {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
3902 -       {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
3903 -       {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
3904 -       {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
3905 -       {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
3906 -       {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
3907 -       {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
3908 -       {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
3909 -       {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
3910 -       {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
3911 -       {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
3912 -       {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
3913 -       {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
3914 -       {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
3915 -       {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
3916 -       {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
3917 -       {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
3918 -       {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
3919 -       {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
3920 -       {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
3921 -       {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
3922 -       {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
3923 -       {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
3924 -       {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
3925 -       {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
3926 -
3927 -       /* power per rate from sromrev 9 */
3928 -       {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
3929 -       {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
3930 -       {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
3931 -        SROM9_2GPO_LOFDMBW20, 0xffff},
3932 -       {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
3933 -       {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
3934 -        SROM9_2GPO_LOFDMBW20UL, 0xffff},
3935 -       {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
3936 -       {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
3937 -        SROM9_5GLPO_LOFDMBW20, 0xffff},
3938 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
3939 -       {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
3940 -        SROM9_5GLPO_LOFDMBW20UL, 0xffff},
3941 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
3942 -       {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
3943 -        SROM9_5GMPO_LOFDMBW20, 0xffff},
3944 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
3945 -       {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
3946 -        SROM9_5GMPO_LOFDMBW20UL, 0xffff},
3947 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
3948 -       {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
3949 -        SROM9_5GHPO_LOFDMBW20, 0xffff},
3950 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
3951 -       {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
3952 -        SROM9_5GHPO_LOFDMBW20UL, 0xffff},
3953 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
3954 -       {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
3955 -        0xffff},
3956 -       {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
3957 -       {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
3958 -        0xffff},
3959 -       {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
3960 -       {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
3961 -        0xffff},
3962 -       {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
3963 -       {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
3964 -        0xffff},
3965 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
3966 -       {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
3967 -        SROM9_5GLPO_MCSBW20UL, 0xffff},
3968 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
3969 -       {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
3970 -        0xffff},
3971 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
3972 -       {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
3973 -        0xffff},
3974 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
3975 -       {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
3976 -        SROM9_5GMPO_MCSBW20UL, 0xffff},
3977 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
3978 -       {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
3979 -        0xffff},
3980 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
3981 -       {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
3982 -        0xffff},
3983 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
3984 -       {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
3985 -        SROM9_5GHPO_MCSBW20UL, 0xffff},
3986 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
3987 -       {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
3988 -        0xffff},
3989 -       {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
3990 -       {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
3991 -       {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
3992 -
3993 -       {BRCMS_SROM_NULL, 0, 0, 0, 0}
3994 -};
3995 -
3996 -static const struct brcms_sromvar perpath_pci_sromvars[] = {
3997 -       {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
3998 -       {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
3999 -       {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
4000 -       {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
4001 -       {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
4002 -       {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
4003 -       {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
4004 -       {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
4005 -       {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
4006 -       {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
4007 -       {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
4008 -       {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
4009 -       {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
4010 -       {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
4011 -        0xffff},
4012 -       {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
4013 -        0xffff},
4014 -       {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
4015 -       {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
4016 -        0xffff},
4017 -       {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
4018 -        0xffff},
4019 -       {BRCMS_SROM_NULL, 0, 0, 0, 0}
4020 -};
4021 -
4022 -/* crc table has the same contents for every device instance, so it can be
4023 - * shared between devices. */
4024 -static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
4025 -
4026 -static uint mask_shift(u16 mask)
4027 -{
4028 -       uint i;
4029 -       for (i = 0; i < (sizeof(mask) << 3); i++) {
4030 -               if (mask & (1 << i))
4031 -                       return i;
4032 -       }
4033 -       return 0;
4034 -}
4035 -
4036 -static uint mask_width(u16 mask)
4037 -{
4038 -       int i;
4039 -       for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
4040 -               if (mask & (1 << i))
4041 -                       return (uint) (i - mask_shift(mask) + 1);
4042 -       }
4043 -       return 0;
4044 -}
4045 -
4046 -static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
4047 -{
4048 -       while (nwords--)
4049 -               *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
4050 -}
4051 -
4052 -static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
4053 -{
4054 -       while (nwords--)
4055 -               *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
4056 -}
4057 -
4058 -/*
4059 - * convert binary srom data into linked list of srom variable items.
4060 - */
4061 -static int
4062 -_initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
4063 -{
4064 -       struct brcms_srom_list_head *entry;
4065 -       enum brcms_srom_id id;
4066 -       u16 w;
4067 -       u32 val = 0;
4068 -       const struct brcms_sromvar *srv;
4069 -       uint width;
4070 -       uint flags;
4071 -       u32 sr = (1 << sromrev);
4072 -       uint p;
4073 -       uint pb =  SROM8_PATH0;
4074 -       const uint psz = SROM8_PATH1 - SROM8_PATH0;
4075 -
4076 -       /* first store the srom revision */
4077 -       entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
4078 -       if (!entry)
4079 -               return -ENOMEM;
4080 -
4081 -       entry->varid = BRCMS_SROM_REV;
4082 -       entry->var_type = BRCMS_SROM_UNUMBER;
4083 -       entry->uval = sromrev;
4084 -       list_add(&entry->var_list, var_list);
4085 -
4086 -       for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
4087 -               enum brcms_srom_var_type type;
4088 -               u8 ea[ETH_ALEN];
4089 -               u8 extra_space = 0;
4090 -
4091 -               if ((srv->revmask & sr) == 0)
4092 -                       continue;
4093 -
4094 -               flags = srv->flags;
4095 -               id = srv->varid;
4096 -
4097 -               /* This entry is for mfgc only. Don't generate param for it, */
4098 -               if (flags & SRFL_NOVAR)
4099 -                       continue;
4100 -
4101 -               if (flags & SRFL_ETHADDR) {
4102 -                       /*
4103 -                        * stored in string format XX:XX:XX:XX:XX:XX (17 chars)
4104 -                        */
4105 -                       ea[0] = (srom[srv->off] >> 8) & 0xff;
4106 -                       ea[1] = srom[srv->off] & 0xff;
4107 -                       ea[2] = (srom[srv->off + 1] >> 8) & 0xff;
4108 -                       ea[3] = srom[srv->off + 1] & 0xff;
4109 -                       ea[4] = (srom[srv->off + 2] >> 8) & 0xff;
4110 -                       ea[5] = srom[srv->off + 2] & 0xff;
4111 -                       /* 17 characters + string terminator - union size */
4112 -                       extra_space = 18 - sizeof(s32);
4113 -                       type = BRCMS_SROM_STRING;
4114 -               } else {
4115 -                       w = srom[srv->off];
4116 -                       val = (w & srv->mask) >> mask_shift(srv->mask);
4117 -                       width = mask_width(srv->mask);
4118 -
4119 -                       while (srv->flags & SRFL_MORE) {
4120 -                               srv++;
4121 -                               if (srv->off == 0)
4122 -                                       continue;
4123 -
4124 -                               w = srom[srv->off];
4125 -                               val +=
4126 -                                   ((w & srv->mask) >> mask_shift(srv->
4127 -                                                                  mask)) <<
4128 -                                   width;
4129 -                               width += mask_width(srv->mask);
4130 -                       }
4131 -
4132 -                       if ((flags & SRFL_NOFFS)
4133 -                           && ((int)val == (1 << width) - 1))
4134 -                               continue;
4135 -
4136 -                       if (flags & SRFL_CCODE) {
4137 -                               type = BRCMS_SROM_STRING;
4138 -                       } else if (flags & SRFL_LEDDC) {
4139 -                               /* LED Powersave duty cycle has to be scaled:
4140 -                                *(oncount >> 24) (offcount >> 8)
4141 -                                */
4142 -                               u32 w32 = /* oncount */
4143 -                                         (((val >> 8) & 0xff) << 24) |
4144 -                                         /* offcount */
4145 -                                         (((val & 0xff)) << 8);
4146 -                               type = BRCMS_SROM_UNUMBER;
4147 -                               val = w32;
4148 -                       } else if ((flags & SRFL_PRSIGN)
4149 -                                && (val & (1 << (width - 1)))) {
4150 -                               type = BRCMS_SROM_SNUMBER;
4151 -                               val |= ~0 << width;
4152 -                       } else
4153 -                               type = BRCMS_SROM_UNUMBER;
4154 -               }
4155 -
4156 -               entry = kzalloc(sizeof(struct brcms_srom_list_head) +
4157 -                               extra_space, GFP_KERNEL);
4158 -               if (!entry)
4159 -                       return -ENOMEM;
4160 -               entry->varid = id;
4161 -               entry->var_type = type;
4162 -               if (flags & SRFL_ETHADDR) {
4163 -                       snprintf(entry->buf, 18, "%pM", ea);
4164 -               } else if (flags & SRFL_CCODE) {
4165 -                       if (val == 0)
4166 -                               entry->buf[0] = '\0';
4167 -                       else
4168 -                               snprintf(entry->buf, 3, "%c%c",
4169 -                                        (val >> 8), (val & 0xff));
4170 -               } else {
4171 -                       entry->uval = val;
4172 -               }
4173 -
4174 -               list_add(&entry->var_list, var_list);
4175 -       }
4176 -
4177 -       for (p = 0; p < MAX_PATH_SROM; p++) {
4178 -               for (srv = perpath_pci_sromvars;
4179 -                    srv->varid != BRCMS_SROM_NULL; srv++) {
4180 -                       if ((srv->revmask & sr) == 0)
4181 -                               continue;
4182 -
4183 -                       if (srv->flags & SRFL_NOVAR)
4184 -                               continue;
4185 -
4186 -                       w = srom[pb + srv->off];
4187 -                       val = (w & srv->mask) >> mask_shift(srv->mask);
4188 -                       width = mask_width(srv->mask);
4189 -
4190 -                       /* Cheating: no per-path var is more than
4191 -                        * 1 word */
4192 -                       if ((srv->flags & SRFL_NOFFS)
4193 -                           && ((int)val == (1 << width) - 1))
4194 -                               continue;
4195 -
4196 -                       entry =
4197 -                           kzalloc(sizeof(struct brcms_srom_list_head),
4198 -                                   GFP_KERNEL);
4199 -                       if (!entry)
4200 -                               return -ENOMEM;
4201 -                       entry->varid = srv->varid+p;
4202 -                       entry->var_type = BRCMS_SROM_UNUMBER;
4203 -                       entry->uval = val;
4204 -                       list_add(&entry->var_list, var_list);
4205 -               }
4206 -               pb += psz;
4207 -       }
4208 -       return 0;
4209 -}
4210 -
4211 -/*
4212 - * The crc check is done on a little-endian array, we need
4213 - * to switch the bytes around before checking crc (and
4214 - * then switch it back).
4215 - */
4216 -static int do_crc_check(u16 *buf, unsigned nwords)
4217 -{
4218 -       u8 crc;
4219 -
4220 -       cpu_to_le16_buf(buf, nwords);
4221 -       crc = crc8(brcms_srom_crc8_table, (void *)buf, nwords << 1, CRC8_INIT_VALUE);
4222 -       le16_to_cpu_buf(buf, nwords);
4223 -
4224 -       return crc == CRC8_GOOD_VALUE(brcms_srom_crc8_table);
4225 -}
4226 -
4227 -/*
4228 - * Read in and validate sprom.
4229 - * Return 0 on success, nonzero on error.
4230 - */
4231 -static int
4232 -sprom_read_pci(struct si_pub *sih, u16 *buf, uint nwords, bool check_crc)
4233 -{
4234 -       int err = 0;
4235 -       uint i;
4236 -       struct bcma_device *core;
4237 -       uint sprom_offset;
4238 -
4239 -       /* determine core to read */
4240 -       if (ai_get_ccrev(sih) < 32) {
4241 -               core = ai_findcore(sih, BCMA_CORE_80211, 0);
4242 -               sprom_offset = PCI_BAR0_SPROM_OFFSET;
4243 -       } else {
4244 -               core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
4245 -               sprom_offset = CHIPCREGOFFS(sromotp);
4246 -       }
4247 -
4248 -       /* read the sprom */
4249 -       for (i = 0; i < nwords; i++)
4250 -               buf[i] = bcma_read16(core, sprom_offset+i*2);
4251 -
4252 -       if (buf[0] == 0xffff)
4253 -               /*
4254 -                * The hardware thinks that an srom that starts with
4255 -                * 0xffff is blank, regardless of the rest of the
4256 -                * content, so declare it bad.
4257 -                */
4258 -               return -ENODATA;
4259 -
4260 -       if (check_crc && !do_crc_check(buf, nwords))
4261 -               err = -EIO;
4262 -
4263 -       return err;
4264 -}
4265 -
4266 -static int otp_read_pci(struct si_pub *sih, u16 *buf, uint nwords)
4267 -{
4268 -       u8 *otp;
4269 -       uint sz = OTP_SZ_MAX / 2;       /* size in words */
4270 -       int err = 0;
4271 -
4272 -       otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
4273 -       if (otp == NULL)
4274 -               return -ENOMEM;
4275 -
4276 -       err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
4277 -
4278 -       sz = min_t(uint, sz, nwords);
4279 -       memcpy(buf, otp, sz * 2);
4280 -
4281 -       kfree(otp);
4282 -
4283 -       /* Check CRC */
4284 -       if (buf[0] == 0xffff)
4285 -               /* The hardware thinks that an srom that starts with 0xffff
4286 -                * is blank, regardless of the rest of the content, so declare
4287 -                * it bad.
4288 -                */
4289 -               return -ENODATA;
4290 -
4291 -       /* fixup the endianness so crc8 will pass */
4292 -       cpu_to_le16_buf(buf, sz);
4293 -       if (crc8(brcms_srom_crc8_table, (u8 *) buf, sz * 2,
4294 -                CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
4295 -               err = -EIO;
4296 -       else
4297 -               /* now correct the endianness of the byte array */
4298 -               le16_to_cpu_buf(buf, sz);
4299 -
4300 -       return err;
4301 -}
4302 -
4303 -/*
4304 - * Initialize nonvolatile variable table from sprom.
4305 - * Return 0 on success, nonzero on error.
4306 - */
4307 -int srom_var_init(struct si_pub *sih)
4308 -{
4309 -       u16 *srom;
4310 -       u8 sromrev = 0;
4311 -       u32 sr;
4312 -       int err = 0;
4313 -
4314 -       /*
4315 -        * Apply CRC over SROM content regardless SROM is present or not.
4316 -        */
4317 -       srom = kmalloc(SROM_MAX, GFP_ATOMIC);
4318 -       if (!srom)
4319 -               return -ENOMEM;
4320 -
4321 -       crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
4322 -       if (ai_is_sprom_available(sih)) {
4323 -               err = sprom_read_pci(sih, srom, SROM4_WORDS, true);
4324 -
4325 -               if (err == 0)
4326 -                       /* srom read and passed crc */
4327 -                       /* top word of sprom contains version and crc8 */
4328 -                       sromrev = srom[SROM4_CRCREV] & 0xff;
4329 -       } else {
4330 -               /* Use OTP if SPROM not available */
4331 -               err = otp_read_pci(sih, srom, SROM4_WORDS);
4332 -               if (err == 0)
4333 -                       /* OTP only contain SROM rev8/rev9 for now */
4334 -                       sromrev = srom[SROM4_CRCREV] & 0xff;
4335 -       }
4336 -
4337 -       if (!err) {
4338 -               struct si_info *sii = (struct si_info *)sih;
4339 -
4340 -               /* Bitmask for the sromrev */
4341 -               sr = 1 << sromrev;
4342 -
4343 -               /*
4344 -                * srom version check: Current valid versions: 8, 9
4345 -                */
4346 -               if ((sr & 0x300) == 0) {
4347 -                       err = -EINVAL;
4348 -                       goto errout;
4349 -               }
4350 -
4351 -               INIT_LIST_HEAD(&sii->var_list);
4352 -
4353 -               /* parse SROM into name=value pairs. */
4354 -               err = _initvars_srom_pci(sromrev, srom, &sii->var_list);
4355 -               if (err)
4356 -                       srom_free_vars(sih);
4357 -       }
4358 -
4359 -errout:
4360 -       kfree(srom);
4361 -       return err;
4362 -}
4363 -
4364 -void srom_free_vars(struct si_pub *sih)
4365 -{
4366 -       struct si_info *sii;
4367 -       struct brcms_srom_list_head *entry, *next;
4368 -
4369 -       sii = (struct si_info *)sih;
4370 -       list_for_each_entry_safe(entry, next, &sii->var_list, var_list) {
4371 -               list_del(&entry->var_list);
4372 -               kfree(entry);
4373 -       }
4374 -}
4375 -
4376 -/*
4377 - * Search the name=value vars for a specific one and return its value.
4378 - * Returns NULL if not found.
4379 - */
4380 -char *getvar(struct si_pub *sih, enum brcms_srom_id id)
4381 -{
4382 -       struct si_info *sii;
4383 -       struct brcms_srom_list_head *entry;
4384 -
4385 -       sii = (struct si_info *)sih;
4386 -
4387 -       list_for_each_entry(entry, &sii->var_list, var_list)
4388 -               if (entry->varid == id)
4389 -                       return &entry->buf[0];
4390 -
4391 -       /* nothing found */
4392 -       return NULL;
4393 -}
4394 -
4395 -/*
4396 - * Search the vars for a specific one and return its value as
4397 - * an integer. Returns 0 if not found.-
4398 - */
4399 -int getintvar(struct si_pub *sih, enum brcms_srom_id id)
4400 -{
4401 -       struct si_info *sii;
4402 -       struct brcms_srom_list_head *entry;
4403 -       unsigned long res;
4404 -
4405 -       sii = (struct si_info *)sih;
4406 -
4407 -       list_for_each_entry(entry, &sii->var_list, var_list)
4408 -               if (entry->varid == id) {
4409 -                       if (entry->var_type == BRCMS_SROM_SNUMBER ||
4410 -                           entry->var_type == BRCMS_SROM_UNUMBER)
4411 -                               return (int)entry->sval;
4412 -                       else if (!kstrtoul(&entry->buf[0], 0, &res))
4413 -                               return (int)res;
4414 -               }
4415 -
4416 -       return 0;
4417 -}
4418 --- a/drivers/net/wireless/brcm80211/brcmsmac/srom.h
4419 +++ /dev/null
4420 @@ -1,29 +0,0 @@
4421 -/*
4422 - * Copyright (c) 2010 Broadcom Corporation
4423 - *
4424 - * Permission to use, copy, modify, and/or distribute this software for any
4425 - * purpose with or without fee is hereby granted, provided that the above
4426 - * copyright notice and this permission notice appear in all copies.
4427 - *
4428 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4429 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4430 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
4431 - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4432 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
4433 - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
4434 - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4435 - */
4436 -
4437 -#ifndef        _BRCM_SROM_H_
4438 -#define        _BRCM_SROM_H_
4439 -
4440 -#include "types.h"
4441 -
4442 -/* Prototypes */
4443 -extern int srom_var_init(struct si_pub *sih);
4444 -extern void srom_free_vars(struct si_pub *sih);
4445 -
4446 -extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
4447 -                    uint byteoff, uint nbytes, u16 *buf, bool check_crc);
4448 -
4449 -#endif                         /* _BRCM_SROM_H_ */
4450 --- a/drivers/net/wireless/brcm80211/brcmsmac/stf.c
4451 +++ b/drivers/net/wireless/brcm80211/brcmsmac/stf.c
4452 @@ -370,9 +370,11 @@ void brcms_c_stf_phy_txant_upd(struct br
4453
4454  void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc)
4455  {
4456 +       struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4457 +
4458         /* get available rx/tx chains */
4459 -       wlc->stf->hw_txchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_TXCHAIN);
4460 -       wlc->stf->hw_rxchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_RXCHAIN);
4461 +       wlc->stf->hw_txchain = sprom->txchain;
4462 +       wlc->stf->hw_rxchain = sprom->rxchain;
4463
4464         /* these parameter are intended to be used for all PHY types */
4465         if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) {