package/mac80211/patches/820-b43-backport.patch

   1 --- a/drivers/net/wireless/b43/Kconfig
   2 +++ b/drivers/net/wireless/b43/Kconfig
   3 @@ -90,6 +90,12 @@ config B43_SDIO
   4
   5  #Data transfers to the device via PIO. We want it as a fallback even
   6  # if we can do DMA.
   7 +config B43_BCMA_PIO
   8 +       bool
   9 +       depends on B43_BCMA
  10 +       select BCMA_BLOCKIO
  11 +       default y
  12 +
  13  config B43_PIO
  14         bool
  15         depends on B43
  16 @@ -125,6 +131,14 @@ config B43_PHY_HT
  17
  18           Say N, this is BROKEN and crashes driver.
  19
  20 +config B43_PHY_LCN
  21 +       bool "Support for LCN-PHY devices (BROKEN)"
  22 +       depends on B43 && BROKEN
  23 +       ---help---
  24 +         Support for the LCN-PHY.
  25 +
  26 +         Say N, this is BROKEN and crashes driver.
  27 +
  28  # This config option automatically enables b43 LEDS support,
  29  # if it's possible.
  30  config B43_LEDS
  31 --- a/drivers/net/wireless/b43/Makefile
  32 +++ b/drivers/net/wireless/b43/Makefile
  33 @@ -11,7 +11,9 @@ b43-$(CONFIG_B43_PHY_N)               += phy_n.o
  34  b43-$(CONFIG_B43_PHY_LP)       += phy_lp.o
  35  b43-$(CONFIG_B43_PHY_LP)       += tables_lpphy.o
  36  b43-$(CONFIG_B43_PHY_HT)       += phy_ht.o
  37 +b43-$(CONFIG_B43_PHY_HT)       += tables_phy_ht.o
  38  b43-$(CONFIG_B43_PHY_HT)       += radio_2059.o
  39 +b43-$(CONFIG_B43_PHY_LCN)      += phy_lcn.o tables_phy_lcn.o
  40  b43-y                          += sysfs.o
  41  b43-y                          += xmit.o
  42  b43-y                          += lo.o
  43 --- a/drivers/net/wireless/b43/b43.h
  44 +++ b/drivers/net/wireless/b43/b43.h
  45 @@ -433,6 +433,12 @@ enum {
  46  #define  B43_BCMA_IOCTL_PHY_BW_40MHZ   0x00000080      /* 40 MHz bandwidth, 160 MHz PHY */
  47  #define B43_BCMA_IOCTL_GMODE           0x00002000      /* G Mode Enable */
  48
  49 +/* BCMA 802.11 core specific IO status (BCMA_IOST) flags */
  50 +#define B43_BCMA_IOST_2G_PHY           0x00000001      /* 2.4G capable phy */
  51 +#define B43_BCMA_IOST_5G_PHY           0x00000002      /* 5G capable phy */
  52 +#define B43_BCMA_IOST_FASTCLKA         0x00000004      /* Fast Clock Available */
  53 +#define B43_BCMA_IOST_DUALB_PHY                0x00000008      /* Dualband phy */
  54 +
  55  /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
  56  #define B43_TMSLOW_GMODE               0x20000000      /* G Mode Enable */
  57  #define B43_TMSLOW_PHY_BANDWIDTH       0x00C00000      /* PHY band width and clock speed mask (N-PHY only) */
  58 @@ -588,6 +594,7 @@ struct b43_dma {
  59         struct b43_dmaring *rx_ring;
  60
  61         u32 translation; /* Routing bits */
  62 +       bool parity; /* Check for parity */
  63  };
  64
  65  struct b43_pio_txqueue;
  66 @@ -726,7 +733,6 @@ enum {
  67
  68  /* Data structure for one wireless device (802.11 core) */
  69  struct b43_wldev {
  70 -       struct ssb_device *sdev; /* TODO: remove when b43_bus_dev is ready */
  71         struct b43_bus_dev *dev;
  72         struct b43_wl *wl;
  73
  74 --- a/drivers/net/wireless/b43/bus.c
  75 +++ b/drivers/net/wireless/b43/bus.c
  76 @@ -23,58 +23,155 @@
  77  #include "b43.h"
  78  #include "bus.h"
  79
  80 +/* BCMA */
  81 +#ifdef CONFIG_B43_BCMA
  82 +static int b43_bus_bcma_bus_may_powerdown(struct b43_bus_dev *dev)
  83 +{
  84 +       return 0; /* bcma_bus_may_powerdown(dev->bdev->bus); */
  85 +}
  86 +static int b43_bus_bcma_bus_powerup(struct b43_bus_dev *dev,
  87 +                                         bool dynamic_pctl)
  88 +{
  89 +       return 0; /* bcma_bus_powerup(dev->sdev->bus, dynamic_pctl); */
  90 +}
  91 +static int b43_bus_bcma_device_is_enabled(struct b43_bus_dev *dev)
  92 +{
  93 +       return bcma_core_is_enabled(dev->bdev);
  94 +}
  95 +static void b43_bus_bcma_device_enable(struct b43_bus_dev *dev,
  96 +                                            u32 core_specific_flags)
  97 +{
  98 +       bcma_core_enable(dev->bdev, core_specific_flags);
  99 +}
 100 +static void b43_bus_bcma_device_disable(struct b43_bus_dev *dev,
 101 +                                             u32 core_specific_flags)
 102 +{
 103 +       bcma_core_disable(dev->bdev, core_specific_flags);
 104 +}
 105 +static u16 b43_bus_bcma_read16(struct b43_bus_dev *dev, u16 offset)
 106 +{
 107 +       return bcma_read16(dev->bdev, offset);
 108 +}
 109 +static u32 b43_bus_bcma_read32(struct b43_bus_dev *dev, u16 offset)
 110 +{
 111 +       return bcma_read32(dev->bdev, offset);
 112 +}
 113 +static
 114 +void b43_bus_bcma_write16(struct b43_bus_dev *dev, u16 offset, u16 value)
 115 +{
 116 +       bcma_write16(dev->bdev, offset, value);
 117 +}
 118 +static
 119 +void b43_bus_bcma_write32(struct b43_bus_dev *dev, u16 offset, u32 value)
 120 +{
 121 +       bcma_write32(dev->bdev, offset, value);
 122 +}
 123 +static
 124 +void b43_bus_bcma_block_read(struct b43_bus_dev *dev, void *buffer,
 125 +                            size_t count, u16 offset, u8 reg_width)
 126 +{
 127 +       bcma_block_read(dev->bdev, buffer, count, offset, reg_width);
 128 +}
 129 +static
 130 +void b43_bus_bcma_block_write(struct b43_bus_dev *dev, const void *buffer,
 131 +                             size_t count, u16 offset, u8 reg_width)
 132 +{
 133 +       bcma_block_write(dev->bdev, buffer, count, offset, reg_width);
 134 +}
 135 +
 136 +struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core)
 137 +{
 138 +       struct b43_bus_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 139 +       if (!dev)
 140 +               return NULL;
 141 +
 142 +       dev->bus_type = B43_BUS_BCMA;
 143 +       dev->bdev = core;
 144 +
 145 +       dev->bus_may_powerdown = b43_bus_bcma_bus_may_powerdown;
 146 +       dev->bus_powerup = b43_bus_bcma_bus_powerup;
 147 +       dev->device_is_enabled = b43_bus_bcma_device_is_enabled;
 148 +       dev->device_enable = b43_bus_bcma_device_enable;
 149 +       dev->device_disable = b43_bus_bcma_device_disable;
 150 +
 151 +       dev->read16 = b43_bus_bcma_read16;
 152 +       dev->read32 = b43_bus_bcma_read32;
 153 +       dev->write16 = b43_bus_bcma_write16;
 154 +       dev->write32 = b43_bus_bcma_write32;
 155 +       dev->block_read = b43_bus_bcma_block_read;
 156 +       dev->block_write = b43_bus_bcma_block_write;
 157 +
 158 +       dev->dev = &core->dev;
 159 +       dev->dma_dev = core->dma_dev;
 160 +       dev->irq = core->irq;
 161 +
 162 +       /*
 163 +       dev->board_vendor = core->bus->boardinfo.vendor;
 164 +       dev->board_type = core->bus->boardinfo.type;
 165 +       dev->board_rev = core->bus->boardinfo.rev;
 166 +       */
 167 +
 168 +       dev->chip_id = core->bus->chipinfo.id;
 169 +       dev->chip_rev = core->bus->chipinfo.rev;
 170 +       dev->chip_pkg = core->bus->chipinfo.pkg;
 171 +
 172 +       dev->bus_sprom = &core->bus->sprom;
 173 +
 174 +       dev->core_id = core->id.id;
 175 +       dev->core_rev = core->id.rev;
 176 +
 177 +       return dev;
 178 +}
 179 +#endif /* CONFIG_B43_BCMA */
 180
 181  /* SSB */
 182  #ifdef CONFIG_B43_SSB
 183 -static inline int b43_bus_ssb_bus_may_powerdown(struct b43_bus_dev *dev)
 184 +static int b43_bus_ssb_bus_may_powerdown(struct b43_bus_dev *dev)
 185  {
 186         return ssb_bus_may_powerdown(dev->sdev->bus);
 187  }
 188 -static inline int b43_bus_ssb_bus_powerup(struct b43_bus_dev *dev,
 189 +static int b43_bus_ssb_bus_powerup(struct b43_bus_dev *dev,
 190                                           bool dynamic_pctl)
 191  {
 192         return ssb_bus_powerup(dev->sdev->bus, dynamic_pctl);
 193  }
 194 -static inline int b43_bus_ssb_device_is_enabled(struct b43_bus_dev *dev)
 195 +static int b43_bus_ssb_device_is_enabled(struct b43_bus_dev *dev)
 196  {
 197         return ssb_device_is_enabled(dev->sdev);
 198  }
 199 -static inline void b43_bus_ssb_device_enable(struct b43_bus_dev *dev,
 200 +static void b43_bus_ssb_device_enable(struct b43_bus_dev *dev,
 201                                              u32 core_specific_flags)
 202  {
 203         ssb_device_enable(dev->sdev, core_specific_flags);
 204  }
 205 -static inline void b43_bus_ssb_device_disable(struct b43_bus_dev *dev,
 206 +static void b43_bus_ssb_device_disable(struct b43_bus_dev *dev,
 207                                               u32 core_specific_flags)
 208  {
 209         ssb_device_disable(dev->sdev, core_specific_flags);
 210  }
 211
 212 -static inline u16 b43_bus_ssb_read16(struct b43_bus_dev *dev, u16 offset)
 213 +static u16 b43_bus_ssb_read16(struct b43_bus_dev *dev, u16 offset)
 214  {
 215         return ssb_read16(dev->sdev, offset);
 216  }
 217 -static inline u32 b43_bus_ssb_read32(struct b43_bus_dev *dev, u16 offset)
 218 +static u32 b43_bus_ssb_read32(struct b43_bus_dev *dev, u16 offset)
 219  {
 220         return ssb_read32(dev->sdev, offset);
 221  }
 222 -static inline
 223 -void b43_bus_ssb_write16(struct b43_bus_dev *dev, u16 offset, u16 value)
 224 +static void b43_bus_ssb_write16(struct b43_bus_dev *dev, u16 offset, u16 value)
 225  {
 226         ssb_write16(dev->sdev, offset, value);
 227  }
 228 -static inline
 229 -void b43_bus_ssb_write32(struct b43_bus_dev *dev, u16 offset, u32 value)
 230 +static void b43_bus_ssb_write32(struct b43_bus_dev *dev, u16 offset, u32 value)
 231  {
 232         ssb_write32(dev->sdev, offset, value);
 233  }
 234 -static inline
 235 -void b43_bus_ssb_block_read(struct b43_bus_dev *dev, void *buffer,
 236 -                           size_t count, u16 offset, u8 reg_width)
 237 +static void b43_bus_ssb_block_read(struct b43_bus_dev *dev, void *buffer,
 238 +                                  size_t count, u16 offset, u8 reg_width)
 239  {
 240         ssb_block_read(dev->sdev, buffer, count, offset, reg_width);
 241  }
 242 -static inline
 243 +static
 244  void b43_bus_ssb_block_write(struct b43_bus_dev *dev, const void *buffer,
 245                              size_t count, u16 offset, u8 reg_width)
 246  {
 247 @@ -125,3 +222,32 @@ struct b43_bus_dev *b43_bus_dev_ssb_init
 248         return dev;
 249  }
 250  #endif /* CONFIG_B43_SSB */
 251 +
 252 +void *b43_bus_get_wldev(struct b43_bus_dev *dev)
 253 +{
 254 +       switch (dev->bus_type) {
 255 +#ifdef CONFIG_B43_BCMA
 256 +       case B43_BUS_BCMA:
 257 +               return bcma_get_drvdata(dev->bdev);
 258 +#endif
 259 +#ifdef CONFIG_B43_SSB
 260 +       case B43_BUS_SSB:
 261 +               return ssb_get_drvdata(dev->sdev);
 262 +#endif
 263 +       }
 264 +       return NULL;
 265 +}
 266 +
 267 +void b43_bus_set_wldev(struct b43_bus_dev *dev, void *wldev)
 268 +{
 269 +       switch (dev->bus_type) {
 270 +#ifdef CONFIG_B43_BCMA
 271 +       case B43_BUS_BCMA:
 272 +               bcma_set_drvdata(dev->bdev, wldev);
 273 +#endif
 274 +#ifdef CONFIG_B43_SSB
 275 +       case B43_BUS_SSB:
 276 +               ssb_set_drvdata(dev->sdev, wldev);
 277 +#endif
 278 +       }
 279 +}
 280 --- a/drivers/net/wireless/b43/bus.h
 281 +++ b/drivers/net/wireless/b43/bus.h
 282 @@ -2,12 +2,16 @@
 283  #define B43_BUS_H_
 284
 285  enum b43_bus_type {
 286 +#ifdef CONFIG_B43_BCMA
 287 +       B43_BUS_BCMA,
 288 +#endif
 289         B43_BUS_SSB,
 290  };
 291
 292  struct b43_bus_dev {
 293         enum b43_bus_type bus_type;
 294         union {
 295 +               struct bcma_device *bdev;
 296                 struct ssb_device *sdev;
 297         };
 298
 299 @@ -57,6 +61,10 @@ static inline bool b43_bus_host_is_sdio(
 300                 dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO);
 301  }
 302
 303 +struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core);
 304  struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev);
 305
 306 +void *b43_bus_get_wldev(struct b43_bus_dev *dev);
 307 +void b43_bus_set_wldev(struct b43_bus_dev *dev, void *data);
 308 +
 309  #endif /* B43_BUS_H_ */
 310 --- a/drivers/net/wireless/b43/dma.c
 311 +++ b/drivers/net/wireless/b43/dma.c
 312 @@ -174,7 +174,7 @@ static void op64_fill_descriptor(struct
 313         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 314         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 315             >> SSB_DMA_TRANSLATION_SHIFT;
 316 -       addrhi |= (ring->dev->dma.translation << 1);
 317 +       addrhi |= ring->dev->dma.translation;
 318         if (slot == ring->nr_slots - 1)
 319                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 320         if (start)
 321 @@ -659,6 +659,7 @@ static int dmacontroller_setup(struct b4
 322         u32 value;
 323         u32 addrext;
 324         u32 trans = ring->dev->dma.translation;
 325 +       bool parity = ring->dev->dma.parity;
 326
 327         if (ring->tx) {
 328                 if (ring->type == B43_DMA_64BIT) {
 329 @@ -669,13 +670,15 @@ static int dmacontroller_setup(struct b4
 330                         value = B43_DMA64_TXENABLE;
 331                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 332                             & B43_DMA64_TXADDREXT_MASK;
 333 +                       if (!parity)
 334 +                               value |= B43_DMA64_TXPARITYDISABLE;
 335                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 336                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
 337                                       (ringbase & 0xFFFFFFFF));
 338                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
 339                                       ((ringbase >> 32) &
 340                                        ~SSB_DMA_TRANSLATION_MASK)
 341 -                                     | (trans << 1));
 342 +                                     | trans);
 343                 } else {
 344                         u32 ringbase = (u32) (ring->dmabase);
 345
 346 @@ -684,6 +687,8 @@ static int dmacontroller_setup(struct b4
 347                         value = B43_DMA32_TXENABLE;
 348                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 349                             & B43_DMA32_TXADDREXT_MASK;
 350 +                       if (!parity)
 351 +                               value |= B43_DMA32_TXPARITYDISABLE;
 352                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 353                         b43_dma_write(ring, B43_DMA32_TXRING,
 354                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 355 @@ -702,13 +707,15 @@ static int dmacontroller_setup(struct b4
 356                         value |= B43_DMA64_RXENABLE;
 357                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 358                             & B43_DMA64_RXADDREXT_MASK;
 359 +                       if (!parity)
 360 +                               value |= B43_DMA64_RXPARITYDISABLE;
 361                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 362                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
 363                                       (ringbase & 0xFFFFFFFF));
 364                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
 365                                       ((ringbase >> 32) &
 366                                        ~SSB_DMA_TRANSLATION_MASK)
 367 -                                     | (trans << 1));
 368 +                                     | trans);
 369                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 370                                       sizeof(struct b43_dmadesc64));
 371                 } else {
 372 @@ -720,6 +727,8 @@ static int dmacontroller_setup(struct b4
 373                         value |= B43_DMA32_RXENABLE;
 374                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 375                             & B43_DMA32_RXADDREXT_MASK;
 376 +                       if (!parity)
 377 +                               value |= B43_DMA32_RXPARITYDISABLE;
 378                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 379                         b43_dma_write(ring, B43_DMA32_RXRING,
 380                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 381 @@ -1055,7 +1064,26 @@ int b43_dma_init(struct b43_wldev *dev)
 382         err = b43_dma_set_mask(dev, dmamask);
 383         if (err)
 384                 return err;
 385 -       dma->translation = ssb_dma_translation(dev->sdev);
 386 +
 387 +       switch (dev->dev->bus_type) {
 388 +#ifdef CONFIG_B43_BCMA
 389 +       case B43_BUS_BCMA:
 390 +               dma->translation = bcma_core_dma_translation(dev->dev->bdev);
 391 +               break;
 392 +#endif
 393 +#ifdef CONFIG_B43_SSB
 394 +       case B43_BUS_SSB:
 395 +               dma->translation = ssb_dma_translation(dev->dev->sdev);
 396 +               break;
 397 +#endif
 398 +       }
 399 +
 400 +       dma->parity = true;
 401 +#ifdef CONFIG_B43_BCMA
 402 +       /* TODO: find out which SSB devices need disabling parity */
 403 +       if (dev->dev->bus_type == B43_BUS_BCMA)
 404 +               dma->parity = false;
 405 +#endif
 406
 407         err = -ENOMEM;
 408         /* setup TX DMA channels. */
 409 @@ -1600,6 +1628,7 @@ void b43_dma_rx(struct b43_dmaring *ring
 410                 dma_rx(ring, &slot);
 411                 update_max_used_slots(ring, ++used_slots);
 412         }
 413 +       wmb();
 414         ops->set_current_rxslot(ring, slot);
 415         ring->current_slot = slot;
 416  }
 417 --- a/drivers/net/wireless/b43/dma.h
 418 +++ b/drivers/net/wireless/b43/dma.h
 419 @@ -20,6 +20,7 @@
 420  #define                B43_DMA32_TXSUSPEND                     0x00000002
 421  #define                B43_DMA32_TXLOOPBACK            0x00000004
 422  #define                B43_DMA32_TXFLUSH                       0x00000010
 423 +#define                B43_DMA32_TXPARITYDISABLE               0x00000800
 424  #define                B43_DMA32_TXADDREXT_MASK                0x00030000
 425  #define                B43_DMA32_TXADDREXT_SHIFT               16
 426  #define B43_DMA32_TXRING                               0x04
 427 @@ -44,6 +45,7 @@
 428  #define                B43_DMA32_RXFROFF_MASK          0x000000FE
 429  #define                B43_DMA32_RXFROFF_SHIFT         1
 430  #define                B43_DMA32_RXDIRECTFIFO          0x00000100
 431 +#define                B43_DMA32_RXPARITYDISABLE               0x00000800
 432  #define                B43_DMA32_RXADDREXT_MASK                0x00030000
 433  #define                B43_DMA32_RXADDREXT_SHIFT               16
 434  #define B43_DMA32_RXRING                               0x14
 435 @@ -84,6 +86,7 @@ struct b43_dmadesc32 {
 436  #define                B43_DMA64_TXSUSPEND                     0x00000002
 437  #define                B43_DMA64_TXLOOPBACK            0x00000004
 438  #define                B43_DMA64_TXFLUSH                       0x00000010
 439 +#define                B43_DMA64_TXPARITYDISABLE               0x00000800
 440  #define                B43_DMA64_TXADDREXT_MASK                0x00030000
 441  #define                B43_DMA64_TXADDREXT_SHIFT               16
 442  #define B43_DMA64_TXINDEX                              0x04
 443 @@ -111,6 +114,7 @@ struct b43_dmadesc32 {
 444  #define                B43_DMA64_RXFROFF_MASK          0x000000FE
 445  #define                B43_DMA64_RXFROFF_SHIFT         1
 446  #define                B43_DMA64_RXDIRECTFIFO          0x00000100
 447 +#define                B43_DMA64_RXPARITYDISABLE               0x00000800
 448  #define                B43_DMA64_RXADDREXT_MASK                0x00030000
 449  #define                B43_DMA64_RXADDREXT_SHIFT               16
 450  #define B43_DMA64_RXINDEX                              0x24
 451 --- a/drivers/net/wireless/b43/main.c
 452 +++ b/drivers/net/wireless/b43/main.c
 453 @@ -1136,6 +1136,41 @@ void b43_power_saving_ctl_bits(struct b4
 454         }
 455  }
 456
 457 +#ifdef CONFIG_B43_BCMA
 458 +static void b43_bcma_phy_reset(struct b43_wldev *dev)
 459 +{
 460 +       u32 flags;
 461 +
 462 +       /* Put PHY into reset */
 463 +       flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 464 +       flags |= B43_BCMA_IOCTL_PHY_RESET;
 465 +       flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
 466 +       bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
 467 +       udelay(2);
 468 +
 469 +       /* Take PHY out of reset */
 470 +       flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 471 +       flags &= ~B43_BCMA_IOCTL_PHY_RESET;
 472 +       flags |= BCMA_IOCTL_FGC;
 473 +       bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
 474 +       udelay(1);
 475 +
 476 +       /* Do not force clock anymore */
 477 +       flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 478 +       flags &= ~BCMA_IOCTL_FGC;
 479 +       bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
 480 +       udelay(1);
 481 +}
 482 +
 483 +static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
 484 +{
 485 +       b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
 486 +       bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
 487 +       b43_bcma_phy_reset(dev);
 488 +       bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
 489 +}
 490 +#endif
 491 +
 492  static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
 493  {
 494         struct ssb_device *sdev = dev->dev->sdev;
 495 @@ -1168,7 +1203,18 @@ void b43_wireless_core_reset(struct b43_
 496  {
 497         u32 macctl;
 498
 499 -       b43_ssb_wireless_core_reset(dev, gmode);
 500 +       switch (dev->dev->bus_type) {
 501 +#ifdef CONFIG_B43_BCMA
 502 +       case B43_BUS_BCMA:
 503 +               b43_bcma_wireless_core_reset(dev, gmode);
 504 +               break;
 505 +#endif
 506 +#ifdef CONFIG_B43_SSB
 507 +       case B43_BUS_SSB:
 508 +               b43_ssb_wireless_core_reset(dev, gmode);
 509 +               break;
 510 +#endif
 511 +       }
 512
 513         /* Turn Analog ON, but only if we already know the PHY-type.
 514          * This protects against very early setup where we don't know the
 515 @@ -1921,7 +1967,7 @@ static irqreturn_t b43_do_interrupt(stru
 516                 return IRQ_NONE;
 517         reason &= dev->irq_mask;
 518         if (!reason)
 519 -               return IRQ_HANDLED;
 520 +               return IRQ_NONE;
 521
 522         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
 523             & 0x0001DC00;
 524 @@ -2116,21 +2162,43 @@ static int b43_try_request_fw(struct b43
 525         u32 tmshigh;
 526         int err;
 527
 528 +       /* Files for HT and LCN were found by trying one by one */
 529 +
 530         /* Get microcode */
 531 -       if ((rev >= 5) && (rev <= 10))
 532 +       if ((rev >= 5) && (rev <= 10)) {
 533                 filename = "ucode5";
 534 -       else if ((rev >= 11) && (rev <= 12))
 535 +       } else if ((rev >= 11) && (rev <= 12)) {
 536                 filename = "ucode11";
 537 -       else if (rev == 13)
 538 +       } else if (rev == 13) {
 539                 filename = "ucode13";
 540 -       else if (rev == 14)
 541 +       } else if (rev == 14) {
 542                 filename = "ucode14";
 543 -       else if (rev == 15)
 544 +       } else if (rev == 15) {
 545                 filename = "ucode15";
 546 -       else if ((rev >= 16) && (rev <= 20))
 547 -               filename = "ucode16_mimo";
 548 -       else
 549 -               goto err_no_ucode;
 550 +       } else {
 551 +               switch (dev->phy.type) {
 552 +               case B43_PHYTYPE_N:
 553 +                       if (rev >= 16)
 554 +                               filename = "ucode16_mimo";
 555 +                       else
 556 +                               goto err_no_ucode;
 557 +                       break;
 558 +               case B43_PHYTYPE_HT:
 559 +                       if (rev == 29)
 560 +                               filename = "ucode29_mimo";
 561 +                       else
 562 +                               goto err_no_ucode;
 563 +                       break;
 564 +               case B43_PHYTYPE_LCN:
 565 +                       if (rev == 24)
 566 +                               filename = "ucode24_mimo";
 567 +                       else
 568 +                               goto err_no_ucode;
 569 +                       break;
 570 +               default:
 571 +                       goto err_no_ucode;
 572 +               }
 573 +       }
 574         err = b43_do_request_fw(ctx, filename, &fw->ucode);
 575         if (err)
 576                 goto err_load;
 577 @@ -2189,6 +2257,18 @@ static int b43_try_request_fw(struct b43
 578                 else
 579                         goto err_no_initvals;
 580                 break;
 581 +       case B43_PHYTYPE_HT:
 582 +               if (rev == 29)
 583 +                       filename = "ht0initvals29";
 584 +               else
 585 +                       goto err_no_initvals;
 586 +               break;
 587 +       case B43_PHYTYPE_LCN:
 588 +               if (rev == 24)
 589 +                       filename = "lcn0initvals24";
 590 +               else
 591 +                       goto err_no_initvals;
 592 +               break;
 593         default:
 594                 goto err_no_initvals;
 595         }
 596 @@ -2236,6 +2316,18 @@ static int b43_try_request_fw(struct b43
 597                 else
 598                         goto err_no_initvals;
 599                 break;
 600 +       case B43_PHYTYPE_HT:
 601 +               if (rev == 29)
 602 +                       filename = "ht0bsinitvals29";
 603 +               else
 604 +                       goto err_no_initvals;
 605 +               break;
 606 +       case B43_PHYTYPE_LCN:
 607 +               if (rev == 24)
 608 +                       filename = "lcn0bsinitvals24";
 609 +               else
 610 +                       goto err_no_initvals;
 611 +               break;
 612         default:
 613                 goto err_no_initvals;
 614         }
 615 @@ -2607,11 +2699,24 @@ static int b43_gpio_init(struct b43_wlde
 616         if (dev->dev->core_rev >= 2)
 617                 mask |= 0x0010; /* FIXME: This is redundant. */
 618
 619 -       gpiodev = b43_ssb_gpio_dev(dev);
 620 -       if (gpiodev)
 621 -               ssb_write32(gpiodev, B43_GPIO_CONTROL,
 622 -                           (ssb_read32(gpiodev, B43_GPIO_CONTROL)
 623 -                            & mask) | set);
 624 +       switch (dev->dev->bus_type) {
 625 +#ifdef CONFIG_B43_BCMA
 626 +       case B43_BUS_BCMA:
 627 +               bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
 628 +                               (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
 629 +                                       BCMA_CC_GPIOCTL) & mask) | set);
 630 +               break;
 631 +#endif
 632 +#ifdef CONFIG_B43_SSB
 633 +       case B43_BUS_SSB:
 634 +               gpiodev = b43_ssb_gpio_dev(dev);
 635 +               if (gpiodev)
 636 +                       ssb_write32(gpiodev, B43_GPIO_CONTROL,
 637 +                                   (ssb_read32(gpiodev, B43_GPIO_CONTROL)
 638 +                                   & mask) | set);
 639 +               break;
 640 +#endif
 641 +       }
 642
 643         return 0;
 644  }
 645 @@ -2621,9 +2726,21 @@ static void b43_gpio_cleanup(struct b43_
 646  {
 647         struct ssb_device *gpiodev;
 648
 649 -       gpiodev = b43_ssb_gpio_dev(dev);
 650 -       if (gpiodev)
 651 -               ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
 652 +       switch (dev->dev->bus_type) {
 653 +#ifdef CONFIG_B43_BCMA
 654 +       case B43_BUS_BCMA:
 655 +               bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
 656 +                               0);
 657 +               break;
 658 +#endif
 659 +#ifdef CONFIG_B43_SSB
 660 +       case B43_BUS_SSB:
 661 +               gpiodev = b43_ssb_gpio_dev(dev);
 662 +               if (gpiodev)
 663 +                       ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
 664 +               break;
 665 +#endif
 666 +       }
 667  }
 668
 669  /* http://bcm-specs.sipsolutions.net/EnableMac */
 670 @@ -2695,12 +2812,30 @@ out:
 671  /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
 672  void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
 673  {
 674 -       u32 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
 675 -       if (on)
 676 -               tmslow |= B43_TMSLOW_MACPHYCLKEN;
 677 -       else
 678 -               tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
 679 -       ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
 680 +       u32 tmp;
 681 +
 682 +       switch (dev->dev->bus_type) {
 683 +#ifdef CONFIG_B43_BCMA
 684 +       case B43_BUS_BCMA:
 685 +               tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 686 +               if (on)
 687 +                       tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
 688 +               else
 689 +                       tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
 690 +               bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 691 +               break;
 692 +#endif
 693 +#ifdef CONFIG_B43_SSB
 694 +       case B43_BUS_SSB:
 695 +               tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 696 +               if (on)
 697 +                       tmp |= B43_TMSLOW_MACPHYCLKEN;
 698 +               else
 699 +                       tmp &= ~B43_TMSLOW_MACPHYCLKEN;
 700 +               ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 701 +               break;
 702 +#endif
 703 +       }
 704  }
 705
 706  static void b43_adjust_opmode(struct b43_wldev *dev)
 707 @@ -2939,8 +3074,20 @@ static int b43_chip_init(struct b43_wlde
 708
 709         b43_mac_phy_clock_set(dev, true);
 710
 711 -       b43_write16(dev, B43_MMIO_POWERUP_DELAY,
 712 -                   dev->sdev->bus->chipco.fast_pwrup_delay);
 713 +       switch (dev->dev->bus_type) {
 714 +#ifdef CONFIG_B43_BCMA
 715 +       case B43_BUS_BCMA:
 716 +               /* FIXME: 0xE74 is quite common, but should be read from CC */
 717 +               b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
 718 +               break;
 719 +#endif
 720 +#ifdef CONFIG_B43_SSB
 721 +       case B43_BUS_SSB:
 722 +               b43_write16(dev, B43_MMIO_POWERUP_DELAY,
 723 +                           dev->dev->sdev->bus->chipco.fast_pwrup_delay);
 724 +               break;
 725 +#endif
 726 +       }
 727
 728         err = 0;
 729         b43dbg(dev->wl, "Chip initialized\n");
 730 @@ -3456,21 +3603,33 @@ static void b43_op_set_tsf(struct ieee80
 731
 732  static void b43_put_phy_into_reset(struct b43_wldev *dev)
 733  {
 734 -       struct ssb_device *sdev = dev->sdev;
 735 -       u32 tmslow;
 736 +       u32 tmp;
 737
 738 -       tmslow = ssb_read32(sdev, SSB_TMSLOW);
 739 -       tmslow &= ~B43_TMSLOW_GMODE;
 740 -       tmslow |= B43_TMSLOW_PHYRESET;
 741 -       tmslow |= SSB_TMSLOW_FGC;
 742 -       ssb_write32(sdev, SSB_TMSLOW, tmslow);
 743 -       msleep(1);
 744 +       switch (dev->dev->bus_type) {
 745 +#ifdef CONFIG_B43_BCMA
 746 +       case B43_BUS_BCMA:
 747 +               b43err(dev->wl,
 748 +                      "Putting PHY into reset not supported on BCMA\n");
 749 +               break;
 750 +#endif
 751 +#ifdef CONFIG_B43_SSB
 752 +       case B43_BUS_SSB:
 753 +               tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 754 +               tmp &= ~B43_TMSLOW_GMODE;
 755 +               tmp |= B43_TMSLOW_PHYRESET;
 756 +               tmp |= SSB_TMSLOW_FGC;
 757 +               ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 758 +               msleep(1);
 759 +
 760 +               tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 761 +               tmp &= ~SSB_TMSLOW_FGC;
 762 +               tmp |= B43_TMSLOW_PHYRESET;
 763 +               ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 764 +               msleep(1);
 765
 766 -       tmslow = ssb_read32(sdev, SSB_TMSLOW);
 767 -       tmslow &= ~SSB_TMSLOW_FGC;
 768 -       tmslow |= B43_TMSLOW_PHYRESET;
 769 -       ssb_write32(sdev, SSB_TMSLOW, tmslow);
 770 -       msleep(1);
 771 +               break;
 772 +#endif
 773 +       }
 774  }
 775
 776  static const char *band_to_string(enum ieee80211_band band)
 777 @@ -4100,6 +4259,12 @@ static int b43_phy_versioning(struct b43
 778                         unsupported = 1;
 779                 break;
 780  #endif
 781 +#ifdef CONFIG_B43_PHY_LCN
 782 +       case B43_PHYTYPE_LCN:
 783 +               if (phy_rev > 1)
 784 +                       unsupported = 1;
 785 +               break;
 786 +#endif
 787         default:
 788                 unsupported = 1;
 789         };
 790 @@ -4113,22 +4278,42 @@ static int b43_phy_versioning(struct b43
 791                analog_type, phy_type, phy_rev);
 792
 793         /* Get RADIO versioning */
 794 -       if (dev->dev->chip_id == 0x4317) {
 795 -               if (dev->dev->chip_rev == 0)
 796 -                       tmp = 0x3205017F;
 797 -               else if (dev->dev->chip_rev == 1)
 798 -                       tmp = 0x4205017F;
 799 -               else
 800 -                       tmp = 0x5205017F;
 801 +       if (dev->dev->core_rev >= 24) {
 802 +               u16 radio24[3];
 803 +
 804 +               for (tmp = 0; tmp < 3; tmp++) {
 805 +                       b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
 806 +                       radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
 807 +               }
 808 +
 809 +               /* Broadcom uses "id" for our "ver" and has separated "ver" */
 810 +               /* radio_ver = (radio24[0] & 0xF0) >> 4; */
 811 +
 812 +               radio_manuf = 0x17F;
 813 +               radio_ver = (radio24[2] << 8) | radio24[1];
 814 +               radio_rev = (radio24[0] & 0xF);
 815         } else {
 816 -               b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
 817 -               tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 818 -               b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
 819 -               tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
 820 -       }
 821 -       radio_manuf = (tmp & 0x00000FFF);
 822 -       radio_ver = (tmp & 0x0FFFF000) >> 12;
 823 -       radio_rev = (tmp & 0xF0000000) >> 28;
 824 +               if (dev->dev->chip_id == 0x4317) {
 825 +                       if (dev->dev->chip_rev == 0)
 826 +                               tmp = 0x3205017F;
 827 +                       else if (dev->dev->chip_rev == 1)
 828 +                               tmp = 0x4205017F;
 829 +                       else
 830 +                               tmp = 0x5205017F;
 831 +               } else {
 832 +                       b43_write16(dev, B43_MMIO_RADIO_CONTROL,
 833 +                                   B43_RADIOCTL_ID);
 834 +                       tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 835 +                       b43_write16(dev, B43_MMIO_RADIO_CONTROL,
 836 +                                   B43_RADIOCTL_ID);
 837 +                       tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
 838 +                               << 16;
 839 +               }
 840 +               radio_manuf = (tmp & 0x00000FFF);
 841 +               radio_ver = (tmp & 0x0FFFF000) >> 12;
 842 +               radio_rev = (tmp & 0xF0000000) >> 28;
 843 +       }
 844 +
 845         if (radio_manuf != 0x17F /* Broadcom */)
 846                 unsupported = 1;
 847         switch (phy_type) {
 848 @@ -4160,6 +4345,10 @@ static int b43_phy_versioning(struct b43
 849                 if (radio_ver != 0x2059)
 850                         unsupported = 1;
 851                 break;
 852 +       case B43_PHYTYPE_LCN:
 853 +               if (radio_ver != 0x2064)
 854 +                       unsupported = 1;
 855 +               break;
 856         default:
 857                 B43_WARN_ON(1);
 858         }
 859 @@ -4343,7 +4532,6 @@ static void b43_wireless_core_exit(struc
 860  /* Initialize a wireless core */
 861  static int b43_wireless_core_init(struct b43_wldev *dev)
 862  {
 863 -       struct ssb_bus *bus = dev->sdev->bus;
 864         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 865         struct b43_phy *phy = &dev->phy;
 866         int err;
 867 @@ -4362,7 +4550,20 @@ static int b43_wireless_core_init(struct
 868         phy->ops->prepare_structs(dev);
 869
 870         /* Enable IRQ routing to this device. */
 871 -       ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->sdev);
 872 +       switch (dev->dev->bus_type) {
 873 +#ifdef CONFIG_B43_BCMA
 874 +       case B43_BUS_BCMA:
 875 +               bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
 876 +                                     dev->dev->bdev, true);
 877 +               break;
 878 +#endif
 879 +#ifdef CONFIG_B43_SSB
 880 +       case B43_BUS_SSB:
 881 +               ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
 882 +                                              dev->dev->sdev);
 883 +               break;
 884 +#endif
 885 +       }
 886
 887         b43_imcfglo_timeouts_workaround(dev);
 888         b43_bluetooth_coext_disable(dev);
 889 @@ -4393,8 +4594,9 @@ static int b43_wireless_core_init(struct
 890         if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
 891                 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
 892  #ifdef CONFIG_SSB_DRIVER_PCICORE
 893 -       if ((bus->bustype == SSB_BUSTYPE_PCI) &&
 894 -           (bus->pcicore.dev->id.revision <= 10))
 895 +       if (dev->dev->bus_type == B43_BUS_SSB &&
 896 +           dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
 897 +           dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
 898                 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
 899  #endif
 900         hf &= ~B43_HF_SKCFPUP;
 901 @@ -4764,9 +4966,9 @@ static void b43_wireless_core_detach(str
 902  static int b43_wireless_core_attach(struct b43_wldev *dev)
 903  {
 904         struct b43_wl *wl = dev->wl;
 905 -       struct ssb_bus *bus = dev->sdev->bus;
 906 -       struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
 907 +       struct pci_dev *pdev = NULL;
 908         int err;
 909 +       u32 tmp;
 910         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
 911
 912         /* Do NOT do any device initialization here.
 913 @@ -4776,20 +4978,38 @@ static int b43_wireless_core_attach(stru
 914          * that in core_init(), too.
 915          */
 916
 917 +#ifdef CONFIG_B43_SSB
 918 +       if (dev->dev->bus_type == B43_BUS_SSB &&
 919 +           dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
 920 +               pdev = dev->dev->sdev->bus->host_pci;
 921 +#endif
 922 +
 923         err = b43_bus_powerup(dev, 0);
 924         if (err) {
 925                 b43err(wl, "Bus powerup failed\n");
 926                 goto out;
 927         }
 928 -       /* Get the PHY type. */
 929 -       if (dev->dev->core_rev >= 5) {
 930 -               u32 tmshigh;
 931
 932 -               tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH);
 933 -               have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
 934 -               have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
 935 -       } else
 936 -               B43_WARN_ON(1);
 937 +       /* Get the PHY type. */
 938 +       switch (dev->dev->bus_type) {
 939 +#ifdef CONFIG_B43_BCMA
 940 +       case B43_BUS_BCMA:
 941 +               tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
 942 +               have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
 943 +               have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
 944 +               break;
 945 +#endif
 946 +#ifdef CONFIG_B43_SSB
 947 +       case B43_BUS_SSB:
 948 +               if (dev->dev->core_rev >= 5) {
 949 +                       tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
 950 +                       have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
 951 +                       have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
 952 +               } else
 953 +                       B43_WARN_ON(1);
 954 +               break;
 955 +#endif
 956 +       }
 957
 958         dev->phy.gmode = have_2ghz_phy;
 959         dev->phy.radio_on = 1;
 960 @@ -4815,6 +5035,8 @@ static int b43_wireless_core_attach(stru
 961  #endif
 962                 case B43_PHYTYPE_G:
 963                 case B43_PHYTYPE_N:
 964 +               case B43_PHYTYPE_HT:
 965 +               case B43_PHYTYPE_LCN:
 966                         have_2ghz_phy = 1;
 967                         break;
 968                 default:
 969 @@ -4877,13 +5099,13 @@ static void b43_one_core_detach(struct b
 970         /* Do not cancel ieee80211-workqueue based work here.
 971          * See comment in b43_remove(). */
 972
 973 -       wldev = ssb_get_drvdata(dev->sdev);
 974 +       wldev = b43_bus_get_wldev(dev);
 975         wl = wldev->wl;
 976         b43_debugfs_remove_device(wldev);
 977         b43_wireless_core_detach(wldev);
 978         list_del(&wldev->list);
 979         wl->nr_devs--;
 980 -       ssb_set_drvdata(dev->sdev, NULL);
 981 +       b43_bus_set_wldev(dev, NULL);
 982         kfree(wldev);
 983  }
 984
 985 @@ -4898,7 +5120,6 @@ static int b43_one_core_attach(struct b4
 986
 987         wldev->use_pio = b43_modparam_pio;
 988         wldev->dev = dev;
 989 -       wldev->sdev = dev->sdev; /* TODO: Remove when not needed */
 990         wldev->wl = wl;
 991         b43_set_status(wldev, B43_STAT_UNINIT);
 992         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
 993 @@ -4910,7 +5131,7 @@ static int b43_one_core_attach(struct b4
 994
 995         list_add(&wldev->list, &wl->devlist);
 996         wl->nr_devs++;
 997 -       ssb_set_drvdata(dev->sdev, wldev);
 998 +       b43_bus_set_wldev(dev, wldev);
 999         b43_debugfs_add_device(wldev);
1000
1001        out:
1002 @@ -4959,11 +5180,12 @@ static void b43_wireless_exit(struct b43
1003         ieee80211_free_hw(hw);
1004  }
1005
1006 -static struct b43_wl *b43_wireless_init(struct ssb_device *dev)
1007 +static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
1008  {
1009 -       struct ssb_sprom *sprom = &dev->bus->sprom;
1010 +       struct ssb_sprom *sprom = dev->bus_sprom;
1011         struct ieee80211_hw *hw;
1012         struct b43_wl *wl;
1013 +       char chip_name[6];
1014
1015         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
1016         if (!hw) {
1017 @@ -5002,21 +5224,70 @@ static struct b43_wl *b43_wireless_init(
1018         INIT_WORK(&wl->tx_work, b43_tx_work);
1019         skb_queue_head_init(&wl->tx_queue);
1020
1021 -       b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
1022 -               dev->bus->chip_id, dev->id.revision);
1023 +       snprintf(chip_name, ARRAY_SIZE(chip_name),
1024 +                (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
1025 +       b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
1026 +               dev->core_rev);
1027         return wl;
1028  }
1029
1030  #ifdef CONFIG_B43_BCMA
1031  static int b43_bcma_probe(struct bcma_device *core)
1032  {
1033 -       b43err(NULL, "BCMA is not supported yet!");
1034 -       return -EOPNOTSUPP;
1035 +       struct b43_bus_dev *dev;
1036 +       struct b43_wl *wl;
1037 +       int err;
1038 +
1039 +       dev = b43_bus_dev_bcma_init(core);
1040 +       if (!dev)
1041 +               return -ENODEV;
1042 +
1043 +       wl = b43_wireless_init(dev);
1044 +       if (IS_ERR(wl)) {
1045 +               err = PTR_ERR(wl);
1046 +               goto bcma_out;
1047 +       }
1048 +
1049 +       err = b43_one_core_attach(dev, wl);
1050 +       if (err)
1051 +               goto bcma_err_wireless_exit;
1052 +
1053 +       err = ieee80211_register_hw(wl->hw);
1054 +       if (err)
1055 +               goto bcma_err_one_core_detach;
1056 +       b43_leds_register(wl->current_dev);
1057 +
1058 +bcma_out:
1059 +       return err;
1060 +
1061 +bcma_err_one_core_detach:
1062 +       b43_one_core_detach(dev);
1063 +bcma_err_wireless_exit:
1064 +       ieee80211_free_hw(wl->hw);
1065 +       return err;
1066  }
1067
1068  static void b43_bcma_remove(struct bcma_device *core)
1069  {
1070 -       /* TODO */
1071 +       struct b43_wldev *wldev = bcma_get_drvdata(core);
1072 +       struct b43_wl *wl = wldev->wl;
1073 +
1074 +       /* We must cancel any work here before unregistering from ieee80211,
1075 +        * as the ieee80211 unreg will destroy the workqueue. */
1076 +       cancel_work_sync(&wldev->restart_work);
1077 +
1078 +       /* Restore the queues count before unregistering, because firmware detect
1079 +        * might have modified it. Restoring is important, so the networking
1080 +        * stack can properly free resources. */
1081 +       wl->hw->queues = wl->mac80211_initially_registered_queues;
1082 +       b43_leds_stop(wldev);
1083 +       ieee80211_unregister_hw(wl->hw);
1084 +
1085 +       b43_one_core_detach(wldev->dev);
1086 +
1087 +       b43_leds_unregister(wl);
1088 +
1089 +       ieee80211_free_hw(wl->hw);
1090  }
1091
1092  static struct bcma_driver b43_bcma_driver = {
1093 @@ -5045,7 +5316,7 @@ int b43_ssb_probe(struct ssb_device *sde
1094                 /* Probing the first core. Must setup common struct b43_wl */
1095                 first = 1;
1096                 b43_sprom_fixup(sdev->bus);
1097 -               wl = b43_wireless_init(sdev);
1098 +               wl = b43_wireless_init(dev);
1099                 if (IS_ERR(wl)) {
1100                         err = PTR_ERR(wl);
1101                         goto out;
1102 --- a/drivers/net/wireless/b43/phy_common.c
1103 +++ b/drivers/net/wireless/b43/phy_common.c
1104 @@ -32,6 +32,7 @@
1105  #include "phy_n.h"
1106  #include "phy_lp.h"
1107  #include "phy_ht.h"
1108 +#include "phy_lcn.h"
1109  #include "b43.h"
1110  #include "main.h"
1111
1112 @@ -65,6 +66,11 @@ int b43_phy_allocate(struct b43_wldev *d
1113                 phy->ops = &b43_phyops_ht;
1114  #endif
1115                 break;
1116 +       case B43_PHYTYPE_LCN:
1117 +#ifdef CONFIG_B43_PHY_LCN
1118 +               phy->ops = &b43_phyops_lcn;
1119 +#endif
1120 +               break;
1121         }
1122         if (B43_WARN_ON(!phy->ops))
1123                 return -ENODEV;
1124 --- a/drivers/net/wireless/b43/phy_common.h
1125 +++ b/drivers/net/wireless/b43/phy_common.h
1126 @@ -198,6 +198,7 @@ struct b43_phy_g;
1127  struct b43_phy_n;
1128  struct b43_phy_lp;
1129  struct b43_phy_ht;
1130 +struct b43_phy_lcn;
1131
1132  struct b43_phy {
1133         /* Hardware operation callbacks. */
1134 @@ -222,6 +223,8 @@ struct b43_phy {
1135                 struct b43_phy_lp *lp;
1136                 /* HT-PHY specific information */
1137                 struct b43_phy_ht *ht;
1138 +               /* LCN-PHY specific information */
1139 +               struct b43_phy_lcn *lcn;
1140         };
1141
1142         /* Band support flags. */
1143 --- a/drivers/net/wireless/b43/phy_ht.c
1144 +++ b/drivers/net/wireless/b43/phy_ht.c
1145 @@ -24,9 +24,14 @@
1146
1147  #include "b43.h"
1148  #include "phy_ht.h"
1149 +#include "tables_phy_ht.h"
1150  #include "radio_2059.h"
1151  #include "main.h"
1152
1153 +/**************************************************
1154 + * Radio 2059.
1155 + **************************************************/
1156 +
1157  static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
1158                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
1159  {
1160 @@ -56,7 +61,7 @@ static void b43_radio_2059_channel_setup
1161         b43_radio_write(dev, 0x98, e->radio_syn98);
1162
1163         for (i = 0; i < 2; i++) {
1164 -               routing = i ? 0x800 : 0x400;
1165 +               routing = i ? R2059_RXRX1 : R2059_TXRX0;
1166                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
1167                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
1168                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
1169 @@ -78,11 +83,120 @@ static void b43_radio_2059_channel_setup
1170         udelay(300);
1171  }
1172
1173 +static void b43_radio_2059_init(struct b43_wldev *dev)
1174 +{
1175 +       const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
1176 +       const u16 radio_values[3][2] = {
1177 +               { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
1178 +       };
1179 +       u16 i, j;
1180 +
1181 +       b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
1182 +       b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
1183 +
1184 +       for (i = 0; i < ARRAY_SIZE(routing); i++)
1185 +               b43_radio_set(dev, routing[i] | 0x146, 0x3);
1186 +
1187 +       b43_radio_set(dev, 0x2e, 0x0078);
1188 +       b43_radio_set(dev, 0xc0, 0x0080);
1189 +       msleep(2);
1190 +       b43_radio_mask(dev, 0x2e, ~0x0078);
1191 +       b43_radio_mask(dev, 0xc0, ~0x0080);
1192 +
1193 +       if (1) { /* FIXME */
1194 +               b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
1195 +               udelay(10);
1196 +               b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
1197 +               b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
1198 +
1199 +               b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
1200 +               udelay(100);
1201 +               b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
1202 +
1203 +               for (i = 0; i < 10000; i++) {
1204 +                       if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
1205 +                               i = 0;
1206 +                               break;
1207 +                       }
1208 +                       udelay(100);
1209 +               }
1210 +               if (i)
1211 +                       b43err(dev->wl, "radio 0x945 timeout\n");
1212 +
1213 +               b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
1214 +               b43_radio_set(dev, 0xa, 0x60);
1215 +
1216 +               for (i = 0; i < 3; i++) {
1217 +                       b43_radio_write(dev, 0x17F, radio_values[i][0]);
1218 +                       b43_radio_write(dev, 0x13D, 0x6E);
1219 +                       b43_radio_write(dev, 0x13E, radio_values[i][1]);
1220 +                       b43_radio_write(dev, 0x13C, 0x55);
1221 +
1222 +                       for (j = 0; j < 10000; j++) {
1223 +                               if (b43_radio_read(dev, 0x140) & 2) {
1224 +                                       j = 0;
1225 +                                       break;
1226 +                               }
1227 +                               udelay(500);
1228 +                       }
1229 +                       if (j)
1230 +                               b43err(dev->wl, "radio 0x140 timeout\n");
1231 +
1232 +                       b43_radio_write(dev, 0x13C, 0x15);
1233 +               }
1234 +
1235 +               b43_radio_mask(dev, 0x17F, ~0x1);
1236 +       }
1237 +
1238 +       b43_radio_mask(dev, 0x11, ~0x0008);
1239 +}
1240 +
1241 +/**************************************************
1242 + * Channel switching ops.
1243 + **************************************************/
1244 +
1245  static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
1246                                 const struct b43_phy_ht_channeltab_e_phy *e,
1247                                 struct ieee80211_channel *new_channel)
1248  {
1249 -       /* TODO */
1250 +       bool old_band_5ghz;
1251 +       u8 i;
1252 +
1253 +       old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
1254 +       if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1255 +               /* TODO */
1256 +       } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1257 +               /* TODO */
1258 +       }
1259 +
1260 +       b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
1261 +       b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
1262 +       b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
1263 +       b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
1264 +       b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
1265 +       b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
1266 +
1267 +       /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
1268 +
1269 +       /* TODO: separated function? */
1270 +       for (i = 0; i < 3; i++) {
1271 +               u16 mask;
1272 +               u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
1273 +
1274 +               if (0) /* FIXME */
1275 +                       mask = 0x2 << (i * 4);
1276 +               else
1277 +                       mask = 0;
1278 +               b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
1279 +
1280 +               b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
1281 +               b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
1282 +                               tmp & 0xFF);
1283 +               b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
1284 +                               tmp & 0xFF);
1285 +       }
1286 +
1287 +       b43_phy_write(dev, 0x017e, 0x3830);
1288  }
1289
1290  static int b43_phy_ht_set_channel(struct b43_wldev *dev,
1291 @@ -139,6 +253,13 @@ static void b43_phy_ht_op_prepare_struct
1292         memset(phy_ht, 0, sizeof(*phy_ht));
1293  }
1294
1295 +static int b43_phy_ht_op_init(struct b43_wldev *dev)
1296 +{
1297 +       b43_phy_ht_tables_init(dev);
1298 +
1299 +       return 0;
1300 +}
1301 +
1302  static void b43_phy_ht_op_free(struct b43_wldev *dev)
1303  {
1304         struct b43_phy *phy = &dev->phy;
1305 @@ -155,13 +276,25 @@ static void b43_phy_ht_op_software_rfkil
1306         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
1307                 b43err(dev->wl, "MAC not suspended\n");
1308
1309 +       /* In the following PHY ops we copy wl's dummy behaviour.
1310 +        * TODO: Find out if reads (currently hidden in masks/masksets) are
1311 +        * needed and replace following ops with just writes or w&r.
1312 +        * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
1313 +        * cause delayed (!) machine lock up. */
1314         if (blocked) {
1315 -               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
1316 +               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
1317         } else {
1318 -               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
1319 -               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x1);
1320 -               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
1321 -               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x2);
1322 +               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
1323 +               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
1324 +               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
1325 +               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
1326 +
1327 +               if (dev->phy.radio_ver == 0x2059)
1328 +                       b43_radio_2059_init(dev);
1329 +               else
1330 +                       B43_WARN_ON(1);
1331 +
1332 +               b43_switch_channel(dev, dev->phy.channel);
1333         }
1334  }
1335
1336 @@ -203,7 +336,7 @@ static int b43_phy_ht_op_switch_channel(
1337  static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1338  {
1339         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1340 -               return 1;
1341 +               return 11;
1342         return 36;
1343  }
1344
1345 @@ -247,6 +380,16 @@ static void b43_phy_ht_op_radio_write(st
1346         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1347  }
1348
1349 +static enum b43_txpwr_result
1350 +b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1351 +{
1352 +       return B43_TXPWR_RES_DONE;
1353 +}
1354 +
1355 +static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1356 +{
1357 +}
1358 +
1359  /**************************************************
1360   * PHY ops struct.
1361   **************************************************/
1362 @@ -255,9 +398,7 @@ const struct b43_phy_operations b43_phyo
1363         .allocate               = b43_phy_ht_op_allocate,
1364         .free                   = b43_phy_ht_op_free,
1365         .prepare_structs        = b43_phy_ht_op_prepare_structs,
1366 -       /*
1367         .init                   = b43_phy_ht_op_init,
1368 -       */
1369         .phy_read               = b43_phy_ht_op_read,
1370         .phy_write              = b43_phy_ht_op_write,
1371         .phy_maskset            = b43_phy_ht_op_maskset,
1372 @@ -267,8 +408,6 @@ const struct b43_phy_operations b43_phyo
1373         .switch_analog          = b43_phy_ht_op_switch_analog,
1374         .switch_channel         = b43_phy_ht_op_switch_channel,
1375         .get_default_chan       = b43_phy_ht_op_get_default_chan,
1376 -       /*
1377         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
1378         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
1379 -       */
1380  };
1381 --- a/drivers/net/wireless/b43/phy_ht.h
1382 +++ b/drivers/net/wireless/b43/phy_ht.h
1383 @@ -4,9 +4,16 @@
1384  #include "phy_common.h"
1385
1386
1387 +#define B43_PHY_HT_BANDCTL                     0x009 /* Band control */
1388  #define B43_PHY_HT_TABLE_ADDR                  0x072 /* Table address */
1389  #define B43_PHY_HT_TABLE_DATALO                        0x073 /* Table data low */
1390  #define B43_PHY_HT_TABLE_DATAHI                        0x074 /* Table data high */
1391 +#define B43_PHY_HT_BW1                         0x1CE
1392 +#define B43_PHY_HT_BW2                         0x1CF
1393 +#define B43_PHY_HT_BW3                         0x1D0
1394 +#define B43_PHY_HT_BW4                         0x1D1
1395 +#define B43_PHY_HT_BW5                         0x1D2
1396 +#define B43_PHY_HT_BW6                         0x1D3
1397
1398  #define B43_PHY_HT_RF_CTL1                     B43_PHY_EXTG(0x010)
1399
1400 @@ -20,7 +27,12 @@
1401
1402  /* Values for PHY registers used on channel switching */
1403  struct b43_phy_ht_channeltab_e_phy {
1404 -       /* TODO */
1405 +       u16 bw1;
1406 +       u16 bw2;
1407 +       u16 bw3;
1408 +       u16 bw4;
1409 +       u16 bw5;
1410 +       u16 bw6;
1411  };
1412
1413
1414 --- /dev/null
1415 +++ b/drivers/net/wireless/b43/phy_lcn.c
1416 @@ -0,0 +1,52 @@
1417 +/*
1418 +
1419 +  Broadcom B43 wireless driver
1420 +  IEEE 802.11n LCN-PHY support
1421 +
1422 +  This program is free software; you can redistribute it and/or modify
1423 +  it under the terms of the GNU General Public License as published by
1424 +  the Free Software Foundation; either version 2 of the License, or
1425 +  (at your option) any later version.
1426 +
1427 +  This program is distributed in the hope that it will be useful,
1428 +  but WITHOUT ANY WARRANTY; without even the implied warranty of
1429 +  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1430 +  GNU General Public License for more details.
1431 +
1432 +  You should have received a copy of the GNU General Public License
1433 +  along with this program; see the file COPYING.  If not, write to
1434 +  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
1435 +  Boston, MA 02110-1301, USA.
1436 +
1437 +*/
1438 +
1439 +#include <linux/slab.h>
1440 +
1441 +#include "b43.h"
1442 +#include "phy_lcn.h"
1443 +#include "tables_phy_lcn.h"
1444 +#include "main.h"
1445 +
1446 +/**************************************************
1447 + * PHY ops struct.
1448 + **************************************************/
1449 +
1450 +const struct b43_phy_operations b43_phyops_lcn = {
1451 +       /*
1452 +       .allocate               = b43_phy_lcn_op_allocate,
1453 +       .free                   = b43_phy_lcn_op_free,
1454 +       .prepare_structs        = b43_phy_lcn_op_prepare_structs,
1455 +       .init                   = b43_phy_lcn_op_init,
1456 +       .phy_read               = b43_phy_lcn_op_read,
1457 +       .phy_write              = b43_phy_lcn_op_write,
1458 +       .phy_maskset            = b43_phy_lcn_op_maskset,
1459 +       .radio_read             = b43_phy_lcn_op_radio_read,
1460 +       .radio_write            = b43_phy_lcn_op_radio_write,
1461 +       .software_rfkill        = b43_phy_lcn_op_software_rfkill,
1462 +       .switch_analog          = b43_phy_lcn_op_switch_analog,
1463 +       .switch_channel         = b43_phy_lcn_op_switch_channel,
1464 +       .get_default_chan       = b43_phy_lcn_op_get_default_chan,
1465 +       .recalc_txpower         = b43_phy_lcn_op_recalc_txpower,
1466 +       .adjust_txpower         = b43_phy_lcn_op_adjust_txpower,
1467 +       */
1468 +};
1469 --- /dev/null
1470 +++ b/drivers/net/wireless/b43/phy_lcn.h
1471 @@ -0,0 +1,14 @@
1472 +#ifndef B43_PHY_LCN_H_
1473 +#define B43_PHY_LCN_H_
1474 +
1475 +#include "phy_common.h"
1476 +
1477 +
1478 +struct b43_phy_lcn {
1479 +};
1480 +
1481 +
1482 +struct b43_phy_operations;
1483 +extern const struct b43_phy_operations b43_phyops_lcn;
1484 +
1485 +#endif /* B43_PHY_LCN_H_ */
1486 \ No newline at end of file
1487 --- a/drivers/net/wireless/b43/phy_n.c
1488 +++ b/drivers/net/wireless/b43/phy_n.c
1489 @@ -603,17 +603,33 @@ static void b43_nphy_tx_lp_fbw(struct b4
1490  /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
1491  static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
1492  {
1493 -       u32 tmslow;
1494 +       u32 tmp;
1495
1496         if (dev->phy.type != B43_PHYTYPE_N)
1497                 return;
1498
1499 -       tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
1500 -       if (force)
1501 -               tmslow |= SSB_TMSLOW_FGC;
1502 -       else
1503 -               tmslow &= ~SSB_TMSLOW_FGC;
1504 -       ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
1505 +       switch (dev->dev->bus_type) {
1506 +#ifdef CONFIG_B43_BCMA
1507 +       case B43_BUS_BCMA:
1508 +               tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1509 +               if (force)
1510 +                       tmp |= BCMA_IOCTL_FGC;
1511 +               else
1512 +                       tmp &= ~BCMA_IOCTL_FGC;
1513 +               bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1514 +               break;
1515 +#endif
1516 +#ifdef CONFIG_B43_SSB
1517 +       case B43_BUS_SSB:
1518 +               tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
1519 +               if (force)
1520 +                       tmp |= SSB_TMSLOW_FGC;
1521 +               else
1522 +                       tmp &= ~SSB_TMSLOW_FGC;
1523 +               ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
1524 +               break;
1525 +#endif
1526 +       }
1527  }
1528
1529  /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
1530 @@ -958,8 +974,21 @@ static void b43_nphy_superswitch_init(st
1531                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1532                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1533
1534 -               ssb_chipco_gpio_control(&dev->sdev->bus->chipco, 0xFC00,
1535 -                                       0xFC00);
1536 +               switch (dev->dev->bus_type) {
1537 +#ifdef CONFIG_B43_BCMA
1538 +               case B43_BUS_BCMA:
1539 +                       bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1540 +                                                0xFC00, 0xFC00);
1541 +                       break;
1542 +#endif
1543 +#ifdef CONFIG_B43_SSB
1544 +               case B43_BUS_SSB:
1545 +                       ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1546 +                                               0xFC00, 0xFC00);
1547 +                       break;
1548 +#endif
1549 +               }
1550 +
1551                 b43_write32(dev, B43_MMIO_MACCTL,
1552                         b43_read32(dev, B43_MMIO_MACCTL) &
1553                         ~B43_MACCTL_GPOUTSMSK);
1554 @@ -3600,7 +3629,20 @@ int b43_phy_initn(struct b43_wldev *dev)
1555         if ((dev->phy.rev >= 3) &&
1556            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
1557            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1558 -               chipco_set32(&dev->sdev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1559 +               switch (dev->dev->bus_type) {
1560 +#ifdef CONFIG_B43_BCMA
1561 +               case B43_BUS_BCMA:
1562 +                       bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
1563 +                                     BCMA_CC_CHIPCTL, 0x40);
1564 +                       break;
1565 +#endif
1566 +#ifdef CONFIG_B43_SSB
1567 +               case B43_BUS_SSB:
1568 +                       chipco_set32(&dev->dev->sdev->bus->chipco,
1569 +                                    SSB_CHIPCO_CHIPCTL, 0x40);
1570 +                       break;
1571 +#endif
1572 +               }
1573         }
1574         nphy->deaf_count = 0;
1575         b43_nphy_tables_init(dev);
1576 --- a/drivers/net/wireless/b43/radio_2059.c
1577 +++ b/drivers/net/wireless/b43/radio_2059.c
1578 @@ -23,8 +23,152 @@
1579  #include "b43.h"
1580  #include "radio_2059.h"
1581
1582 +#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
1583 +                 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
1584 +                 r20, r21, r22, r23, r24, r25, r26, r27, r28) \
1585 +       .radio_syn16                    = r00,  \
1586 +       .radio_syn17                    = r01,  \
1587 +       .radio_syn22                    = r02,  \
1588 +       .radio_syn25                    = r03,  \
1589 +       .radio_syn27                    = r04,  \
1590 +       .radio_syn28                    = r05,  \
1591 +       .radio_syn29                    = r06,  \
1592 +       .radio_syn2c                    = r07,  \
1593 +       .radio_syn2d                    = r08,  \
1594 +       .radio_syn37                    = r09,  \
1595 +       .radio_syn41                    = r10,  \
1596 +       .radio_syn43                    = r11,  \
1597 +       .radio_syn47                    = r12,  \
1598 +       .radio_syn4a                    = r13,  \
1599 +       .radio_syn58                    = r14,  \
1600 +       .radio_syn5a                    = r15,  \
1601 +       .radio_syn6a                    = r16,  \
1602 +       .radio_syn6d                    = r17,  \
1603 +       .radio_syn6e                    = r18,  \
1604 +       .radio_syn92                    = r19,  \
1605 +       .radio_syn98                    = r20,  \
1606 +       .radio_rxtx4a                   = r21,  \
1607 +       .radio_rxtx58                   = r22,  \
1608 +       .radio_rxtx5a                   = r23,  \
1609 +       .radio_rxtx6a                   = r24,  \
1610 +       .radio_rxtx6d                   = r25,  \
1611 +       .radio_rxtx6e                   = r26,  \
1612 +       .radio_rxtx92                   = r27,  \
1613 +       .radio_rxtx98                   = r28
1614 +
1615 +#define PHYREGS(r0, r1, r2, r3, r4, r5)        \
1616 +       .phy_regs.bw1   = r0,   \
1617 +       .phy_regs.bw2   = r1,   \
1618 +       .phy_regs.bw3   = r2,   \
1619 +       .phy_regs.bw4   = r3,   \
1620 +       .phy_regs.bw5   = r4,   \
1621 +       .phy_regs.bw6   = r5
1622 +
1623 +static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radio2059[] = {
1624 +  {    .freq                   = 2412,
1625 +       RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
1626 +                 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
1627 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1628 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1629 +       PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
1630 +  },
1631 +  {    .freq                   = 2417,
1632 +       RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
1633 +                 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
1634 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1635 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1636 +       PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
1637 +  },
1638 +  {    .freq                   = 2422,
1639 +       RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
1640 +                 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
1641 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1642 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1643 +       PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
1644 +  },
1645 +  {    .freq                   = 2427,
1646 +       RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
1647 +                 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
1648 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1649 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1650 +       PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
1651 +  },
1652 +  {    .freq                   = 2432,
1653 +       RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
1654 +                 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
1655 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1656 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1657 +       PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
1658 +  },
1659 +  {    .freq                   = 2437,
1660 +       RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
1661 +                 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
1662 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1663 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1664 +       PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
1665 +  },
1666 +  {    .freq                   = 2442,
1667 +       RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
1668 +                 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
1669 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1670 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1671 +       PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
1672 +  },
1673 +  {    .freq                   = 2447,
1674 +       RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
1675 +                 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
1676 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1677 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1678 +       PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
1679 +  },
1680 +  {    .freq                   = 2452,
1681 +       RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
1682 +                 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
1683 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1684 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1685 +       PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
1686 +  },
1687 +  {    .freq                   = 2457,
1688 +       RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
1689 +                 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
1690 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1691 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1692 +       PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
1693 +  },
1694 +  {    .freq                   = 2462,
1695 +       RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
1696 +                 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
1697 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1698 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1699 +       PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
1700 +  },
1701 +  {    .freq                   = 2467,
1702 +       RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
1703 +                 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
1704 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1705 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1706 +       PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
1707 +  },
1708 +  {    .freq                   = 2472,
1709 +       RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
1710 +                 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
1711 +                 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
1712 +                 0x00, 0x00, 0x00, 0xf0, 0x00),
1713 +       PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
1714 +  },
1715 +};
1716 +
1717  const struct b43_phy_ht_channeltab_e_radio2059
1718  *b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq)
1719  {
1720 +       const struct b43_phy_ht_channeltab_e_radio2059 *e;
1721 +       unsigned int i;
1722 +
1723 +       e = b43_phy_ht_channeltab_radio2059;
1724 +       for (i = 0; i < ARRAY_SIZE(b43_phy_ht_channeltab_radio2059); i++, e++) {
1725 +               if (e->freq == freq)
1726 +                       return e;
1727 +       }
1728 +
1729         return NULL;
1730  }
1731 --- a/drivers/net/wireless/b43/radio_2059.h
1732 +++ b/drivers/net/wireless/b43/radio_2059.h
1733 @@ -5,6 +5,11 @@
1734
1735  #include "phy_ht.h"
1736
1737 +#define R2059_SYN                      0x000
1738 +#define R2059_TXRX0                    0x400
1739 +#define R2059_RXRX1                    0x800
1740 +#define R2059_ALL                      0xC00
1741 +
1742  /* Values for various registers uploaded on channel switching */
1743  struct b43_phy_ht_channeltab_e_radio2059 {
1744         /* The channel frequency in MHz */
1745 --- /dev/null
1746 +++ b/drivers/net/wireless/b43/tables_phy_ht.c
1747 @@ -0,0 +1,750 @@
1748 +/*
1749 +
1750 +  Broadcom B43 wireless driver
1751 +  IEEE 802.11n HT-PHY data tables
1752 +
1753 +  This program is free software; you can redistribute it and/or modify
1754 +  it under the terms of the GNU General Public License as published by
1755 +  the Free Software Foundation; either version 2 of the License, or
1756 +  (at your option) any later version.
1757 +
1758 +  This program is distributed in the hope that it will be useful,
1759 +  but WITHOUT ANY WARRANTY; without even the implied warranty of
1760 +  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1761 +  GNU General Public License for more details.
1762 +
1763 +  You should have received a copy of the GNU General Public License
1764 +  along with this program; see the file COPYING.  If not, write to
1765 +  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
1766 +  Boston, MA 02110-1301, USA.
1767 +
1768 +*/
1769 +
1770 +#include "b43.h"
1771 +#include "tables_phy_ht.h"
1772 +#include "phy_common.h"
1773 +#include "phy_ht.h"
1774 +
1775 +static const u16 b43_httab_0x12[] = {
1776 +       0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019,
1777 +       0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090,
1778 +       0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108,
1779 +       0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c,
1780 +       0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199,
1781 +       0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8,
1782 +       0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128,
1783 +       0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a,
1784 +       0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8,
1785 +       0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8,
1786 +       0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa,
1787 +       0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca,
1788 +       0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001,
1789 +       0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014,
1790 +       0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081,
1791 +       0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094,
1792 +       0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007,
1793 +       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
1794 +       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
1795 +       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
1796 +       0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
1797 +       0x0007, 0x0007,
1798 +};
1799 +
1800 +static const u16 b43_httab_0x27[] = {
1801 +       0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a,
1802 +       0x001d, 0x0020, 0x0009, 0x000e, 0x0011, 0x0014,
1803 +       0x0017, 0x001a, 0x001d, 0x0020, 0x0009, 0x000e,
1804 +       0x0011, 0x0014, 0x0017, 0x001a, 0x001d, 0x0020,
1805 +       0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a,
1806 +       0x001d, 0x0020,
1807 +};
1808 +
1809 +static const u16 b43_httab_0x26[] = {
1810 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1811 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1812 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1813 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1814 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1815 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1816 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1817 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1818 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1819 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1820 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1821 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1822 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1823 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1824 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1825 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1826 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1827 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1828 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1829 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1830 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1831 +       0x0000, 0x0000,
1832 +};
1833 +
1834 +static const u32 b43_httab_0x25[] = {
1835 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1836 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1837 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1838 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1839 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1840 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1841 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1842 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1843 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1844 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1845 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1846 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1847 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1848 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1849 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1850 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1851 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1852 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1853 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1854 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1855 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1856 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1857 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1858 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1859 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1860 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1861 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1862 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1863 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1864 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1865 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1866 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1867 +};
1868 +
1869 +static const u32 b43_httab_0x2f[] = {
1870 +       0x00035700, 0x0002cc9a, 0x00026666, 0x0001581f,
1871 +       0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f,
1872 +       0x0001581f, 0x0001581f, 0x0001581f, 0x00035700,
1873 +       0x0002cc9a, 0x00026666, 0x0001581f, 0x0001581f,
1874 +       0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f,
1875 +       0x0001581f, 0x0001581f,
1876 +};
1877 +
1878 +static const u16 b43_httab_0x1a[] = {
1879 +       0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
1880 +       0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
1881 +       0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
1882 +       0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
1883 +       0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
1884 +       0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
1885 +       0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
1886 +       0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
1887 +       0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
1888 +       0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
1889 +       0x000b, 0x0007, 0x0002, 0x00fd,
1890 +};
1891 +
1892 +static const u16 b43_httab_0x1b[] = {
1893 +       0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
1894 +       0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
1895 +       0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
1896 +       0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
1897 +       0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
1898 +       0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
1899 +       0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
1900 +       0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
1901 +       0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
1902 +       0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
1903 +       0x000b, 0x0007, 0x0002, 0x00fd,
1904 +};
1905 +
1906 +static const u16 b43_httab_0x1c[] = {
1907 +       0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
1908 +       0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
1909 +       0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
1910 +       0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
1911 +       0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
1912 +       0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
1913 +       0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
1914 +       0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
1915 +       0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
1916 +       0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
1917 +       0x000b, 0x0007, 0x0002, 0x00fd,
1918 +};
1919 +
1920 +static const u32 b43_httab_0x1a_0xc0[] = {
1921 +       0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
1922 +       0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
1923 +       0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
1924 +       0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
1925 +       0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
1926 +       0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
1927 +       0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
1928 +       0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
1929 +       0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
1930 +       0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
1931 +       0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
1932 +       0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
1933 +       0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
1934 +       0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
1935 +       0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
1936 +       0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
1937 +       0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
1938 +       0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
1939 +       0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
1940 +       0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
1941 +       0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
1942 +       0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
1943 +       0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
1944 +       0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
1945 +       0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
1946 +       0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
1947 +       0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
1948 +       0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
1949 +       0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
1950 +       0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
1951 +       0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
1952 +       0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
1953 +};
1954 +
1955 +static const u32 b43_httab_0x1a_0x140[] = {
1956 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1957 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1958 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1959 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1960 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1961 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1962 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1963 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1964 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1965 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1966 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1967 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1968 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1969 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1970 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1971 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1972 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1973 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1974 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1975 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1976 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1977 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1978 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1979 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1980 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1981 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1982 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1983 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1984 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1985 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1986 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1987 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1988 +};
1989 +
1990 +static const u32 b43_httab_0x1b_0x140[] = {
1991 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1992 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1993 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1994 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1995 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1996 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1997 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1998 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
1999 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2000 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2001 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2002 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2003 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2004 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2005 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2006 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2007 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2008 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2009 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2010 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2011 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2012 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2013 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2014 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2015 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2016 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2017 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2018 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2019 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2020 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2021 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2022 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2023 +};
2024 +
2025 +static const u32 b43_httab_0x1c_0x140[] = {
2026 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2027 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2028 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2029 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2030 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2031 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2032 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2033 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2034 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2035 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2036 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2037 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2038 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2039 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2040 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2041 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2042 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2043 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2044 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2045 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2046 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2047 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2048 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2049 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2050 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2051 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2052 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2053 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2054 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2055 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2056 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2057 +       0x00000000, 0x00000000, 0x00000000, 0x00000000,
2058 +};
2059 +
2060 +static const u16 b43_httab_0x1a_0x1c0[] = {
2061 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2062 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2063 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2064 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2065 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2066 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2067 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2068 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2069 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2070 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2071 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2072 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2073 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2074 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2075 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2076 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2077 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2078 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2079 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2080 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2081 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2082 +       0x0000, 0x0000,
2083 +};
2084 +
2085 +static const u16 b43_httab_0x1b_0x1c0[] = {
2086 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2087 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2088 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2089 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2090 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2091 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2092 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2093 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2094 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2095 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2096 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2097 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2098 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2099 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2100 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2101 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2102 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2103 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2104 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2105 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2106 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2107 +       0x0000, 0x0000,
2108 +};
2109 +
2110 +static const u16 b43_httab_0x1c_0x1c0[] = {
2111 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2112 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2113 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2114 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2115 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2116 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2117 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2118 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2119 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2120 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2121 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2122 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2123 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2124 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2125 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2126 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2127 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2128 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2129 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2130 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2131 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2132 +       0x0000, 0x0000,
2133 +};
2134 +
2135 +static const u16 b43_httab_0x1a_0x240[] = {
2136 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2137 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2138 +       0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2139 +       0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2140 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2141 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2142 +       0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
2143 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2144 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2145 +       0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
2146 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2147 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2148 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2149 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2150 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2151 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2152 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2153 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2154 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2155 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2156 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2157 +       0x01d6, 0x01d6,
2158 +};
2159 +
2160 +static const u16 b43_httab_0x1b_0x240[] = {
2161 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2162 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2163 +       0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2164 +       0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2165 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2166 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2167 +       0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
2168 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2169 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2170 +       0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
2171 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2172 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2173 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2174 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2175 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2176 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2177 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2178 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2179 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2180 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2181 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2182 +       0x01d6, 0x01d6,
2183 +};
2184 +
2185 +static const u16 b43_httab_0x1c_0x240[] = {
2186 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2187 +       0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
2188 +       0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2189 +       0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
2190 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2191 +       0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
2192 +       0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
2193 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2194 +       0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
2195 +       0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
2196 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2197 +       0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
2198 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2199 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2200 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2201 +       0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
2202 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2203 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2204 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2205 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2206 +       0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
2207 +       0x01d6, 0x01d6,
2208 +};
2209 +
2210 +static const u32 b43_httab_0x1f[] = {
2211 +       0x00000000, 0x00000000, 0x00016023, 0x00006028,
2212 +       0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
2213 +       0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
2214 +       0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
2215 +       0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
2216 +       0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
2217 +       0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
2218 +       0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
2219 +       0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
2220 +       0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
2221 +       0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
2222 +       0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
2223 +       0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
2224 +       0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
2225 +       0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
2226 +       0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
2227 +};
2228 +
2229 +static const u32 b43_httab_0x21[] = {
2230 +       0x00000000, 0x00000000, 0x00016023, 0x00006028,
2231 +       0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
2232 +       0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
2233 +       0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
2234 +       0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
2235 +       0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
2236 +       0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
2237 +       0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
2238 +       0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
2239 +       0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
2240 +       0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
2241 +       0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
2242 +       0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
2243 +       0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
2244 +       0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
2245 +       0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
2246 +};
2247 +
2248 +static const u32 b43_httab_0x23[] = {
2249 +       0x00000000, 0x00000000, 0x00016023, 0x00006028,
2250 +       0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
2251 +       0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
2252 +       0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
2253 +       0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
2254 +       0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
2255 +       0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
2256 +       0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
2257 +       0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
2258 +       0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
2259 +       0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
2260 +       0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
2261 +       0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
2262 +       0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
2263 +       0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
2264 +       0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
2265 +};
2266 +
2267 +static const u32 b43_httab_0x20[] = {
2268 +       0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
2269 +       0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
2270 +       0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
2271 +       0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
2272 +       0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
2273 +       0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
2274 +       0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
2275 +       0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
2276 +       0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
2277 +       0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
2278 +       0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
2279 +       0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
2280 +       0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
2281 +       0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
2282 +       0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
2283 +       0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
2284 +};
2285 +
2286 +static const u32 b43_httab_0x22[] = {
2287 +       0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
2288 +       0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
2289 +       0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
2290 +       0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
2291 +       0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
2292 +       0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
2293 +       0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
2294 +       0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
2295 +       0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
2296 +       0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
2297 +       0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
2298 +       0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
2299 +       0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
2300 +       0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
2301 +       0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
2302 +       0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
2303 +};
2304 +
2305 +static const u32 b43_httab_0x24[] = {
2306 +       0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
2307 +       0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
2308 +       0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
2309 +       0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
2310 +       0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
2311 +       0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
2312 +       0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
2313 +       0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
2314 +       0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
2315 +       0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
2316 +       0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
2317 +       0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
2318 +       0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
2319 +       0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
2320 +       0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
2321 +       0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
2322 +};
2323 +
2324 +/**************************************************
2325 + * R/W ops.
2326 + **************************************************/
2327 +
2328 +u32 b43_httab_read(struct b43_wldev *dev, u32 offset)
2329 +{
2330 +       u32 type, value;
2331 +
2332 +       type = offset & B43_HTTAB_TYPEMASK;
2333 +       offset &= ~B43_HTTAB_TYPEMASK;
2334 +       B43_WARN_ON(offset > 0xFFFF);
2335 +
2336 +       switch (type) {
2337 +       case B43_HTTAB_8BIT:
2338 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2339 +               value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF;
2340 +               break;
2341 +       case B43_HTTAB_16BIT:
2342 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2343 +               value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
2344 +               break;
2345 +       case B43_HTTAB_32BIT:
2346 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2347 +               value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI);
2348 +               value <<= 16;
2349 +               value |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
2350 +               break;
2351 +       default:
2352 +               B43_WARN_ON(1);
2353 +               value = 0;
2354 +       }
2355 +
2356 +       return value;
2357 +}
2358 +
2359 +void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset,
2360 +                        unsigned int nr_elements, void *_data)
2361 +{
2362 +       u32 type;
2363 +       u8 *data = _data;
2364 +       unsigned int i;
2365 +
2366 +       type = offset & B43_HTTAB_TYPEMASK;
2367 +       offset &= ~B43_HTTAB_TYPEMASK;
2368 +       B43_WARN_ON(offset > 0xFFFF);
2369 +
2370 +       b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2371 +
2372 +       for (i = 0; i < nr_elements; i++) {
2373 +               switch (type) {
2374 +               case B43_HTTAB_8BIT:
2375 +                       *data = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF;
2376 +                       data++;
2377 +                       break;
2378 +               case B43_HTTAB_16BIT:
2379 +                       *((u16 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
2380 +                       data += 2;
2381 +                       break;
2382 +               case B43_HTTAB_32BIT:
2383 +                       *((u32 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI);
2384 +                       *((u32 *)data) <<= 16;
2385 +                       *((u32 *)data) |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
2386 +                       data += 4;
2387 +                       break;
2388 +               default:
2389 +                       B43_WARN_ON(1);
2390 +               }
2391 +       }
2392 +}
2393 +
2394 +void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value)
2395 +{
2396 +       u32 type;
2397 +
2398 +       type = offset & B43_HTTAB_TYPEMASK;
2399 +       offset &= 0xFFFF;
2400 +
2401 +       switch (type) {
2402 +       case B43_HTTAB_8BIT:
2403 +               B43_WARN_ON(value & ~0xFF);
2404 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2405 +               b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
2406 +               break;
2407 +       case B43_HTTAB_16BIT:
2408 +               B43_WARN_ON(value & ~0xFFFF);
2409 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2410 +               b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
2411 +               break;
2412 +       case B43_HTTAB_32BIT:
2413 +               b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2414 +               b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16);
2415 +               b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value & 0xFFFF);
2416 +               break;
2417 +       default:
2418 +               B43_WARN_ON(1);
2419 +       }
2420 +
2421 +       return;
2422 +}
2423 +
2424 +void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset,
2425 +                         unsigned int nr_elements, const void *_data)
2426 +{
2427 +       u32 type, value;
2428 +       const u8 *data = _data;
2429 +       unsigned int i;
2430 +
2431 +       type = offset & B43_HTTAB_TYPEMASK;
2432 +       offset &= ~B43_HTTAB_TYPEMASK;
2433 +       B43_WARN_ON(offset > 0xFFFF);
2434 +
2435 +       b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
2436 +
2437 +       for (i = 0; i < nr_elements; i++) {
2438 +               switch (type) {
2439 +               case B43_HTTAB_8BIT:
2440 +                       value = *data;
2441 +                       data++;
2442 +                       B43_WARN_ON(value & ~0xFF);
2443 +                       b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
2444 +                       break;
2445 +               case B43_HTTAB_16BIT:
2446 +                       value = *((u16 *)data);
2447 +                       data += 2;
2448 +                       B43_WARN_ON(value & ~0xFFFF);
2449 +                       b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
2450 +                       break;
2451 +               case B43_HTTAB_32BIT:
2452 +                       value = *((u32 *)data);
2453 +                       data += 4;
2454 +                       b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16);
2455 +                       b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO,
2456 +                                       value & 0xFFFF);
2457 +                       break;
2458 +               default:
2459 +                       B43_WARN_ON(1);
2460 +               }
2461 +       }
2462 +}
2463 +
2464 +/**************************************************
2465 + * Tables ops.
2466 + **************************************************/
2467 +
2468 +#define httab_upload(dev, offset, data) do { \
2469 +               b43_httab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
2470 +       } while (0)
2471 +void b43_phy_ht_tables_init(struct b43_wldev *dev)
2472 +{
2473 +       httab_upload(dev, B43_HTTAB16(0x12, 0), b43_httab_0x12);
2474 +       httab_upload(dev, B43_HTTAB16(0x27, 0), b43_httab_0x27);
2475 +       httab_upload(dev, B43_HTTAB16(0x26, 0), b43_httab_0x26);
2476 +       httab_upload(dev, B43_HTTAB32(0x25, 0), b43_httab_0x25);
2477 +       httab_upload(dev, B43_HTTAB32(0x2f, 0), b43_httab_0x2f);
2478 +       httab_upload(dev, B43_HTTAB16(0x1a, 0), b43_httab_0x1a);
2479 +       httab_upload(dev, B43_HTTAB16(0x1b, 0), b43_httab_0x1b);
2480 +       httab_upload(dev, B43_HTTAB16(0x1c, 0), b43_httab_0x1c);
2481 +       httab_upload(dev, B43_HTTAB32(0x1a, 0x0c0), b43_httab_0x1a_0xc0);
2482 +       httab_upload(dev, B43_HTTAB32(0x1a, 0x140), b43_httab_0x1a_0x140);
2483 +       httab_upload(dev, B43_HTTAB32(0x1b, 0x140), b43_httab_0x1b_0x140);
2484 +       httab_upload(dev, B43_HTTAB32(0x1c, 0x140), b43_httab_0x1c_0x140);
2485 +       httab_upload(dev, B43_HTTAB16(0x1a, 0x1c0), b43_httab_0x1a_0x1c0);
2486 +       httab_upload(dev, B43_HTTAB16(0x1b, 0x1c0), b43_httab_0x1b_0x1c0);
2487 +       httab_upload(dev, B43_HTTAB16(0x1c, 0x1c0), b43_httab_0x1c_0x1c0);
2488 +       httab_upload(dev, B43_HTTAB16(0x1a, 0x240), b43_httab_0x1a_0x240);
2489 +       httab_upload(dev, B43_HTTAB16(0x1b, 0x240), b43_httab_0x1b_0x240);
2490 +       httab_upload(dev, B43_HTTAB16(0x1c, 0x240), b43_httab_0x1c_0x240);
2491 +       httab_upload(dev, B43_HTTAB32(0x1f, 0), b43_httab_0x1f);
2492 +       httab_upload(dev, B43_HTTAB32(0x21, 0), b43_httab_0x21);
2493 +       httab_upload(dev, B43_HTTAB32(0x23, 0), b43_httab_0x23);
2494 +       httab_upload(dev, B43_HTTAB32(0x20, 0), b43_httab_0x20);
2495 +       httab_upload(dev, B43_HTTAB32(0x22, 0), b43_httab_0x22);
2496 +       httab_upload(dev, B43_HTTAB32(0x24, 0), b43_httab_0x24);
2497 +}
2498 --- /dev/null
2499 +++ b/drivers/net/wireless/b43/tables_phy_ht.h
2500 @@ -0,0 +1,22 @@
2501 +#ifndef B43_TABLES_PHY_HT_H_
2502 +#define B43_TABLES_PHY_HT_H_
2503 +
2504 +/* The HT-PHY tables. */
2505 +#define B43_HTTAB_TYPEMASK             0xF0000000
2506 +#define B43_HTTAB_8BIT                 0x10000000
2507 +#define B43_HTTAB_16BIT                        0x20000000
2508 +#define B43_HTTAB_32BIT                        0x30000000
2509 +#define B43_HTTAB8(table, offset)      (((table) << 10) | (offset) | B43_HTTAB_8BIT)
2510 +#define B43_HTTAB16(table, offset)     (((table) << 10) | (offset) | B43_HTTAB_16BIT)
2511 +#define B43_HTTAB32(table, offset)     (((table) << 10) | (offset) | B43_HTTAB_32BIT)
2512 +
2513 +u32 b43_httab_read(struct b43_wldev *dev, u32 offset);
2514 +void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset,
2515 +                        unsigned int nr_elements, void *_data);
2516 +void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value);
2517 +void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset,
2518 +                         unsigned int nr_elements, const void *_data);
2519 +
2520 +void b43_phy_ht_tables_init(struct b43_wldev *dev);
2521 +
2522 +#endif /* B43_TABLES_PHY_HT_H_ */
2523 --- /dev/null
2524 +++ b/drivers/net/wireless/b43/tables_phy_lcn.c
2525 @@ -0,0 +1,34 @@
2526 +/*
2527 +
2528 +  Broadcom B43 wireless driver
2529 +  IEEE 802.11n LCN-PHY data tables
2530 +
2531 +  This program is free software; you can redistribute it and/or modify
2532 +  it under the terms of the GNU General Public License as published by
2533 +  the Free Software Foundation; either version 2 of the License, or
2534 +  (at your option) any later version.
2535 +
2536 +  This program is distributed in the hope that it will be useful,
2537 +  but WITHOUT ANY WARRANTY; without even the implied warranty of
2538 +  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2539 +  GNU General Public License for more details.
2540 +
2541 +  You should have received a copy of the GNU General Public License
2542 +  along with this program; see the file COPYING.  If not, write to
2543 +  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
2544 +  Boston, MA 02110-1301, USA.
2545 +
2546 +*/
2547 +
2548 +#include "b43.h"
2549 +#include "tables_phy_lcn.h"
2550 +#include "phy_common.h"
2551 +#include "phy_lcn.h"
2552 +
2553 +/**************************************************
2554 + * Tables ops.
2555 + **************************************************/
2556 +
2557 +void b43_phy_lcn_tables_init(struct b43_wldev *dev)
2558 +{
2559 +}
2560 --- /dev/null
2561 +++ b/drivers/net/wireless/b43/tables_phy_lcn.h
2562 @@ -0,0 +1,6 @@
2563 +#ifndef B43_TABLES_PHY_LCN_H_
2564 +#define B43_TABLES_PHY_LCN_H_
2565 +
2566 +void b43_phy_lcn_tables_init(struct b43_wldev *dev);
2567 +
2568 +#endif /* B43_TABLES_PHY_LCN_H_ */