1 From d211df2956ae9d696bb0cab985426e0d236544b8 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Mon, 2 Jul 2012 17:16:00 +0200
4 Subject: [PATCH 17/20] ath9k: fix PLL initialization for AR9550
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
9 drivers/net/wireless/ath/ath9k/hw.c | 27 +++++++++++++++++++--------
10 1 files changed, 19 insertions(+), 8 deletions(-)
12 --- a/drivers/net/wireless/ath/ath9k/hw.c
13 +++ b/drivers/net/wireless/ath/ath9k/hw.c
14 @@ -861,7 +861,7 @@ static void ath9k_hw_init_pll(struct ath
15 /* program BB PLL phase_shift */
16 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
17 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
18 - } else if (AR_SREV_9340(ah)) {
19 + } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
20 u32 regval, pll2_divint, pll2_divfrac, refdiv;
22 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
23 @@ -875,9 +875,15 @@ static void ath9k_hw_init_pll(struct ath
24 pll2_divfrac = 0x1eb85;
30 + if (AR_SREV_9340(ah)) {
36 + pll2_divfrac = 0x26666;
41 regval = REG_READ(ah, AR_PHY_PLL_MODE);
42 @@ -890,8 +896,12 @@ static void ath9k_hw_init_pll(struct ath
45 regval = REG_READ(ah, AR_PHY_PLL_MODE);
46 - regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
47 - (0x4 << 26) | (0x18 << 19);
48 + if (AR_SREV_9340(ah))
49 + regval = (regval & 0x80071fff) | (0x1 << 30) |
50 + (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
52 + regval = (regval & 0x80071fff) | (0x3 << 30) |
53 + (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
54 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
55 REG_WRITE(ah, AR_PHY_PLL_MODE,
56 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
57 @@ -902,7 +912,8 @@ static void ath9k_hw_init_pll(struct ath
59 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
61 - if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
62 + if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
66 /* Switch the core clock for ar9271 to 117Mhz */
67 @@ -915,7 +926,7 @@ static void ath9k_hw_init_pll(struct ath
69 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
71 - if (AR_SREV_9340(ah)) {
72 + if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
73 if (ah->is_clk_25mhz) {
74 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
75 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);