1 From 2b4e3da2e595e1c76f65f7da752ec1f037446bd2 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Mon, 2 Jul 2012 17:10:16 +0200
4 Subject: [PATCH 09/20] ath9k: add mode register initialization code for AR9550
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
9 drivers/net/wireless/ath/ath9k/ar9003_hw.c | 86 ++++++++++++++++++++++++++-
10 drivers/net/wireless/ath/ath9k/ar9003_phy.c | 61 +++++++++++++++++++-
11 drivers/net/wireless/ath/ath9k/hw.h | 1 +
12 3 files changed, 145 insertions(+), 3 deletions(-)
14 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
15 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
16 @@ -328,7 +328,61 @@ static void ar9003_hw_init_mode_regs(str
18 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
19 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
20 + } else if (AR_SREV_9550(ah)) {
22 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
23 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
24 + ar955x_1p0_mac_core,
25 + ARRAY_SIZE(ar955x_1p0_mac_core), 2);
26 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
27 + ar955x_1p0_mac_postamble,
28 + ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
31 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
32 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
33 + ar955x_1p0_baseband_core,
34 + ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
35 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
36 + ar955x_1p0_baseband_postamble,
37 + ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
40 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
41 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
42 + ar955x_1p0_radio_core,
43 + ARRAY_SIZE(ar955x_1p0_radio_core), 2);
44 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
45 + ar955x_1p0_radio_postamble,
46 + ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
49 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
50 + ar955x_1p0_soc_preamble,
51 + ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
52 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
53 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
54 + ar955x_1p0_soc_postamble,
55 + ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
58 + INIT_INI_ARRAY(&ah->iniModesRxGain,
59 + ar955x_1p0_common_wo_xlna_rx_gain_table,
60 + ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
62 + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
63 + ar955x_1p0_common_wo_xlna_rx_gain_bounds,
64 + ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
66 + INIT_INI_ARRAY(&ah->iniModesTxGain,
67 + ar955x_1p0_modes_xpa_tx_gain_table,
68 + ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
71 + /* Fast clock modal settings */
72 + INIT_INI_ARRAY(&ah->iniModesFastClock,
73 + ar955x_1p0_modes_fast_clock,
74 + ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
75 } else if (AR_SREV_9580(ah)) {
77 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
78 @@ -471,6 +525,11 @@ static void ar9003_tx_gain_table_mode0(s
79 ar9485_modes_lowest_ob_db_tx_gain_1_1,
80 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
82 + else if (AR_SREV_9550(ah))
83 + INIT_INI_ARRAY(&ah->iniModesTxGain,
84 + ar955x_1p0_modes_xpa_tx_gain_table,
85 + ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
87 else if (AR_SREV_9580(ah))
88 INIT_INI_ARRAY(&ah->iniModesTxGain,
89 ar9580_1p0_lowest_ob_db_tx_gain_table,
90 @@ -515,6 +574,11 @@ static void ar9003_tx_gain_table_mode1(s
91 ar9580_1p0_high_ob_db_tx_gain_table,
92 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
94 + else if (AR_SREV_9550(ah))
95 + INIT_INI_ARRAY(&ah->iniModesTxGain,
96 + ar955x_1p0_modes_no_xpa_tx_gain_table,
97 + ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
99 else if (AR_SREV_9462_20(ah))
100 INIT_INI_ARRAY(&ah->iniModesTxGain,
101 ar9462_modes_high_ob_db_tx_gain_table_2p0,
102 @@ -636,7 +700,16 @@ static void ar9003_rx_gain_table_mode0(s
103 ar9485Common_wo_xlna_rx_gain_1_1,
104 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
106 - else if (AR_SREV_9580(ah))
107 + else if (AR_SREV_9550(ah)) {
108 + INIT_INI_ARRAY(&ah->iniModesRxGain,
109 + ar955x_1p0_common_rx_gain_table,
110 + ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
112 + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
113 + ar955x_1p0_common_rx_gain_bounds,
114 + ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
116 + } else if (AR_SREV_9580(ah))
117 INIT_INI_ARRAY(&ah->iniModesRxGain,
118 ar9580_1p0_rx_gain_table,
119 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
120 @@ -680,7 +753,16 @@ static void ar9003_rx_gain_table_mode1(s
121 ar9462_common_wo_xlna_rx_gain_table_2p0,
122 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
124 - else if (AR_SREV_9580(ah))
125 + else if (AR_SREV_9550(ah)) {
126 + INIT_INI_ARRAY(&ah->iniModesRxGain,
127 + ar955x_1p0_common_wo_xlna_rx_gain_table,
128 + ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
130 + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
131 + ar955x_1p0_common_wo_xlna_rx_gain_bounds,
132 + ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
134 + } else if (AR_SREV_9580(ah))
135 INIT_INI_ARRAY(&ah->iniModesRxGain,
136 ar9580_1p0_wo_xlna_rx_gain_table,
137 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
138 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
139 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
140 @@ -620,6 +620,50 @@ static void ar9003_hw_prog_ini(struct at
144 +static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
145 + struct ath9k_channel *chan)
149 + switch (chan->chanmode) {
151 + case CHANNEL_A_HT20:
152 + if (chan->channel <= 5350)
154 + else if ((chan->channel > 5350) && (chan->channel <= 5600))
160 + case CHANNEL_A_HT40PLUS:
161 + case CHANNEL_A_HT40MINUS:
162 + if (chan->channel <= 5350)
164 + else if ((chan->channel > 5350) && (chan->channel <= 5600))
171 + case CHANNEL_G_HT20:
176 + case CHANNEL_G_HT40PLUS:
177 + case CHANNEL_G_HT40MINUS:
188 static int ar9003_hw_process_ini(struct ath_hw *ah,
189 struct ath9k_channel *chan)
191 @@ -661,7 +705,22 @@ static int ar9003_hw_process_ini(struct
194 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
195 - REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
196 + if (AR_SREV_9550(ah))
197 + REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
200 + if (AR_SREV_9550(ah)) {
201 + int modes_txgain_index;
203 + modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
204 + if (modes_txgain_index < 0)
207 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
210 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
214 * For 5GHz channels requiring Fast Clock, apply
215 --- a/drivers/net/wireless/ath/ath9k/hw.h
216 +++ b/drivers/net/wireless/ath/ath9k/hw.h
217 @@ -820,6 +820,7 @@ struct ath_hw {
218 struct ar5416IniArray iniModesFastClock;
219 struct ar5416IniArray iniAdditional;
220 struct ar5416IniArray iniModesRxGain;
221 + struct ar5416IniArray ini_modes_rx_gain_bounds;
222 struct ar5416IniArray iniModesTxGain;
223 struct ar5416IniArray iniCckfirNormal;
224 struct ar5416IniArray iniCckfirJapan2484;