package/mac80211/patches/563-ath9k_reg_write_array_func.patch

   1 --- a/drivers/net/wireless/ath/ath9k/hw.c
   2 +++ b/drivers/net/wireless/ath/ath9k/hw.c
   3 @@ -131,6 +131,20 @@ bool ath9k_hw_wait(struct ath_hw *ah, u3
   4  }
   5  EXPORT_SYMBOL(ath9k_hw_wait);
   6
   7 +void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
   8 +                         int column, unsigned int *writecnt)
   9 +{
  10 +       int r;
  11 +
  12 +       ENABLE_REGWRITE_BUFFER(ah);
  13 +       for (r = 0; r < array->ia_rows; r++) {
  14 +               REG_WRITE(ah, INI_RA(array, r, 0),
  15 +                         INI_RA(array, r, column));
  16 +               DO_DELAY(*writecnt);
  17 +       }
  18 +       REGWRITE_BUFFER_FLUSH(ah);
  19 +}
  20 +
  21  u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  22  {
  23         u32 retval;
  24 --- a/drivers/net/wireless/ath/ath9k/hw.h
  25 +++ b/drivers/net/wireless/ath/ath9k/hw.h
  26 @@ -106,16 +106,8 @@
  27                         udelay(1);                              \
  28         } while (0)
  29
  30 -#define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
  31 -               int r;                                                  \
  32 -               ENABLE_REGWRITE_BUFFER(ah);                             \
  33 -               for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  34 -                       REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
  35 -                                 INI_RA((iniarray), r, (column)));     \
  36 -                       DO_DELAY(regWr);                                \
  37 -               }                                                       \
  38 -               REGWRITE_BUFFER_FLUSH(ah);                              \
  39 -       } while (0)
  40 +#define REG_WRITE_ARRAY(iniarray, column, regWr) \
  41 +       ath9k_hw_write_array(ah, iniarray, column, &(regWr))
  42
  43  #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
  44  #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
  45 @@ -915,6 +907,8 @@ void ath9k_hw_antdiv_comb_conf_set(struc
  46
  47  /* General Operation */
  48  bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
  49 +void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
  50 +                         int column, unsigned int *writecnt);
  51  u32 ath9k_hw_reverse_bits(u32 val, u32 n);
  52  bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
  53  u16 ath9k_hw_computetxtime(struct ath_hw *ah,
  54 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
  55 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
  56 @@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
  57  static const int m2ThreshExt_off = 127;
  58
  59
  60 +static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
  61 +                                int col)
  62 +{
  63 +       int i;
  64 +
  65 +       for (i = 0; i < array->ia_rows; i++)
  66 +               bank[i] = INI_RA(array, i, col);
  67 +}
  68 +
  69 +
  70 +#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
  71 +       ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
  72 +
  73 +static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
  74 +                                 u32 *data, unsigned int *writecnt)
  75 +{
  76 +       int r;
  77 +
  78 +       ENABLE_REGWRITE_BUFFER(ah);
  79 +
  80 +       for (r = 0; r < array->ia_rows; r++) {
  81 +               REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
  82 +               DO_DELAY(*writecnt);
  83 +       }
  84 +
  85 +       REGWRITE_BUFFER_FLUSH(ah);
  86 +}
  87 +
  88  /**
  89   * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  90   * @rfbuf:
  91 @@ -530,16 +558,16 @@ static bool ar5008_hw_set_rf_regs(struct
  92         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
  93
  94         /* Setup Bank 0 Write */
  95 -       RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
  96 +       ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
  97
  98         /* Setup Bank 1 Write */
  99 -       RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 100 +       ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
 101
 102         /* Setup Bank 2 Write */
 103 -       RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 104 +       ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
 105
 106         /* Setup Bank 6 Write */
 107 -       RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 108 +       ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
 109                       modesIndex);
 110         {
 111                 int i;
 112 @@ -569,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct
 113         }
 114
 115         /* Setup Bank 7 Setup */
 116 -       RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 117 +       ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
 118
 119         /* Write Analog registers */
 120         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 121 --- a/drivers/net/wireless/ath/ath9k/phy.h
 122 +++ b/drivers/net/wireless/ath/ath9k/phy.h
 123 @@ -38,27 +38,11 @@
 124  #define AR_PHY_CLC_Q0        0x0000ffd0
 125  #define AR_PHY_CLC_Q0_S      5
 126
 127 -#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
 128 -               int r;                                                  \
 129 -               ENABLE_REGWRITE_BUFFER(ah);                             \
 130 -               for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
 131 -                       REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
 132 -                       DO_DELAY(regWr);                                \
 133 -               }                                                       \
 134 -               REGWRITE_BUFFER_FLUSH(ah);                              \
 135 -       } while (0)
 136 -
 137  #define ANTSWAP_AB 0x0001
 138  #define REDUCE_CHAIN_0 0x00000050
 139  #define REDUCE_CHAIN_1 0x00000051
 140  #define AR_PHY_CHIP_ID 0x9818
 141
 142 -#define RF_BANK_SETUP(_bank, _iniarray, _col) do {                     \
 143 -               int i;                                                  \
 144 -               for (i = 0; i < (_iniarray)->ia_rows; i++)              \
 145 -                       (_bank)[i] = INI_RA((_iniarray), i, _col);;     \
 146 -       } while (0)
 147 -
 148  #define        AR_PHY_TIMING11_SPUR_FREQ_SD            0x3FF00000
 149  #define        AR_PHY_TIMING11_SPUR_FREQ_SD_S          20
 150