package/mac80211/patches/308-rt2x00-DMA-fixes-new-chipset-support-rt2800pci.patch

   1 From bfa282e0f525b074ec9a21372ab906156ce0aa20 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Mon, 16 Mar 2009 20:16:59 +0100
   4 Subject: [PATCH] rt2x00: DMA fixes & new chipset support (rt2800pci)
   5
   6 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
   7 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
   8 ---
   9  drivers/net/wireless/rt2x00/rt2800pci.c |  320 +++++++++++++++++++++++++++++--
  10  drivers/net/wireless/rt2x00/rt2800pci.h |   57 ++++++-
  11  2 files changed, 361 insertions(+), 16 deletions(-)
  12
  13 --- a/drivers/net/wireless/rt2x00/rt2800pci.c
  14 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  15 @@ -66,6 +66,8 @@ MODULE_PARM_DESC(nohwcrypt, "Disable har
  16   */
  17  #define WAIT_FOR_BBP(__dev, __reg) \
  18         rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  19 +#define WAIT_FOR_RFCSR(__dev, __reg) \
  20 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  21  #define WAIT_FOR_RF(__dev, __reg) \
  22         rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  23  #define WAIT_FOR_MCU(__dev, __reg) \
  24 @@ -129,6 +131,61 @@ static void rt2800pci_bbp_read(struct rt
  25         mutex_unlock(&rt2x00dev->csr_mutex);
  26  }
  27
  28 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  29 +                                 const unsigned int word, const u8 value)
  30 +{
  31 +       u32 reg;
  32 +
  33 +       mutex_lock(&rt2x00dev->csr_mutex);
  34 +
  35 +       /*
  36 +        * Wait until the RFCSR becomes available, afterwards we
  37 +        * can safely write the new data into the register.
  38 +        */
  39 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  40 +               reg = 0;
  41 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  42 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  43 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  44 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  45 +
  46 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
  47 +       }
  48 +
  49 +       mutex_unlock(&rt2x00dev->csr_mutex);
  50 +}
  51 +
  52 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  53 +                                const unsigned int word, u8 *value)
  54 +{
  55 +       u32 reg;
  56 +
  57 +       mutex_lock(&rt2x00dev->csr_mutex);
  58 +
  59 +       /*
  60 +        * Wait until the RFCSR becomes available, afterwards we
  61 +        * can safely write the read request into the register.
  62 +        * After the data has been written, we wait until hardware
  63 +        * returns the correct value, if at any time the register
  64 +        * doesn't become available in time, reg will be 0xffffffff
  65 +        * which means we return 0xff to the caller.
  66 +        */
  67 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  68 +               reg = 0;
  69 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  70 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  71 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  72 +
  73 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
  74 +
  75 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
  76 +       }
  77 +
  78 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  79 +
  80 +       mutex_unlock(&rt2x00dev->csr_mutex);
  81 +}
  82 +
  83  static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
  84                                const unsigned int word, const u32 value)
  85  {
  86 @@ -160,6 +217,13 @@ static void rt2800pci_mcu_request(struct
  87  {
  88         u32 reg;
  89
  90 +       /*
  91 +        * RT2880 and RT3052 don't support MCU requests.
  92 +        */
  93 +       if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
  94 +           rt2x00_rt(&rt2x00dev->chip, RT3052))
  95 +               return;
  96 +
  97         mutex_lock(&rt2x00dev->csr_mutex);
  98
  99         /*
 100 @@ -729,13 +793,11 @@ static void rt2800pci_config_lna_gain(st
 101         rt2x00dev->lna_gain = lna_gain;
 102  }
 103
 104 -static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 105 -                                    struct ieee80211_conf *conf,
 106 -                                    struct rf_channel *rf,
 107 -                                    struct channel_info *info)
 108 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 109 +                                         struct ieee80211_conf *conf,
 110 +                                         struct rf_channel *rf,
 111 +                                         struct channel_info *info)
 112  {
 113 -       u32 reg;
 114 -       unsigned int tx_pin;
 115         u16 eeprom;
 116
 117         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 118 @@ -745,9 +807,8 @@ static void rt2800pci_config_channel(str
 119          */
 120         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 121
 122 -       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
 123 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
 124                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 125 -       }
 126
 127         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 128                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 129 @@ -806,6 +867,62 @@ static void rt2800pci_config_channel(str
 130         rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 131         rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 132         rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 133 +}
 134 +
 135 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 136 +                                         struct ieee80211_conf *conf,
 137 +                                         struct rf_channel *rf,
 138 +                                         struct channel_info *info)
 139 +{
 140 +       u8 rfcsr;
 141 +
 142 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
 143 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
 144 +
 145 +       rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
 146 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 147 +       rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
 148 +
 149 +       rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
 150 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 151 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 152 +       rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
 153 +
 154 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 155 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 156 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 157 +
 158 +       if (conf_is_ht40(conf))
 159 +               rt2800pci_rfcsr_write(rt2x00dev, 24,
 160 +                                     rt2x00dev->calibration_bw40);
 161 +       else
 162 +               rt2800pci_rfcsr_write(rt2x00dev, 24,
 163 +                                     rt2x00dev->calibration_bw20);
 164 +
 165 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 166 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 167 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 168 +}
 169 +
 170 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 171 +                                    struct ieee80211_conf *conf,
 172 +                                    struct rf_channel *rf,
 173 +                                    struct channel_info *info)
 174 +{
 175 +       u32 reg;
 176 +       unsigned int tx_pin;
 177 +       u16 eeprom;
 178 +       u8 bbp;
 179 +
 180 +       /*
 181 +        * Determine antenna settings from EEPROM
 182 +        */
 183 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 184 +
 185 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 186 +               rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
 187 +       else
 188 +               rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
 189
 190         /*
 191          * Change BBP settings
 192 @@ -861,6 +978,26 @@ static void rt2800pci_config_channel(str
 193
 194         rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 195
 196 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
 197 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 198 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
 199 +
 200 +       rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
 201 +       rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 202 +       rt2800pci_bbp_write(rt2x00dev, 3, bbp);
 203 +
 204 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 205 +               if (conf_is_ht40(conf)) {
 206 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
 207 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
 208 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
 209 +               } else {
 210 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
 211 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
 212 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
 213 +               }
 214 +       }
 215 +
 216         msleep(1);
 217  }
 218
 219 @@ -1265,7 +1402,7 @@ static int rt2800pci_init_queues(struct
 220         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 221         rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 222         rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 223 -       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
 224 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 225         rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
 226
 227         /*
 228 @@ -1613,7 +1750,7 @@ static int rt2800pci_init_bbp(struct rt2
 229         rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
 230         rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
 231         rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
 232 -       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
 233 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x01);
 234
 235         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 236                 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
 237 @@ -1623,6 +1760,12 @@ static int rt2800pci_init_bbp(struct rt2
 238         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
 239                 rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
 240
 241 +       if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
 242 +               rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
 243 +               rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
 244 +               rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
 245 +       }
 246 +
 247         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 248                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 249
 250 @@ -1636,6 +1779,144 @@ static int rt2800pci_init_bbp(struct rt2
 251         return 0;
 252  }
 253
 254 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
 255 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
 256 +{
 257 +       unsigned int i;
 258 +       u8 bbp;
 259 +       u8 rfcsr;
 260 +       u8 passband;
 261 +       u8 stopband;
 262 +       u8 overtuned = 0;
 263 +
 264 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
 265 +
 266 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
 267 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
 268 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
 269 +
 270 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
 271 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
 272 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
 273 +
 274 +       /*
 275 +        * Set power & frequency of passband test tone
 276 +        */
 277 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
 278 +
 279 +       for (i = 0; i < 100; i++) {
 280 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
 281 +               msleep(1);
 282 +
 283 +               rt2800pci_bbp_read(rt2x00dev, 55, &passband);
 284 +               if (passband)
 285 +                       break;
 286 +       }
 287 +
 288 +       /*
 289 +        * Set power & frequency of stopband test tone
 290 +        */
 291 +       rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
 292 +
 293 +       for (i = 0; i < 100; i++) {
 294 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
 295 +               msleep(1);
 296 +
 297 +               rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
 298 +
 299 +               if ((passband - stopband) <= filter_target) {
 300 +                       rfcsr24++;
 301 +                       overtuned += ((passband - stopband) == filter_target);
 302 +               } else
 303 +                       break;
 304 +
 305 +               rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
 306 +       }
 307 +
 308 +       rfcsr24 -= !!overtuned;
 309 +
 310 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
 311 +       return rfcsr24;
 312 +}
 313 +
 314 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
 315 +{
 316 +       u8 rfcsr;
 317 +       u8 bbp;
 318 +
 319 +       if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
 320 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
 321 +           !rt2x00_rf(&rt2x00dev->chip, RF3022))
 322 +               return 0;
 323 +
 324 +       /*
 325 +        * Init RF calibration.
 326 +        */
 327 +       rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
 328 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
 329 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
 330 +       msleep(1);
 331 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
 332 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
 333 +
 334 +       rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
 335 +       rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
 336 +       rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
 337 +       rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
 338 +       rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
 339 +       rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
 340 +       rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
 341 +       rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
 342 +       rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
 343 +       rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
 344 +       rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
 345 +       rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
 346 +       rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
 347 +       rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
 348 +       rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
 349 +       rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
 350 +       rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
 351 +       rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
 352 +       rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
 353 +       rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
 354 +       rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
 355 +       rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
 356 +       rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
 357 +       rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
 358 +       rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
 359 +       rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
 360 +       rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
 361 +       rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
 362 +       rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
 363 +       rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
 364 +
 365 +       /*
 366 +        * Set RX Filter calibration for 20MHz and 40MHz
 367 +        */
 368 +       rt2x00dev->calibration_bw20 =
 369 +           rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
 370 +       rt2x00dev->calibration_bw40 =
 371 +           rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
 372 +
 373 +       /*
 374 +        * Set back to initial state
 375 +        */
 376 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
 377 +
 378 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
 379 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
 380 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
 381 +
 382 +       /*
 383 +        * set BBP back to BW20
 384 +        */
 385 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
 386 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
 387 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
 388 +
 389 +       return 0;
 390 +}
 391 +
 392  /*
 393   * Device state switch handlers.
 394   */
 395 @@ -1718,7 +1999,8 @@ static int rt2800pci_enable_radio(struct
 396                      rt2800pci_init_queues(rt2x00dev) ||
 397                      rt2800pci_init_registers(rt2x00dev) ||
 398                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
 399 -                    rt2800pci_init_bbp(rt2x00dev)))
 400 +                    rt2800pci_init_bbp(rt2x00dev) ||
 401 +                    rt2800pci_init_rfcsr(rt2x00dev)))
 402                 return -EIO;
 403
 404         /*
 405 @@ -2114,6 +2396,12 @@ static void rt2800pci_fill_rxdone(struct
 406         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 407
 408         /*
 409 +        * Set RX IDX in register to inform hardware that we have handled
 410 +        * this entry and it is available for reuse again.
 411 +        */
 412 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 413 +
 414 +       /*
 415          * Remove TXWI descriptor from start of buffer.
 416          */
 417         skb_pull(entry->skb, RXWI_DESC_SIZE);
 418 @@ -2380,7 +2668,8 @@ static int rt2800pci_init_eeprom(struct
 419             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
 420             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
 421             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
 422 -           !rt2x00_rf(&rt2x00dev->chip, RF3052)) {
 423 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
 424 +           !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
 425                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
 426                 return -ENODEV;
 427         }
 428 @@ -2528,7 +2817,8 @@ static int rt2800pci_probe_hw_mode(struc
 429
 430         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
 431             rt2x00_rf(&rt2x00dev->chip, RF2720) ||
 432 -           rt2x00_rf(&rt2x00dev->chip, RF3052)) {
 433 +           rt2x00_rf(&rt2x00dev->chip, RF3021) ||
 434 +           rt2x00_rf(&rt2x00dev->chip, RF3022)) {
 435                 spec->num_channels = 14;
 436                 spec->channels = rf_vals;
 437         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
 438 @@ -2624,7 +2914,9 @@ static int rt2800pci_probe_hw(struct rt2
 439         /*
 440          * This device requires firmware.
 441          */
 442 -       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 443 +       if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
 444 +           !rt2x00_rt(&rt2x00dev->chip, RT3052))
 445 +               __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 446         if (!modparam_nohwcrypt)
 447                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 448
 449 --- a/drivers/net/wireless/rt2x00/rt2800pci.h
 450 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
 451 @@ -36,7 +36,8 @@
 452   * RF2750 2.4G/5G 1T2R
 453   * RF3020 2.4G 1T1R
 454   * RF2020 2.4G B/G
 455 - * RF3052 2.4G 2T2R
 456 + * RF3021 2.4G 1T2R
 457 + * RF3022 2.4G 2T2R
 458   */
 459  #define RF2820                         0x0001
 460  #define RF2850                         0x0002
 461 @@ -44,7 +45,8 @@
 462  #define RF2750                         0x0004
 463  #define RF3020                         0x0005
 464  #define RF2020                         0x0006
 465 -#define RF3052                         0x0008
 466 +#define RF3021                         0x0007
 467 +#define RF3022                         0x0008
 468
 469  /*
 470   * RT2860 version
 471 @@ -373,6 +375,15 @@
 472  #define PBF_DBG                                0x043c
 473
 474  /*
 475 + * RF registers
 476 + */
 477 +#define        RF_CSR_CFG                      0x0500
 478 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
 479 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
 480 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
 481 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
 482 +
 483 +/*
 484   * MAC Control/Status Registers(CSR).
 485   * Some values are set in TU, whereas 1 TU == 1024 us.
 486   */
 487 @@ -1465,6 +1476,48 @@ struct mac_iveiv_entry {
 488   * BBP 3: RX Antenna
 489   */
 490  #define BBP3_RX_ANTENNA                        FIELD8(0x18)
 491 +#define BBP3_HT40_PLUS                 FIELD8(0x20)
 492 +
 493 +/*
 494 + * BBP 4: Bandwidth
 495 + */
 496 +#define BBP4_TX_BF                     FIELD8(0x01)
 497 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
 498 +
 499 +/*
 500 + * RFCSR registers
 501 + * The wordsize of the RFCSR is 8 bits.
 502 + */
 503 +
 504 +/*
 505 + * RFCSR 6:
 506 + */
 507 +#define RFCSR6_R                       FIELD8(0x03)
 508 +
 509 +/*
 510 + * RFCSR 7:
 511 + */
 512 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
 513 +
 514 +/*
 515 + * RFCSR 12:
 516 + */
 517 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
 518 +
 519 +/*
 520 + * RFCSR 22:
 521 + */
 522 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
 523 +
 524 +/*
 525 + * RFCSR 23:
 526 + */
 527 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
 528 +
 529 +/*
 530 + * RFCSR 30:
 531 + */
 532 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
 533
 534  /*
 535   * RF registers