package/mac80211/patches/302-rt2x00-Implement-support-for-rt2800pci.patch

   1 From 8dff6729a634d7cf223679d9a29a3df77927540c Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Sat, 8 Aug 2009 23:47:53 +0200
   4 Subject: [PATCH 2/3] rt2x00: Implement support for rt2800pci
   5
   6 Add support for the rt2800pci chipset.
   7
   8 Includes various patches from Luis, Mattias, Mark, Felix and Xose.
   9
  10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
  11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
  13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  14 Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
  15 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  16 ---
  17  drivers/net/wireless/rt2x00/Kconfig     |   26 +
  18  drivers/net/wireless/rt2x00/Makefile    |    1 +
  19  drivers/net/wireless/rt2x00/rt2800pci.c | 3243 +++++++++++++++++++++++++++++++
  20  drivers/net/wireless/rt2x00/rt2800pci.h | 1929 ++++++++++++++++++
  21  drivers/net/wireless/rt2x00/rt2x00.h    |    6 +
  22  5 files changed, 5205 insertions(+), 0 deletions(-)
  23  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
  24  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
  25
  26 --- a/drivers/net/wireless/rt2x00/Makefile
  27 +++ b/drivers/net/wireless/rt2x00/Makefile
  28 @@ -16,6 +16,7 @@ obj-$(CONFIG_RT2X00_LIB_USB)          += rt2x00u
  29  obj-$(CONFIG_RT2400PCI)                        += rt2400pci.o
  30  obj-$(CONFIG_RT2500PCI)                        += rt2500pci.o
  31  obj-$(CONFIG_RT61PCI)                  += rt61pci.o
  32 +obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  33  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  34  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  35  obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  36 --- /dev/null
  37 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  38 @@ -0,0 +1,3240 @@
  39 +/*
  40 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  41 +       <http://rt2x00.serialmonkey.com>
  42 +
  43 +       This program is free software; you can redistribute it and/or modify
  44 +       it under the terms of the GNU General Public License as published by
  45 +       the Free Software Foundation; either version 2 of the License, or
  46 +       (at your option) any later version.
  47 +
  48 +       This program is distributed in the hope that it will be useful,
  49 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  50 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  51 +       GNU General Public License for more details.
  52 +
  53 +       You should have received a copy of the GNU General Public License
  54 +       along with this program; if not, write to the
  55 +       Free Software Foundation, Inc.,
  56 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  57 + */
  58 +
  59 +/*
  60 +       Module: rt2800pci
  61 +       Abstract: rt2800pci device specific routines.
  62 +       Supported chipsets: RT2800E & RT2800ED.
  63 + */
  64 +
  65 +#include <linux/crc-ccitt.h>
  66 +#include <linux/delay.h>
  67 +#include <linux/etherdevice.h>
  68 +#include <linux/init.h>
  69 +#include <linux/kernel.h>
  70 +#include <linux/module.h>
  71 +#include <linux/pci.h>
  72 +#include <linux/platform_device.h>
  73 +#include <linux/eeprom_93cx6.h>
  74 +
  75 +#include "rt2x00.h"
  76 +#include "rt2x00pci.h"
  77 +#include "rt2x00soc.h"
  78 +#include "rt2800pci.h"
  79 +
  80 +#ifdef CONFIG_RT2800PCI_PCI_MODULE
  81 +#define CONFIG_RT2800PCI_PCI
  82 +#endif
  83 +
  84 +#ifdef CONFIG_RT2800PCI_WISOC_MODULE
  85 +#define CONFIG_RT2800PCI_WISOC
  86 +#endif
  87 +
  88 +/*
  89 + * Allow hardware encryption to be disabled.
  90 + */
  91 +static int modparam_nohwcrypt = 0;
  92 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  93 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  94 +
  95 +/*
  96 + * Register access.
  97 + * BBP and RF register require indirect register access,
  98 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  99 + * These indirect registers work with busy bits,
 100 + * and we will try maximal REGISTER_BUSY_COUNT times to access
 101 + * the register while taking a REGISTER_BUSY_DELAY us delay
 102 + * between each attampt. When the busy bit is still set at that time,
 103 + * the access attempt is considered to have failed,
 104 + * and we will print an error.
 105 + */
 106 +#define WAIT_FOR_BBP(__dev, __reg) \
 107 +       rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
 108 +#define WAIT_FOR_RFCSR(__dev, __reg) \
 109 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
 110 +#define WAIT_FOR_RF(__dev, __reg) \
 111 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 112 +#define WAIT_FOR_MCU(__dev, __reg) \
 113 +       rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
 114 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 115 +
 116 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
 117 +                               const unsigned int word, const u8 value)
 118 +{
 119 +       u32 reg;
 120 +
 121 +       mutex_lock(&rt2x00dev->csr_mutex);
 122 +
 123 +       /*
 124 +        * Wait until the BBP becomes available, afterwards we
 125 +        * can safely write the new data into the register.
 126 +        */
 127 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128 +               reg = 0;
 129 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 130 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 131 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 132 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 133 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 134 +
 135 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 136 +       }
 137 +
 138 +       mutex_unlock(&rt2x00dev->csr_mutex);
 139 +}
 140 +
 141 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 142 +                              const unsigned int word, u8 *value)
 143 +{
 144 +       u32 reg;
 145 +
 146 +       mutex_lock(&rt2x00dev->csr_mutex);
 147 +
 148 +       /*
 149 +        * Wait until the BBP becomes available, afterwards we
 150 +        * can safely write the read request into the register.
 151 +        * After the data has been written, we wait until hardware
 152 +        * returns the correct value, if at any time the register
 153 +        * doesn't become available in time, reg will be 0xffffffff
 154 +        * which means we return 0xff to the caller.
 155 +        */
 156 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 157 +               reg = 0;
 158 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 159 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 160 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 161 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 162 +
 163 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 164 +
 165 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 166 +       }
 167 +
 168 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 169 +
 170 +       mutex_unlock(&rt2x00dev->csr_mutex);
 171 +}
 172 +
 173 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 174 +                                 const unsigned int word, const u8 value)
 175 +{
 176 +       u32 reg;
 177 +
 178 +       mutex_lock(&rt2x00dev->csr_mutex);
 179 +
 180 +       /*
 181 +        * Wait until the RFCSR becomes available, afterwards we
 182 +        * can safely write the new data into the register.
 183 +        */
 184 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 185 +               reg = 0;
 186 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 187 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 188 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 189 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 190 +
 191 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
 192 +       }
 193 +
 194 +       mutex_unlock(&rt2x00dev->csr_mutex);
 195 +}
 196 +
 197 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 198 +                                const unsigned int word, u8 *value)
 199 +{
 200 +       u32 reg;
 201 +
 202 +       mutex_lock(&rt2x00dev->csr_mutex);
 203 +
 204 +       /*
 205 +        * Wait until the RFCSR becomes available, afterwards we
 206 +        * can safely write the read request into the register.
 207 +        * After the data has been written, we wait until hardware
 208 +        * returns the correct value, if at any time the register
 209 +        * doesn't become available in time, reg will be 0xffffffff
 210 +        * which means we return 0xff to the caller.
 211 +        */
 212 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 213 +               reg = 0;
 214 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 215 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 216 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 217 +
 218 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
 219 +
 220 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 221 +       }
 222 +
 223 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 224 +
 225 +       mutex_unlock(&rt2x00dev->csr_mutex);
 226 +}
 227 +
 228 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 229 +                              const unsigned int word, const u32 value)
 230 +{
 231 +       u32 reg;
 232 +
 233 +       mutex_lock(&rt2x00dev->csr_mutex);
 234 +
 235 +       /*
 236 +        * Wait until the RF becomes available, afterwards we
 237 +        * can safely write the new data into the register.
 238 +        */
 239 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 240 +               reg = 0;
 241 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 242 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 243 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 244 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 245 +
 246 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
 247 +               rt2x00_rf_write(rt2x00dev, word, value);
 248 +       }
 249 +
 250 +       mutex_unlock(&rt2x00dev->csr_mutex);
 251 +}
 252 +
 253 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 254 +                                 const u8 command, const u8 token,
 255 +                                 const u8 arg0, const u8 arg1)
 256 +{
 257 +       u32 reg;
 258 +
 259 +       /*
 260 +        * RT2880 and RT3052 don't support MCU requests.
 261 +        */
 262 +       if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
 263 +           rt2x00_rt(&rt2x00dev->chip, RT3052))
 264 +               return;
 265 +
 266 +       mutex_lock(&rt2x00dev->csr_mutex);
 267 +
 268 +       /*
 269 +        * Wait until the MCU becomes available, afterwards we
 270 +        * can safely write the new data into the register.
 271 +        */
 272 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 273 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 274 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 275 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 276 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 277 +               rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 278 +
 279 +               reg = 0;
 280 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 281 +               rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 282 +       }
 283 +
 284 +       mutex_unlock(&rt2x00dev->csr_mutex);
 285 +}
 286 +
 287 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
 288 +{
 289 +       unsigned int i;
 290 +       u32 reg;
 291 +
 292 +       for (i = 0; i < 200; i++) {
 293 +               rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
 294 +
 295 +               if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
 296 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
 297 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
 298 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
 299 +                       break;
 300 +
 301 +               udelay(REGISTER_BUSY_DELAY);
 302 +       }
 303 +
 304 +       if (i == 200)
 305 +               ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
 306 +
 307 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 308 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 309 +}
 310 +
 311 +#ifdef CONFIG_RT2800PCI_WISOC
 312 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 313 +{
 314 +       u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
 315 +
 316 +       memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
 317 +}
 318 +#else
 319 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 320 +{
 321 +}
 322 +#endif /* CONFIG_RT2800PCI_WISOC */
 323 +
 324 +#ifdef CONFIG_RT2800PCI_PCI
 325 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 326 +{
 327 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 328 +       u32 reg;
 329 +
 330 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 331 +
 332 +       eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 333 +       eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 334 +       eeprom->reg_data_clock =
 335 +           !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 336 +       eeprom->reg_chip_select =
 337 +           !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 338 +}
 339 +
 340 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 341 +{
 342 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 343 +       u32 reg = 0;
 344 +
 345 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 346 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 347 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 348 +                          !!eeprom->reg_data_clock);
 349 +       rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 350 +                          !!eeprom->reg_chip_select);
 351 +
 352 +       rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 353 +}
 354 +
 355 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 356 +{
 357 +       struct eeprom_93cx6 eeprom;
 358 +       u32 reg;
 359 +
 360 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 361 +
 362 +       eeprom.data = rt2x00dev;
 363 +       eeprom.register_read = rt2800pci_eepromregister_read;
 364 +       eeprom.register_write = rt2800pci_eepromregister_write;
 365 +       eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 366 +           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 367 +       eeprom.reg_data_in = 0;
 368 +       eeprom.reg_data_out = 0;
 369 +       eeprom.reg_data_clock = 0;
 370 +       eeprom.reg_chip_select = 0;
 371 +
 372 +       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 373 +                              EEPROM_SIZE / sizeof(u16));
 374 +}
 375 +#else
 376 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 377 +{
 378 +}
 379 +#endif /* CONFIG_RT2800PCI_PCI */
 380 +
 381 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 382 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
 383 +       .owner  = THIS_MODULE,
 384 +       .csr    = {
 385 +               .read           = rt2x00pci_register_read,
 386 +               .write          = rt2x00pci_register_write,
 387 +               .flags          = RT2X00DEBUGFS_OFFSET,
 388 +               .word_base      = CSR_REG_BASE,
 389 +               .word_size      = sizeof(u32),
 390 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 391 +       },
 392 +       .eeprom = {
 393 +               .read           = rt2x00_eeprom_read,
 394 +               .write          = rt2x00_eeprom_write,
 395 +               .word_base      = EEPROM_BASE,
 396 +               .word_size      = sizeof(u16),
 397 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 398 +       },
 399 +       .bbp    = {
 400 +               .read           = rt2800pci_bbp_read,
 401 +               .write          = rt2800pci_bbp_write,
 402 +               .word_base      = BBP_BASE,
 403 +               .word_size      = sizeof(u8),
 404 +               .word_count     = BBP_SIZE / sizeof(u8),
 405 +       },
 406 +       .rf     = {
 407 +               .read           = rt2x00_rf_read,
 408 +               .write          = rt2800pci_rf_write,
 409 +               .word_base      = RF_BASE,
 410 +               .word_size      = sizeof(u32),
 411 +               .word_count     = RF_SIZE / sizeof(u32),
 412 +       },
 413 +};
 414 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 415 +
 416 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 417 +{
 418 +       u32 reg;
 419 +
 420 +       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 421 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 422 +}
 423 +
 424 +#ifdef CONFIG_RT2X00_LIB_LEDS
 425 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 426 +                                    enum led_brightness brightness)
 427 +{
 428 +       struct rt2x00_led *led =
 429 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 430 +       unsigned int enabled = brightness != LED_OFF;
 431 +       unsigned int bg_mode =
 432 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 433 +       unsigned int polarity =
 434 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 435 +                                  EEPROM_FREQ_LED_POLARITY);
 436 +       unsigned int ledmode =
 437 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 438 +                                  EEPROM_FREQ_LED_MODE);
 439 +
 440 +       if (led->type == LED_TYPE_RADIO) {
 441 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 442 +                                     enabled ? 0x20 : 0);
 443 +       } else if (led->type == LED_TYPE_ASSOC) {
 444 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 445 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 446 +       } else if (led->type == LED_TYPE_QUALITY) {
 447 +               /*
 448 +                * The brightness is divided into 6 levels (0 - 5),
 449 +                * The specs tell us the following levels:
 450 +                *      0, 1 ,3, 7, 15, 31
 451 +                * to determine the level in a simple way we can simply
 452 +                * work with bitshifting:
 453 +                *      (1 << level) - 1
 454 +                */
 455 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 456 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 457 +                                     polarity);
 458 +       }
 459 +}
 460 +
 461 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 462 +                              unsigned long *delay_on,
 463 +                              unsigned long *delay_off)
 464 +{
 465 +       struct rt2x00_led *led =
 466 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 467 +       u32 reg;
 468 +
 469 +       rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
 470 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 471 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 472 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 473 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 474 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 475 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 476 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 477 +       rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
 478 +
 479 +       return 0;
 480 +}
 481 +
 482 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 483 +                              struct rt2x00_led *led,
 484 +                              enum led_type type)
 485 +{
 486 +       led->rt2x00dev = rt2x00dev;
 487 +       led->type = type;
 488 +       led->led_dev.brightness_set = rt2800pci_brightness_set;
 489 +       led->led_dev.blink_set = rt2800pci_blink_set;
 490 +       led->flags = LED_INITIALIZED;
 491 +}
 492 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 493 +
 494 +/*
 495 + * Configuration handlers.
 496 + */
 497 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 498 +                                      struct rt2x00lib_crypto *crypto,
 499 +                                      struct ieee80211_key_conf *key)
 500 +{
 501 +       struct mac_wcid_entry wcid_entry;
 502 +       struct mac_iveiv_entry iveiv_entry;
 503 +       u32 offset;
 504 +       u32 reg;
 505 +
 506 +       offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 507 +
 508 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 509 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 510 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 511 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 512 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 513 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 514 +                          (crypto->cmd == SET_KEY) * crypto->bssidx);
 515 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 516 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 517 +
 518 +       offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 519 +
 520 +       memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 521 +       if ((crypto->cipher == CIPHER_TKIP) ||
 522 +           (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 523 +           (crypto->cipher == CIPHER_AES))
 524 +               iveiv_entry.iv[3] |= 0x20;
 525 +       iveiv_entry.iv[3] |= key->keyidx << 6;
 526 +       rt2x00pci_register_multiwrite(rt2x00dev, offset,
 527 +                                     &iveiv_entry, sizeof(iveiv_entry));
 528 +
 529 +       offset = MAC_WCID_ENTRY(key->hw_key_idx);
 530 +
 531 +       memset(&wcid_entry, 0, sizeof(wcid_entry));
 532 +       if (crypto->cmd == SET_KEY)
 533 +               memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 534 +       rt2x00pci_register_multiwrite(rt2x00dev, offset,
 535 +                                     &wcid_entry, sizeof(wcid_entry));
 536 +}
 537 +
 538 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 539 +                                      struct rt2x00lib_crypto *crypto,
 540 +                                      struct ieee80211_key_conf *key)
 541 +{
 542 +       struct hw_key_entry key_entry;
 543 +       struct rt2x00_field32 field;
 544 +       u32 offset;
 545 +       u32 reg;
 546 +
 547 +       if (crypto->cmd == SET_KEY) {
 548 +               key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 549 +
 550 +               memcpy(key_entry.key, crypto->key,
 551 +                      sizeof(key_entry.key));
 552 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 553 +                      sizeof(key_entry.tx_mic));
 554 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 555 +                      sizeof(key_entry.rx_mic));
 556 +
 557 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 558 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 559 +                                             &key_entry, sizeof(key_entry));
 560 +       }
 561 +
 562 +       /*
 563 +        * The cipher types are stored over multiple registers
 564 +        * starting with SHARED_KEY_MODE_BASE each word will have
 565 +        * 32 bits and contains the cipher types for 2 bssidx each.
 566 +        * Using the correct defines correctly will cause overhead,
 567 +        * so just calculate the correct offset.
 568 +        */
 569 +       field.bit_offset = 4 * (key->hw_key_idx % 8);
 570 +       field.bit_mask = 0x7 << field.bit_offset;
 571 +
 572 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 573 +
 574 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 575 +       rt2x00_set_field32(&reg, field,
 576 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 577 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 578 +
 579 +       /*
 580 +        * Update WCID information
 581 +        */
 582 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 583 +
 584 +       return 0;
 585 +}
 586 +
 587 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 588 +                                        struct rt2x00lib_crypto *crypto,
 589 +                                        struct ieee80211_key_conf *key)
 590 +{
 591 +       struct hw_key_entry key_entry;
 592 +       u32 offset;
 593 +
 594 +       if (crypto->cmd == SET_KEY) {
 595 +               /*
 596 +                * 1 pairwise key is possible per AID, this means that the AID
 597 +                * equals our hw_key_idx. Make sure the WCID starts _after_ the
 598 +                * last possible shared key entry.
 599 +                */
 600 +               if (crypto->aid > (256 - 32))
 601 +                       return -ENOSPC;
 602 +
 603 +               key->hw_key_idx = 32 + crypto->aid;
 604 +
 605 +
 606 +               memcpy(key_entry.key, crypto->key,
 607 +                      sizeof(key_entry.key));
 608 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 609 +                      sizeof(key_entry.tx_mic));
 610 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 611 +                      sizeof(key_entry.rx_mic));
 612 +
 613 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 614 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 615 +                                             &key_entry, sizeof(key_entry));
 616 +       }
 617 +
 618 +       /*
 619 +        * Update WCID information
 620 +        */
 621 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 622 +
 623 +       return 0;
 624 +}
 625 +
 626 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 627 +                                   const unsigned int filter_flags)
 628 +{
 629 +       u32 reg;
 630 +
 631 +       /*
 632 +        * Start configuration steps.
 633 +        * Note that the version error will always be dropped
 634 +        * and broadcast frames will always be accepted since
 635 +        * there is no filter for it at this time.
 636 +        */
 637 +       rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 638 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 639 +                          !(filter_flags & FIF_FCSFAIL));
 640 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 641 +                          !(filter_flags & FIF_PLCPFAIL));
 642 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 643 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 644 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 645 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 646 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 647 +                          !(filter_flags & FIF_ALLMULTI));
 648 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 649 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 650 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 651 +                          !(filter_flags & FIF_CONTROL));
 652 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 653 +                          !(filter_flags & FIF_CONTROL));
 654 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 655 +                          !(filter_flags & FIF_CONTROL));
 656 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 657 +                          !(filter_flags & FIF_CONTROL));
 658 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 659 +                          !(filter_flags & FIF_CONTROL));
 660 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 661 +                          !(filter_flags & FIF_PSPOLL));
 662 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 663 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 664 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 665 +                          !(filter_flags & FIF_CONTROL));
 666 +       rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 667 +}
 668 +
 669 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 670 +                                 struct rt2x00_intf *intf,
 671 +                                 struct rt2x00intf_conf *conf,
 672 +                                 const unsigned int flags)
 673 +{
 674 +       unsigned int beacon_base;
 675 +       u32 reg;
 676 +
 677 +       if (flags & CONFIG_UPDATE_TYPE) {
 678 +               /*
 679 +                * Clear current synchronisation setup.
 680 +                * For the Beacon base registers we only need to clear
 681 +                * the first byte since that byte contains the VALID and OWNER
 682 +                * bits which (when set to 0) will invalidate the entire beacon.
 683 +                */
 684 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 685 +               rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 686 +
 687 +               /*
 688 +                * Enable synchronisation.
 689 +                */
 690 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 691 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 692 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 693 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 694 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 695 +       }
 696 +
 697 +       if (flags & CONFIG_UPDATE_MAC) {
 698 +               reg = le32_to_cpu(conf->mac[1]);
 699 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 700 +               conf->mac[1] = cpu_to_le32(reg);
 701 +
 702 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 703 +                                             conf->mac, sizeof(conf->mac));
 704 +       }
 705 +
 706 +       if (flags & CONFIG_UPDATE_BSSID) {
 707 +               reg = le32_to_cpu(conf->bssid[1]);
 708 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 709 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 710 +               conf->bssid[1] = cpu_to_le32(reg);
 711 +
 712 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 713 +                                             conf->bssid, sizeof(conf->bssid));
 714 +       }
 715 +}
 716 +
 717 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 718 +                                struct rt2x00lib_erp *erp)
 719 +{
 720 +       u32 reg;
 721 +
 722 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 723 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 724 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 725 +
 726 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 727 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 728 +                          !!erp->short_preamble);
 729 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 730 +                          !!erp->short_preamble);
 731 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 732 +
 733 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 734 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 735 +                          erp->cts_protection ? 2 : 0);
 736 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 737 +
 738 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 739 +                                erp->basic_rates);
 740 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 741 +
 742 +       rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 743 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 744 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 745 +       rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 746 +
 747 +       rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 748 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 749 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 750 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 751 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 752 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 753 +       rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 754 +
 755 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 756 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 757 +                          erp->beacon_int * 16);
 758 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 759 +}
 760 +
 761 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 762 +                                struct antenna_setup *ant)
 763 +{
 764 +       u8 r1;
 765 +       u8 r3;
 766 +
 767 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 768 +       rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 769 +
 770 +       /*
 771 +        * Configure the TX antenna.
 772 +        */
 773 +       switch ((int)ant->tx) {
 774 +       case 1:
 775 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 776 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 777 +               break;
 778 +       case 2:
 779 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 780 +               break;
 781 +       case 3:
 782 +               /* Do nothing */
 783 +               break;
 784 +       }
 785 +
 786 +       /*
 787 +        * Configure the RX antenna.
 788 +        */
 789 +       switch ((int)ant->rx) {
 790 +       case 1:
 791 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 792 +               break;
 793 +       case 2:
 794 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 795 +               break;
 796 +       case 3:
 797 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 798 +               break;
 799 +       }
 800 +
 801 +       rt2800pci_bbp_write(rt2x00dev, 3, r3);
 802 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 803 +}
 804 +
 805 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 806 +                                     struct rt2x00lib_conf *libconf)
 807 +{
 808 +       u16 eeprom;
 809 +       short lna_gain;
 810 +
 811 +       if (libconf->rf.channel <= 14) {
 812 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 813 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 814 +       } else if (libconf->rf.channel <= 64) {
 815 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 816 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 817 +       } else if (libconf->rf.channel <= 128) {
 818 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 819 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 820 +       } else {
 821 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 822 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 823 +       }
 824 +
 825 +       rt2x00dev->lna_gain = lna_gain;
 826 +}
 827 +
 828 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 829 +                                         struct ieee80211_conf *conf,
 830 +                                         struct rf_channel *rf,
 831 +                                         struct channel_info *info)
 832 +{
 833 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 834 +
 835 +       if (rt2x00dev->default_ant.tx == 1)
 836 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 837 +
 838 +       if (rt2x00dev->default_ant.rx == 1) {
 839 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 840 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 841 +       } else if (rt2x00dev->default_ant.rx == 2)
 842 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 843 +
 844 +       if (rf->channel > 14) {
 845 +               /*
 846 +                * When TX power is below 0, we should increase it by 7 to
 847 +                * make it a positive value (Minumum value is -7).
 848 +                * However this means that values between 0 and 7 have
 849 +                * double meaning, and we should set a 7DBm boost flag.
 850 +                */
 851 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 852 +                                  (info->tx_power1 >= 0));
 853 +
 854 +               if (info->tx_power1 < 0)
 855 +                       info->tx_power1 += 7;
 856 +
 857 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 858 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 859 +
 860 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 861 +                                  (info->tx_power2 >= 0));
 862 +
 863 +               if (info->tx_power2 < 0)
 864 +                       info->tx_power2 += 7;
 865 +
 866 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 867 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 868 +       } else {
 869 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 870 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 871 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 872 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 873 +       }
 874 +
 875 +       rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 876 +
 877 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 878 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 879 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 880 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 881 +
 882 +       udelay(200);
 883 +
 884 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 885 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 886 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 887 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 888 +
 889 +       udelay(200);
 890 +
 891 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 892 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 893 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 894 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 895 +}
 896 +
 897 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 898 +                                         struct ieee80211_conf *conf,
 899 +                                         struct rf_channel *rf,
 900 +                                         struct channel_info *info)
 901 +{
 902 +       u8 rfcsr;
 903 +
 904 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
 905 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
 906 +
 907 +       rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
 908 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 909 +       rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
 910 +
 911 +       rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
 912 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 913 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 914 +       rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
 915 +
 916 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 917 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 918 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 919 +
 920 +       rt2800pci_rfcsr_write(rt2x00dev, 24,
 921 +                             rt2x00dev->calibration[conf_is_ht40(conf)]);
 922 +
 923 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 924 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 925 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 926 +}
 927 +
 928 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 929 +                                    struct ieee80211_conf *conf,
 930 +                                    struct rf_channel *rf,
 931 +                                    struct channel_info *info)
 932 +{
 933 +       u32 reg;
 934 +       unsigned int tx_pin;
 935 +       u8 bbp;
 936 +
 937 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 938 +               rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
 939 +       else
 940 +               rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
 941 +
 942 +       /*
 943 +        * Change BBP settings
 944 +        */
 945 +       rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 946 +       rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 947 +       rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 948 +       rt2800pci_bbp_write(rt2x00dev, 86, 0);
 949 +
 950 +       if (rf->channel <= 14) {
 951 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 952 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
 953 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 954 +               } else {
 955 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
 956 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 957 +               }
 958 +       } else {
 959 +               rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
 960 +
 961 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 962 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 963 +               else
 964 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 965 +       }
 966 +
 967 +       rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 968 +       rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 969 +       rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 970 +       rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 971 +       rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 972 +
 973 +       tx_pin = 0;
 974 +
 975 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 976 +       if (rt2x00dev->default_ant.tx != 1) {
 977 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 978 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 979 +       }
 980 +
 981 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 982 +       if (rt2x00dev->default_ant.rx != 1) {
 983 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 984 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 985 +       }
 986 +
 987 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 988 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 989 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 990 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 991 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 992 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 993 +
 994 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 995 +
 996 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
 997 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 998 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
 999 +
1000 +       rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1001 +       rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1002 +       rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1003 +
1004 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1005 +               if (conf_is_ht40(conf)) {
1006 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1007 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1008 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1009 +               } else {
1010 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1011 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1012 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1013 +               }
1014 +       }
1015 +
1016 +       msleep(1);
1017 +}
1018 +
1019 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1020 +                                    const int txpower)
1021 +{
1022 +       u32 reg;
1023 +       u32 value = TXPOWER_G_TO_DEV(txpower);
1024 +       u8 r1;
1025 +
1026 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1027 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1028 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
1029 +
1030 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1031 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1032 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1033 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1034 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1035 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1036 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1037 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1038 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1039 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1040 +
1041 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1042 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1043 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1044 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1045 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1046 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1047 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1048 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1049 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1050 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1051 +
1052 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1053 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1054 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1055 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1056 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1057 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1058 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1059 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1060 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1061 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1062 +
1063 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1064 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1065 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1066 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1067 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1068 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1069 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1070 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1071 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1072 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1073 +
1074 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1075 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1076 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1077 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1078 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1079 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1080 +}
1081 +
1082 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1083 +                                        struct rt2x00lib_conf *libconf)
1084 +{
1085 +       u32 reg;
1086 +
1087 +       rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1088 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1089 +                          libconf->conf->short_frame_max_tx_count);
1090 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1091 +                          libconf->conf->long_frame_max_tx_count);
1092 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1093 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1094 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1095 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1096 +       rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1097 +}
1098 +
1099 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1100 +                               struct rt2x00lib_conf *libconf)
1101 +{
1102 +       enum dev_state state =
1103 +           (libconf->conf->flags & IEEE80211_CONF_PS) ?
1104 +               STATE_SLEEP : STATE_AWAKE;
1105 +       u32 reg;
1106 +
1107 +       if (state == STATE_SLEEP) {
1108 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1109 +
1110 +               rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1111 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1112 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1113 +                                  libconf->conf->listen_interval - 1);
1114 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1115 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1116 +
1117 +               rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1118 +       } else {
1119 +               rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1120 +
1121 +               rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1122 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1123 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1124 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1125 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1126 +       }
1127 +}
1128 +
1129 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1130 +                            struct rt2x00lib_conf *libconf,
1131 +                            const unsigned int flags)
1132 +{
1133 +       /* Always recalculate LNA gain before changing configuration */
1134 +       rt2800pci_config_lna_gain(rt2x00dev, libconf);
1135 +
1136 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1137 +               rt2800pci_config_channel(rt2x00dev, libconf->conf,
1138 +                                        &libconf->rf, &libconf->channel);
1139 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1140 +               rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1141 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1142 +               rt2800pci_config_retry_limit(rt2x00dev, libconf);
1143 +       if (flags & IEEE80211_CONF_CHANGE_PS)
1144 +               rt2800pci_config_ps(rt2x00dev, libconf);
1145 +}
1146 +
1147 +/*
1148 + * Link tuning
1149 + */
1150 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1151 +                                struct link_qual *qual)
1152 +{
1153 +       u32 reg;
1154 +
1155 +       /*
1156 +        * Update FCS error count from register.
1157 +        */
1158 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1159 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1160 +}
1161 +
1162 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1163 +{
1164 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1165 +               return 0x2e + rt2x00dev->lna_gain;
1166 +
1167 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1168 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1169 +       else
1170 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1171 +}
1172 +
1173 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1174 +                                    struct link_qual *qual, u8 vgc_level)
1175 +{
1176 +       if (qual->vgc_level != vgc_level) {
1177 +               rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1178 +               qual->vgc_level = vgc_level;
1179 +               qual->vgc_level_reg = vgc_level;
1180 +       }
1181 +}
1182 +
1183 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1184 +                                 struct link_qual *qual)
1185 +{
1186 +       rt2800pci_set_vgc(rt2x00dev, qual,
1187 +                         rt2800pci_get_default_vgc(rt2x00dev));
1188 +}
1189 +
1190 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1191 +                                struct link_qual *qual, const u32 count)
1192 +{
1193 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1194 +               return;
1195 +
1196 +       /*
1197 +        * When RSSI is better then -80 increase VGC level with 0x10
1198 +        */
1199 +       rt2800pci_set_vgc(rt2x00dev, qual,
1200 +                         rt2800pci_get_default_vgc(rt2x00dev) +
1201 +                         ((qual->rssi > -80) * 0x10));
1202 +}
1203 +
1204 +/*
1205 + * Firmware functions
1206 + */
1207 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1208 +{
1209 +       return FIRMWARE_RT2860;
1210 +}
1211 +
1212 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1213 +                                   const u8 *data, const size_t len)
1214 +{
1215 +       u16 fw_crc;
1216 +       u16 crc;
1217 +
1218 +       /*
1219 +        * Only support 8kb firmware files.
1220 +        */
1221 +       if (len != 8192)
1222 +               return FW_BAD_LENGTH;
1223 +
1224 +       /*
1225 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1226 +        * this means that we should never pass those 2 bytes to the crc
1227 +        * algorithm.
1228 +        */
1229 +       fw_crc = (data[len - 2] << 8 | data[len - 1]);
1230 +
1231 +       /*
1232 +        * Use the crc ccitt algorithm.
1233 +        * This will return the same value as the legacy driver which
1234 +        * used bit ordering reversion on the both the firmware bytes
1235 +        * before input input as well as on the final output.
1236 +        * Obviously using crc ccitt directly is much more efficient.
1237 +        */
1238 +       crc = crc_ccitt(~0, data, len - 2);
1239 +
1240 +       /*
1241 +        * There is a small difference between the crc-itu-t + bitrev and
1242 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1243 +        * will be swapped, use swab16 to convert the crc to the correct
1244 +        * value.
1245 +        */
1246 +       crc = swab16(crc);
1247 +
1248 +       return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1249 +}
1250 +
1251 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1252 +                                  const u8 *data, const size_t len)
1253 +{
1254 +       unsigned int i;
1255 +       u32 reg;
1256 +
1257 +       /*
1258 +        * Wait for stable hardware.
1259 +        */
1260 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1261 +               rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1262 +               if (reg && reg != ~0)
1263 +                       break;
1264 +               msleep(1);
1265 +       }
1266 +
1267 +       if (i == REGISTER_BUSY_COUNT) {
1268 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1269 +               return -EBUSY;
1270 +       }
1271 +
1272 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1273 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1274 +
1275 +       /*
1276 +        * Disable DMA, will be reenabled later when enabling
1277 +        * the radio.
1278 +        */
1279 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1280 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1281 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1282 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1283 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1284 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1285 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1286 +
1287 +       /*
1288 +        * enable Host program ram write selection
1289 +        */
1290 +       reg = 0;
1291 +       rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1292 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1293 +
1294 +       /*
1295 +        * Write firmware to device.
1296 +        */
1297 +       rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1298 +                                     data, len);
1299 +
1300 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1301 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1302 +
1303 +       /*
1304 +        * Wait for device to stabilize.
1305 +        */
1306 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1307 +               rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1308 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1309 +                       break;
1310 +               msleep(1);
1311 +       }
1312 +
1313 +       if (i == REGISTER_BUSY_COUNT) {
1314 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1315 +               return -EBUSY;
1316 +       }
1317 +
1318 +       /*
1319 +        * Disable interrupts
1320 +        */
1321 +       rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1322 +
1323 +       /*
1324 +        * Initialize BBP R/W access agent
1325 +        */
1326 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1327 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1328 +
1329 +       return 0;
1330 +}
1331 +
1332 +/*
1333 + * Initialization functions.
1334 + */
1335 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1336 +{
1337 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1338 +       u32 word;
1339 +
1340 +       if (entry->queue->qid == QID_RX) {
1341 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1342 +
1343 +               return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1344 +       } else {
1345 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1346 +
1347 +               return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1348 +       }
1349 +}
1350 +
1351 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1352 +{
1353 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1354 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1355 +       u32 word;
1356 +
1357 +       if (entry->queue->qid == QID_RX) {
1358 +               rt2x00_desc_read(entry_priv->desc, 0, &word);
1359 +               rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1360 +               rt2x00_desc_write(entry_priv->desc, 0, word);
1361 +
1362 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1363 +               rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1364 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1365 +       } else {
1366 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1367 +               rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1368 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1369 +       }
1370 +}
1371 +
1372 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1373 +{
1374 +       struct queue_entry_priv_pci *entry_priv;
1375 +       u32 reg;
1376 +
1377 +       /*
1378 +        * Initialize registers.
1379 +        */
1380 +       entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1381 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1382 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1383 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1384 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1385 +
1386 +       entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1387 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1388 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1389 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1390 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1391 +
1392 +       entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1393 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1394 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1395 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1396 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1397 +
1398 +       entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1399 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1400 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1401 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1402 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1403 +
1404 +       entry_priv = rt2x00dev->rx->entries[0].priv_data;
1405 +       rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1406 +       rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1407 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1408 +       rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1409 +
1410 +       /*
1411 +        * Enable global DMA configuration
1412 +        */
1413 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1414 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1415 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1416 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1417 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1418 +
1419 +       rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1420 +
1421 +       return 0;
1422 +}
1423 +
1424 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1425 +{
1426 +       u32 reg;
1427 +       unsigned int i;
1428 +
1429 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1430 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1431 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1432 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1433 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1434 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1435 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1436 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1437 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1438 +
1439 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1440 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1441 +
1442 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1443 +
1444 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1445 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1446 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1447 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1448 +
1449 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1450 +
1451 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1452 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1453 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1454 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1455 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1456 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1457 +
1458 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1459 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1460 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1461 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1462 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1463 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1464 +
1465 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1466 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1467 +
1468 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1469 +
1470 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1471 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1472 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1473 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1474 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1475 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1476 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1477 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1478 +
1479 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1480 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1481 +
1482 +       rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1483 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1484 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1485 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1486 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1487 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1488 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1489 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1490 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1491 +       rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1492 +
1493 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1494 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1495 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1496 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1497 +
1498 +       rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1499 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1500 +       if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1501 +           rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1502 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1503 +       else
1504 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1505 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1506 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1507 +       rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1508 +
1509 +       rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1510 +
1511 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1512 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1513 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1514 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1515 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1516 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1517 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1518 +
1519 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1520 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1521 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1522 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1523 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1524 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1525 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1526 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1527 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1528 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1529 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1530 +
1531 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1532 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1533 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1534 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1535 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1536 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1537 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1538 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1539 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1540 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1541 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1542 +
1543 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1544 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1545 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1546 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1547 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1548 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1549 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1550 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1551 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1552 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1553 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1554 +
1555 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1556 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1557 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1558 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1559 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1560 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1561 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1562 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1563 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1564 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1565 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1566 +
1567 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1568 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1569 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1570 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1571 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1572 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1573 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1574 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1575 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1576 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1577 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1578 +
1579 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1580 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1581 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1582 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1583 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1584 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1585 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1586 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1587 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1588 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1589 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1590 +
1591 +       rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1592 +       rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1593 +
1594 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1595 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1596 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1597 +                          IEEE80211_MAX_RTS_THRESHOLD);
1598 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1599 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1600 +
1601 +       rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1602 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1603 +
1604 +       /*
1605 +        * ASIC will keep garbage value after boot, clear encryption keys.
1606 +        */
1607 +       for (i = 0; i < 256; i++) {
1608 +               u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1609 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1610 +                                             wcid, sizeof(wcid));
1611 +
1612 +               rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1613 +               rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1614 +       }
1615 +
1616 +       for (i = 0; i < 16; i++)
1617 +               rt2x00pci_register_write(rt2x00dev,
1618 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1619 +
1620 +       /*
1621 +        * Clear all beacons
1622 +        * For the Beacon base registers we only need to clear
1623 +        * the first byte since that byte contains the VALID and OWNER
1624 +        * bits which (when set to 0) will invalidate the entire beacon.
1625 +        */
1626 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1627 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1628 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1629 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1630 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1631 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1632 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1633 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1634 +
1635 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1636 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1637 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1638 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1639 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1640 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1641 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1642 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1643 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1644 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1645 +
1646 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1647 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1648 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1649 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1650 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1651 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1652 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1653 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1654 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1655 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1656 +
1657 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1658 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1659 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1660 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1661 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1662 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1663 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1664 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1665 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1666 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1667 +
1668 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1669 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1670 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1671 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1672 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1673 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1674 +
1675 +       /*
1676 +        * We must clear the error counters.
1677 +        * These registers are cleared on read,
1678 +        * so we may pass a useless variable to store the value.
1679 +        */
1680 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1681 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1682 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1683 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1684 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1685 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1686 +
1687 +       return 0;
1688 +}
1689 +
1690 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1691 +{
1692 +       unsigned int i;
1693 +       u32 reg;
1694 +
1695 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1696 +               rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1697 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1698 +                       return 0;
1699 +
1700 +               udelay(REGISTER_BUSY_DELAY);
1701 +       }
1702 +
1703 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1704 +       return -EACCES;
1705 +}
1706 +
1707 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1708 +{
1709 +       unsigned int i;
1710 +       u8 value;
1711 +
1712 +       /*
1713 +        * BBP was enabled after firmware was loaded,
1714 +        * but we need to reactivate it now.
1715 +        */
1716 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1717 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1718 +       msleep(1);
1719 +
1720 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1721 +               rt2800pci_bbp_read(rt2x00dev, 0, &value);
1722 +               if ((value != 0xff) && (value != 0x00))
1723 +                       return 0;
1724 +               udelay(REGISTER_BUSY_DELAY);
1725 +       }
1726 +
1727 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1728 +       return -EACCES;
1729 +}
1730 +
1731 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1732 +{
1733 +       unsigned int i;
1734 +       u16 eeprom;
1735 +       u8 reg_id;
1736 +       u8 value;
1737 +
1738 +       if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1739 +                    rt2800pci_wait_bbp_ready(rt2x00dev)))
1740 +               return -EACCES;
1741 +
1742 +       rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1743 +       rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1744 +       rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1745 +       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1746 +       rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1747 +       rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1748 +       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1749 +       rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1750 +       rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1751 +       rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1752 +       rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1753 +       rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1754 +       rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1755 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1756 +
1757 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1758 +               rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1759 +               rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1760 +       }
1761 +
1762 +       if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1763 +               rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1764 +
1765 +       if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1766 +               rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1767 +               rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1768 +               rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1769 +       }
1770 +
1771 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1772 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1773 +
1774 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1775 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1776 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1777 +                       rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1778 +               }
1779 +       }
1780 +
1781 +       return 0;
1782 +}
1783 +
1784 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1785 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
1786 +{
1787 +       unsigned int i;
1788 +       u8 bbp;
1789 +       u8 rfcsr;
1790 +       u8 passband;
1791 +       u8 stopband;
1792 +       u8 overtuned = 0;
1793 +
1794 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1795 +
1796 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1797 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1798 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1799 +
1800 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1801 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1802 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1803 +
1804 +       /*
1805 +        * Set power & frequency of passband test tone
1806 +        */
1807 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
1808 +
1809 +       for (i = 0; i < 100; i++) {
1810 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1811 +               msleep(1);
1812 +
1813 +               rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1814 +               if (passband)
1815 +                       break;
1816 +       }
1817 +
1818 +       /*
1819 +        * Set power & frequency of stopband test tone
1820 +        */
1821 +       rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1822 +
1823 +       for (i = 0; i < 100; i++) {
1824 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1825 +               msleep(1);
1826 +
1827 +               rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1828 +
1829 +               if ((passband - stopband) <= filter_target) {
1830 +                       rfcsr24++;
1831 +                       overtuned += ((passband - stopband) == filter_target);
1832 +               } else
1833 +                       break;
1834 +
1835 +               rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1836 +       }
1837 +
1838 +       rfcsr24 -= !!overtuned;
1839 +
1840 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1841 +       return rfcsr24;
1842 +}
1843 +
1844 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1845 +{
1846 +       u8 rfcsr;
1847 +       u8 bbp;
1848 +
1849 +       if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1850 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1851 +           !rt2x00_rf(&rt2x00dev->chip, RF3022))
1852 +               return 0;
1853 +
1854 +       /*
1855 +        * Init RF calibration.
1856 +        */
1857 +       rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1858 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1859 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1860 +       msleep(1);
1861 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1862 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1863 +
1864 +       rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1865 +       rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1866 +       rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1867 +       rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1868 +       rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1869 +       rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1870 +       rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1871 +       rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1872 +       rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1873 +       rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1874 +       rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1875 +       rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1876 +       rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1877 +       rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1878 +       rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1879 +       rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1880 +       rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1881 +       rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1882 +       rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1883 +       rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1884 +       rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1885 +       rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1886 +       rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1887 +       rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1888 +       rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1889 +       rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1890 +       rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1891 +       rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1892 +       rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1893 +       rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1894 +
1895 +       /*
1896 +        * Set RX Filter calibration for 20MHz and 40MHz
1897 +        */
1898 +       rt2x00dev->calibration[0] =
1899 +           rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1900 +       rt2x00dev->calibration[1] =
1901 +           rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1902 +
1903 +       /*
1904 +        * Set back to initial state
1905 +        */
1906 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
1907 +
1908 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1909 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1910 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1911 +
1912 +       /*
1913 +        * set BBP back to BW20
1914 +        */
1915 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1916 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1917 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1918 +
1919 +       return 0;
1920 +}
1921 +
1922 +/*
1923 + * Device state switch handlers.
1924 + */
1925 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1926 +                               enum dev_state state)
1927 +{
1928 +       u32 reg;
1929 +
1930 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1931 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1932 +                          (state == STATE_RADIO_RX_ON) ||
1933 +                          (state == STATE_RADIO_RX_ON_LINK));
1934 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1935 +}
1936 +
1937 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1938 +                                enum dev_state state)
1939 +{
1940 +       int mask = (state == STATE_RADIO_IRQ_ON);
1941 +       u32 reg;
1942 +
1943 +       /*
1944 +        * When interrupts are being enabled, the interrupt registers
1945 +        * should clear the register to assure a clean state.
1946 +        */
1947 +       if (state == STATE_RADIO_IRQ_ON) {
1948 +               rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1949 +               rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1950 +       }
1951 +
1952 +       rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1953 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1954 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1955 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1956 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1957 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1958 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1959 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1960 +       rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1961 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1962 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1963 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1964 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1965 +       rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1966 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1967 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1968 +       rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1969 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1970 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1971 +       rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1972 +}
1973 +
1974 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1975 +{
1976 +       unsigned int i;
1977 +       u32 reg;
1978 +
1979 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1980 +               rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1981 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1982 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1983 +                       return 0;
1984 +
1985 +               msleep(1);
1986 +       }
1987 +
1988 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1989 +       return -EACCES;
1990 +}
1991 +
1992 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1993 +{
1994 +       u32 reg;
1995 +       u16 word;
1996 +
1997 +       /*
1998 +        * Initialize all registers.
1999 +        */
2000 +       if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2001 +                    rt2800pci_init_queues(rt2x00dev) ||
2002 +                    rt2800pci_init_registers(rt2x00dev) ||
2003 +                    rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2004 +                    rt2800pci_init_bbp(rt2x00dev) ||
2005 +                    rt2800pci_init_rfcsr(rt2x00dev)))
2006 +               return -EIO;
2007 +
2008 +       /*
2009 +        * Send signal to firmware during boot time.
2010 +        */
2011 +       rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2012 +
2013 +       /*
2014 +        * Enable RX.
2015 +        */
2016 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2017 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2018 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2019 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2020 +
2021 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2022 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2023 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2024 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2025 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2026 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2027 +
2028 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2029 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2030 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2031 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2032 +
2033 +       /*
2034 +        * Initialize LED control
2035 +        */
2036 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2037 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2038 +                             word & 0xff, (word >> 8) & 0xff);
2039 +
2040 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2041 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2042 +                             word & 0xff, (word >> 8) & 0xff);
2043 +
2044 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2045 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2046 +                             word & 0xff, (word >> 8) & 0xff);
2047 +
2048 +       return 0;
2049 +}
2050 +
2051 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2052 +{
2053 +       u32 reg;
2054 +
2055 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2056 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2057 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2058 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2059 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2060 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2061 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2062 +
2063 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2064 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2065 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2066 +
2067 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2068 +
2069 +       /* Wait for DMA, ignore error */
2070 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
2071 +}
2072 +
2073 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2074 +                              enum dev_state state)
2075 +{
2076 +       /*
2077 +        * Always put the device to sleep (even when we intend to wakeup!)
2078 +        * if the device is booting and wasn't asleep it will return
2079 +        * failure when attempting to wakeup.
2080 +        */
2081 +       rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2082 +
2083 +       if (state == STATE_AWAKE) {
2084 +               rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2085 +               rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2086 +       }
2087 +
2088 +       return 0;
2089 +}
2090 +
2091 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2092 +                                     enum dev_state state)
2093 +{
2094 +       int retval = 0;
2095 +
2096 +       switch (state) {
2097 +       case STATE_RADIO_ON:
2098 +               /*
2099 +                * Before the radio can be enabled, the device first has
2100 +                * to be woken up. After that it needs a bit of time
2101 +                * to be fully awake and then the radio can be enabled.
2102 +                */
2103 +               rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2104 +               msleep(1);
2105 +               retval = rt2800pci_enable_radio(rt2x00dev);
2106 +               break;
2107 +       case STATE_RADIO_OFF:
2108 +               /*
2109 +                * After the radio has been disabled, the device should
2110 +                * be put to sleep for powersaving.
2111 +                */
2112 +               rt2800pci_disable_radio(rt2x00dev);
2113 +               rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2114 +               break;
2115 +       case STATE_RADIO_RX_ON:
2116 +       case STATE_RADIO_RX_ON_LINK:
2117 +       case STATE_RADIO_RX_OFF:
2118 +       case STATE_RADIO_RX_OFF_LINK:
2119 +               rt2800pci_toggle_rx(rt2x00dev, state);
2120 +               break;
2121 +       case STATE_RADIO_IRQ_ON:
2122 +       case STATE_RADIO_IRQ_OFF:
2123 +               rt2800pci_toggle_irq(rt2x00dev, state);
2124 +               break;
2125 +       case STATE_DEEP_SLEEP:
2126 +       case STATE_SLEEP:
2127 +       case STATE_STANDBY:
2128 +       case STATE_AWAKE:
2129 +               retval = rt2800pci_set_state(rt2x00dev, state);
2130 +               break;
2131 +       default:
2132 +               retval = -ENOTSUPP;
2133 +               break;
2134 +       }
2135 +
2136 +       if (unlikely(retval))
2137 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2138 +                     state, retval);
2139 +
2140 +       return retval;
2141 +}
2142 +
2143 +/*
2144 + * TX descriptor initialization
2145 + */
2146 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2147 +                                   struct sk_buff *skb,
2148 +                                   struct txentry_desc *txdesc)
2149 +{
2150 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2151 +       __le32 *txd = skbdesc->desc;
2152 +       __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2153 +       u32 word;
2154 +
2155 +       /*
2156 +        * Initialize TX Info descriptor
2157 +        */
2158 +       rt2x00_desc_read(txwi, 0, &word);
2159 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
2160 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2161 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2162 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2163 +       rt2x00_set_field32(&word, TXWI_W0_TS,
2164 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2165 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2166 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2167 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2168 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2169 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2170 +       rt2x00_set_field32(&word, TXWI_W0_BW,
2171 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2172 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2173 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2174 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2175 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2176 +       rt2x00_desc_write(txwi, 0, word);
2177 +
2178 +       rt2x00_desc_read(txwi, 1, &word);
2179 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2180 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2181 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2182 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2183 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2184 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2185 +                          test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2186 +                              txdesc->key_idx : 0xff);
2187 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2188 +                          skb->len - txdesc->l2pad);
2189 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2190 +                          skbdesc->entry->queue->qid);
2191 +       rt2x00_desc_write(txwi, 1, word);
2192 +
2193 +       /*
2194 +        * Always write 0 to IV/EIV fields, hardware will insert the IV
2195 +        * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2196 +        * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2197 +        * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2198 +        * crypto entry in the registers should be used to encrypt the frame.
2199 +        */
2200 +       _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2201 +       _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2202 +
2203 +       /*
2204 +        * Initialize TX descriptor
2205 +        */
2206 +       rt2x00_desc_read(txd, 0, &word);
2207 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2208 +       rt2x00_desc_write(txd, 0, word);
2209 +
2210 +       rt2x00_desc_read(txd, 1, &word);
2211 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2212 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2213 +       rt2x00_set_field32(&word, TXD_W1_BURST,
2214 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2215 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2216 +                          rt2x00dev->hw->extra_tx_headroom);
2217 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2218 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2219 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2220 +       rt2x00_desc_write(txd, 1, word);
2221 +
2222 +       rt2x00_desc_read(txd, 2, &word);
2223 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2224 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2225 +       rt2x00_desc_write(txd, 2, word);
2226 +
2227 +       rt2x00_desc_read(txd, 3, &word);
2228 +       rt2x00_set_field32(&word, TXD_W3_WIV,
2229 +                          !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2230 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2231 +       rt2x00_desc_write(txd, 3, word);
2232 +}
2233 +
2234 +/*
2235 + * TX data initialization
2236 + */
2237 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2238 +{
2239 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2240 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2241 +       unsigned int beacon_base;
2242 +       u32 reg;
2243 +
2244 +       /*
2245 +        * Disable beaconing while we are reloading the beacon data,
2246 +        * otherwise we might be sending out invalid data.
2247 +        */
2248 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2249 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2250 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2251 +
2252 +       /*
2253 +        * Write entire beacon with descriptor to register.
2254 +        */
2255 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2256 +       rt2x00pci_register_multiwrite(rt2x00dev,
2257 +                                     beacon_base,
2258 +                                     skbdesc->desc, skbdesc->desc_len);
2259 +       rt2x00pci_register_multiwrite(rt2x00dev,
2260 +                                     beacon_base + skbdesc->desc_len,
2261 +                                     entry->skb->data, entry->skb->len);
2262 +
2263 +       /*
2264 +        * Clean up beacon skb.
2265 +        */
2266 +       dev_kfree_skb_any(entry->skb);
2267 +       entry->skb = NULL;
2268 +}
2269 +
2270 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2271 +                                   const enum data_queue_qid queue_idx)
2272 +{
2273 +       struct data_queue *queue;
2274 +       unsigned int idx, qidx = 0;
2275 +       u32 reg;
2276 +
2277 +       if (queue_idx == QID_BEACON) {
2278 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2279 +               if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2280 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2281 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2282 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2283 +                       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2284 +               }
2285 +               return;
2286 +       }
2287 +
2288 +       if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2289 +               return;
2290 +
2291 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2292 +       idx = queue->index[Q_INDEX];
2293 +
2294 +       if (queue_idx == QID_MGMT)
2295 +               qidx = 5;
2296 +       else
2297 +               qidx = queue_idx;
2298 +
2299 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2300 +}
2301 +
2302 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2303 +                                   const enum data_queue_qid qid)
2304 +{
2305 +       u32 reg;
2306 +
2307 +       if (qid == QID_BEACON) {
2308 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2309 +               return;
2310 +       }
2311 +
2312 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2313 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2314 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2315 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2316 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2317 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2318 +}
2319 +
2320 +/*
2321 + * RX control handlers
2322 + */
2323 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2324 +                                 struct rxdone_entry_desc *rxdesc)
2325 +{
2326 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2327 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2328 +       __le32 *rxd = entry_priv->desc;
2329 +       __le32 *rxwi = (__le32 *)entry->skb->data;
2330 +       u32 rxd3;
2331 +       u32 rxwi0;
2332 +       u32 rxwi1;
2333 +       u32 rxwi2;
2334 +       u32 rxwi3;
2335 +
2336 +       rt2x00_desc_read(rxd, 3, &rxd3);
2337 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2338 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2339 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2340 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2341 +
2342 +       if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2343 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2344 +
2345 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2346 +               /*
2347 +                * Unfortunately we don't know the cipher type used during
2348 +                * decryption. This prevents us from correct providing
2349 +                * correct statistics through debugfs.
2350 +                */
2351 +               rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2352 +               rxdesc->cipher_status =
2353 +                   rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2354 +       }
2355 +
2356 +       if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2357 +               /*
2358 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2359 +                * decryption. Unfortunately the descriptor doesn't contain
2360 +                * any fields with the EIV/IV data either, so they can't
2361 +                * be restored by rt2x00lib.
2362 +                */
2363 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2364 +
2365 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2366 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2367 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2368 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2369 +       }
2370 +
2371 +       if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2372 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2373 +
2374 +       if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
2375 +               rxdesc->dev_flags |= RXDONE_L2PAD;
2376 +
2377 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2378 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
2379 +
2380 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2381 +               rxdesc->flags |= RX_FLAG_40MHZ;
2382 +
2383 +       /*
2384 +        * Detect RX rate, always use MCS as signal type.
2385 +        */
2386 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2387 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2388 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2389 +
2390 +       /*
2391 +        * Mask of 0x8 bit to remove the short preamble flag.
2392 +        */
2393 +       if (rxdesc->rate_mode == RATE_MODE_CCK)
2394 +               rxdesc->signal &= ~0x8;
2395 +
2396 +       rxdesc->rssi =
2397 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2398 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2399 +
2400 +       rxdesc->noise =
2401 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2402 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2403 +
2404 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2405 +
2406 +       /*
2407 +        * Set RX IDX in register to inform hardware that we have handled
2408 +        * this entry and it is available for reuse again.
2409 +        */
2410 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2411 +
2412 +       /*
2413 +        * Remove TXWI descriptor from start of buffer.
2414 +        */
2415 +       skb_pull(entry->skb, RXWI_DESC_SIZE);
2416 +       skb_trim(entry->skb, rxdesc->size);
2417 +}
2418 +
2419 +/*
2420 + * Interrupt functions.
2421 + */
2422 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2423 +{
2424 +       struct data_queue *queue;
2425 +       struct queue_entry *entry;
2426 +       struct queue_entry *entry_done;
2427 +       struct queue_entry_priv_pci *entry_priv;
2428 +       struct txdone_entry_desc txdesc;
2429 +       u32 word;
2430 +       u32 reg;
2431 +       u32 old_reg;
2432 +       int type;
2433 +       int index;
2434 +
2435 +       /*
2436 +        * During each loop we will compare the freshly read
2437 +        * TX_STA_FIFO register value with the value read from
2438 +        * the previous loop. If the 2 values are equal then
2439 +        * we should stop processing because the chance it
2440 +        * quite big that the device has been unplugged and
2441 +        * we risk going into an endless loop.
2442 +        */
2443 +       old_reg = 0;
2444 +
2445 +       while (1) {
2446 +               rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2447 +               if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2448 +                       break;
2449 +
2450 +               if (old_reg == reg)
2451 +                       break;
2452 +               old_reg = reg;
2453 +
2454 +               /*
2455 +                * Skip this entry when it contains an invalid
2456 +                * queue identication number.
2457 +                */
2458 +               type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2459 +               queue = rt2x00queue_get_queue(rt2x00dev, type);
2460 +               if (unlikely(!queue))
2461 +                       continue;
2462 +
2463 +               /*
2464 +                * Skip this entry when it contains an invalid
2465 +                * index number.
2466 +                */
2467 +               index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2468 +               if (unlikely(index >= queue->limit))
2469 +                       continue;
2470 +
2471 +               entry = &queue->entries[index];
2472 +               entry_priv = entry->priv_data;
2473 +               rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2474 +
2475 +               entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2476 +               while (entry != entry_done) {
2477 +                       /*
2478 +                        * Catch up.
2479 +                        * Just report any entries we missed as failed.
2480 +                        */
2481 +                       WARNING(rt2x00dev,
2482 +                               "TX status report missed for entry %d\n",
2483 +                               entry_done->entry_idx);
2484 +
2485 +                       txdesc.flags = 0;
2486 +                       __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2487 +                       txdesc.retry = 0;
2488 +
2489 +                       rt2x00lib_txdone(entry_done, &txdesc);
2490 +                       entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2491 +               }
2492 +
2493 +               /*
2494 +                * Obtain the status about this packet.
2495 +                */
2496 +               txdesc.flags = 0;
2497 +               if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2498 +                       __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2499 +               else
2500 +                       __set_bit(TXDONE_FAILURE, &txdesc.flags);
2501 +               txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2502 +
2503 +               rt2x00lib_txdone(entry, &txdesc);
2504 +       }
2505 +}
2506 +
2507 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2508 +{
2509 +       struct rt2x00_dev *rt2x00dev = dev_instance;
2510 +       u32 reg;
2511 +
2512 +       /* Read status and ACK all interrupts */
2513 +       rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2514 +       rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2515 +
2516 +       if (!reg)
2517 +               return IRQ_NONE;
2518 +
2519 +       if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2520 +               return IRQ_HANDLED;
2521 +
2522 +       /*
2523 +        * 1 - Rx ring done interrupt.
2524 +        */
2525 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2526 +               rt2x00pci_rxdone(rt2x00dev);
2527 +
2528 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2529 +               rt2800pci_txdone(rt2x00dev);
2530 +
2531 +       return IRQ_HANDLED;
2532 +}
2533 +
2534 +/*
2535 + * Device probe functions.
2536 + */
2537 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2538 +{
2539 +       u16 word;
2540 +       u8 *mac;
2541 +       u8 default_lna_gain;
2542 +
2543 +       /*
2544 +        * Read EEPROM into buffer
2545 +        */
2546 +       switch(rt2x00dev->chip.rt) {
2547 +       case RT2880:
2548 +       case RT3052:
2549 +               rt2800pci_read_eeprom_soc(rt2x00dev);
2550 +               break;
2551 +       default:
2552 +               rt2800pci_read_eeprom_pci(rt2x00dev);
2553 +               break;
2554 +       }
2555 +
2556 +       /*
2557 +        * Start validation of the data that has been read.
2558 +        */
2559 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2560 +       if (!is_valid_ether_addr(mac)) {
2561 +               DECLARE_MAC_BUF(macbuf);
2562 +
2563 +               random_ether_addr(mac);
2564 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2565 +       }
2566 +
2567 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2568 +       if (word == 0xffff) {
2569 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2570 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2571 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2572 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2573 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2574 +       } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2575 +               /*
2576 +                * There is a max of 2 RX streams for RT2860 series
2577 +                */
2578 +               if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2579 +                       rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2580 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2581 +       }
2582 +
2583 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2584 +       if (word == 0xffff) {
2585 +               rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2586 +               rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2587 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2588 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2589 +               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2590 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2591 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2592 +               rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2593 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2594 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2595 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2596 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2597 +       }
2598 +
2599 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2600 +       if ((word & 0x00ff) == 0x00ff) {
2601 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2602 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2603 +                                  LED_MODE_TXRX_ACTIVITY);
2604 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2605 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2606 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2607 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2608 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2609 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2610 +       }
2611 +
2612 +       /*
2613 +        * During the LNA validation we are going to use
2614 +        * lna0 as correct value. Note that EEPROM_LNA
2615 +        * is never validated.
2616 +        */
2617 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2618 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2619 +
2620 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2621 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2622 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2623 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2624 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2625 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2626 +
2627 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2628 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2629 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2630 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2631 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2632 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2633 +                                  default_lna_gain);
2634 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2635 +
2636 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2637 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2638 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2639 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2640 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2641 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2642 +
2643 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2644 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2645 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2646 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2647 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2648 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2649 +                                  default_lna_gain);
2650 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2651 +
2652 +       return 0;
2653 +}
2654 +
2655 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2656 +{
2657 +       u32 reg;
2658 +       u16 value;
2659 +       u16 eeprom;
2660 +
2661 +       /*
2662 +        * Read EEPROM word for configuration.
2663 +        */
2664 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2665 +
2666 +       /*
2667 +        * Identify RF chipset.
2668 +        */
2669 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2670 +       rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2671 +       rt2x00_set_chip_rf(rt2x00dev, value, reg);
2672 +
2673 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2674 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2675 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2676 +           !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2677 +           !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2678 +           !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2679 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2680 +           !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2681 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2682 +               return -ENODEV;
2683 +       }
2684 +
2685 +       /*
2686 +        * Identify default antenna configuration.
2687 +        */
2688 +       rt2x00dev->default_ant.tx =
2689 +           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2690 +       rt2x00dev->default_ant.rx =
2691 +           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2692 +
2693 +       /*
2694 +        * Read frequency offset and RF programming sequence.
2695 +        */
2696 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2697 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2698 +
2699 +       /*
2700 +        * Read external LNA informations.
2701 +        */
2702 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2703 +
2704 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2705 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2706 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2707 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2708 +
2709 +       /*
2710 +        * Detect if this device has an hardware controlled radio.
2711 +        */
2712 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2713 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2714 +
2715 +       /*
2716 +        * Store led settings, for correct led behaviour.
2717 +        */
2718 +#ifdef CONFIG_RT2X00_LIB_LEDS
2719 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2720 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2721 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2722 +
2723 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2724 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2725 +
2726 +       return 0;
2727 +}
2728 +
2729 +/*
2730 + * RF value list for rt2860
2731 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2732 + */
2733 +static const struct rf_channel rf_vals[] = {
2734 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2735 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2736 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2737 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2738 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2739 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2740 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2741 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2742 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2743 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2744 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2745 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2746 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2747 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2748 +
2749 +       /* 802.11 UNI / HyperLan 2 */
2750 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2751 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2752 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2753 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2754 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2755 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2756 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2757 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2758 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2759 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2760 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2761 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2762 +
2763 +       /* 802.11 HyperLan 2 */
2764 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2765 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2766 +       { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2767 +       { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2768 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2769 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2770 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2771 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2772 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2773 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2774 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2775 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2776 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2777 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2778 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2779 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2780 +
2781 +       /* 802.11 UNII */
2782 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2783 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2784 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2785 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2786 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2787 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2788 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2789 +
2790 +       /* 802.11 Japan */
2791 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2792 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2793 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2794 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2795 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2796 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2797 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2798 +};
2799 +
2800 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2801 +{
2802 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2803 +       struct channel_info *info;
2804 +       char *tx_power1;
2805 +       char *tx_power2;
2806 +       unsigned int i;
2807 +       u16 eeprom;
2808 +
2809 +       /*
2810 +        * Initialize all hw fields.
2811 +        */
2812 +       rt2x00dev->hw->flags =
2813 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2814 +           IEEE80211_HW_SIGNAL_DBM |
2815 +           IEEE80211_HW_SUPPORTS_PS |
2816 +           IEEE80211_HW_PS_NULLFUNC_STACK;
2817 +       rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2818 +
2819 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2820 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2821 +                               rt2x00_eeprom_addr(rt2x00dev,
2822 +                                                  EEPROM_MAC_ADDR_0));
2823 +
2824 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2825 +
2826 +       /*
2827 +        * Initialize hw_mode information.
2828 +        */
2829 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2830 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2831 +
2832 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2833 +           rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2834 +           rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2835 +           rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2836 +               spec->num_channels = 14;
2837 +               spec->channels = rf_vals;
2838 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2839 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2840 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2841 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2842 +               spec->channels = rf_vals;
2843 +       }
2844 +
2845 +       /*
2846 +        * Initialize HT information.
2847 +        */
2848 +       spec->ht.ht_supported = true;
2849 +       spec->ht.cap =
2850 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2851 +           IEEE80211_HT_CAP_GRN_FLD |
2852 +           IEEE80211_HT_CAP_SGI_20 |
2853 +           IEEE80211_HT_CAP_SGI_40 |
2854 +           IEEE80211_HT_CAP_TX_STBC |
2855 +           IEEE80211_HT_CAP_RX_STBC |
2856 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2857 +       spec->ht.ampdu_factor = 3;
2858 +       spec->ht.ampdu_density = 4;
2859 +       spec->ht.mcs.tx_params =
2860 +           IEEE80211_HT_MCS_TX_DEFINED |
2861 +           IEEE80211_HT_MCS_TX_RX_DIFF |
2862 +           ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2863 +               IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2864 +
2865 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2866 +       case 3:
2867 +               spec->ht.mcs.rx_mask[2] = 0xff;
2868 +       case 2:
2869 +               spec->ht.mcs.rx_mask[1] = 0xff;
2870 +       case 1:
2871 +               spec->ht.mcs.rx_mask[0] = 0xff;
2872 +               spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2873 +               break;
2874 +       }
2875 +
2876 +       /*
2877 +        * Create channel information array
2878 +        */
2879 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2880 +       if (!info)
2881 +               return -ENOMEM;
2882 +
2883 +       spec->channels_info = info;
2884 +
2885 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2886 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2887 +
2888 +       for (i = 0; i < 14; i++) {
2889 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2890 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2891 +       }
2892 +
2893 +       if (spec->num_channels > 14) {
2894 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2895 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2896 +
2897 +               for (i = 14; i < spec->num_channels; i++) {
2898 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2899 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2900 +               }
2901 +       }
2902 +
2903 +       return 0;
2904 +}
2905 +
2906 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2907 +{
2908 +       int retval;
2909 +
2910 +       /*
2911 +        * Allocate eeprom data.
2912 +        */
2913 +       retval = rt2800pci_validate_eeprom(rt2x00dev);
2914 +       if (retval)
2915 +               return retval;
2916 +
2917 +       retval = rt2800pci_init_eeprom(rt2x00dev);
2918 +       if (retval)
2919 +               return retval;
2920 +
2921 +       /*
2922 +        * Initialize hw specifications.
2923 +        */
2924 +       retval = rt2800pci_probe_hw_mode(rt2x00dev);
2925 +       if (retval)
2926 +               return retval;
2927 +
2928 +       /*
2929 +        * This device has multiple filters for control frames
2930 +        * and has a separate filter for PS Poll frames.
2931 +        */
2932 +       __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2933 +       __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2934 +
2935 +       /*
2936 +        * This device requires firmware.
2937 +        */
2938 +       if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2939 +           !rt2x00_rt(&rt2x00dev->chip, RT3052))
2940 +               __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2941 +       __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2942 +       __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2943 +       if (!modparam_nohwcrypt)
2944 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2945 +
2946 +       /*
2947 +        * Set the rssi offset.
2948 +        */
2949 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2950 +
2951 +       return 0;
2952 +}
2953 +
2954 +/*
2955 + * IEEE80211 stack callback functions.
2956 + */
2957 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2958 +                                  u32 *iv32, u16 *iv16)
2959 +{
2960 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2961 +       struct mac_iveiv_entry iveiv_entry;
2962 +       u32 offset;
2963 +
2964 +       offset = MAC_IVEIV_ENTRY(hw_key_idx);
2965 +       rt2x00pci_register_multiread(rt2x00dev, offset,
2966 +                                     &iveiv_entry, sizeof(iveiv_entry));
2967 +
2968 +       memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2969 +       memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2970 +}
2971 +
2972 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2973 +{
2974 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2975 +       u32 reg;
2976 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2977 +
2978 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2979 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2980 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2981 +
2982 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2983 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2984 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2985 +
2986 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2987 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2988 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2989 +
2990 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2991 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2992 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2993 +
2994 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2995 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2996 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2997 +
2998 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2999 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3000 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3001 +
3002 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3003 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3004 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3005 +
3006 +       return 0;
3007 +}
3008 +
3009 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3010 +                            const struct ieee80211_tx_queue_params *params)
3011 +{
3012 +       struct rt2x00_dev *rt2x00dev = hw->priv;
3013 +       struct data_queue *queue;
3014 +       struct rt2x00_field32 field;
3015 +       int retval;
3016 +       u32 reg;
3017 +       u32 offset;
3018 +
3019 +       /*
3020 +        * First pass the configuration through rt2x00lib, that will
3021 +        * update the queue settings and validate the input. After that
3022 +        * we are free to update the registers based on the value
3023 +        * in the queue parameter.
3024 +        */
3025 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3026 +       if (retval)
3027 +               return retval;
3028 +
3029 +       /*
3030 +        * We only need to perform additional register initialization
3031 +        * for WMM queues/
3032 +        */
3033 +       if (queue_idx >= 4)
3034 +               return 0;
3035 +
3036 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3037 +
3038 +       /* Update WMM TXOP register */
3039 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3040 +       field.bit_offset = (queue_idx & 1) * 16;
3041 +       field.bit_mask = 0xffff << field.bit_offset;
3042 +
3043 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
3044 +       rt2x00_set_field32(&reg, field, queue->txop);
3045 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
3046 +
3047 +       /* Update WMM registers */
3048 +       field.bit_offset = queue_idx * 4;
3049 +       field.bit_mask = 0xf << field.bit_offset;
3050 +
3051 +       rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3052 +       rt2x00_set_field32(&reg, field, queue->aifs);
3053 +       rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3054 +
3055 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3056 +       rt2x00_set_field32(&reg, field, queue->cw_min);
3057 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3058 +
3059 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3060 +       rt2x00_set_field32(&reg, field, queue->cw_max);
3061 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3062 +
3063 +       /* Update EDCA registers */
3064 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3065 +
3066 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
3067 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3068 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3069 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3070 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3071 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
3072 +
3073 +       return 0;
3074 +}
3075 +
3076 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3077 +{
3078 +       struct rt2x00_dev *rt2x00dev = hw->priv;
3079 +       u64 tsf;
3080 +       u32 reg;
3081 +
3082 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3083 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3084 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3085 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3086 +
3087 +       return tsf;
3088 +}
3089 +
3090 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3091 +       .tx                     = rt2x00mac_tx,
3092 +       .start                  = rt2x00mac_start,
3093 +       .stop                   = rt2x00mac_stop,
3094 +       .add_interface          = rt2x00mac_add_interface,
3095 +       .remove_interface       = rt2x00mac_remove_interface,
3096 +       .config                 = rt2x00mac_config,
3097 +       .configure_filter       = rt2x00mac_configure_filter,
3098 +       .set_key                = rt2x00mac_set_key,
3099 +       .get_stats              = rt2x00mac_get_stats,
3100 +       .get_tkip_seq           = rt2800pci_get_tkip_seq,
3101 +       .set_rts_threshold      = rt2800pci_set_rts_threshold,
3102 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
3103 +       .conf_tx                = rt2800pci_conf_tx,
3104 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
3105 +       .get_tsf                = rt2800pci_get_tsf,
3106 +       .rfkill_poll            = rt2x00mac_rfkill_poll,
3107 +};
3108 +
3109 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3110 +       .irq_handler            = rt2800pci_interrupt,
3111 +       .probe_hw               = rt2800pci_probe_hw,
3112 +       .get_firmware_name      = rt2800pci_get_firmware_name,
3113 +       .check_firmware         = rt2800pci_check_firmware,
3114 +       .load_firmware          = rt2800pci_load_firmware,
3115 +       .initialize             = rt2x00pci_initialize,
3116 +       .uninitialize           = rt2x00pci_uninitialize,
3117 +       .get_entry_state        = rt2800pci_get_entry_state,
3118 +       .clear_entry            = rt2800pci_clear_entry,
3119 +       .set_device_state       = rt2800pci_set_device_state,
3120 +       .rfkill_poll            = rt2800pci_rfkill_poll,
3121 +       .link_stats             = rt2800pci_link_stats,
3122 +       .reset_tuner            = rt2800pci_reset_tuner,
3123 +       .link_tuner             = rt2800pci_link_tuner,
3124 +       .write_tx_desc          = rt2800pci_write_tx_desc,
3125 +       .write_tx_data          = rt2x00pci_write_tx_data,
3126 +       .write_beacon           = rt2800pci_write_beacon,
3127 +       .kick_tx_queue          = rt2800pci_kick_tx_queue,
3128 +       .kill_tx_queue          = rt2800pci_kill_tx_queue,
3129 +       .fill_rxdone            = rt2800pci_fill_rxdone,
3130 +       .config_shared_key      = rt2800pci_config_shared_key,
3131 +       .config_pairwise_key    = rt2800pci_config_pairwise_key,
3132 +       .config_filter          = rt2800pci_config_filter,
3133 +       .config_intf            = rt2800pci_config_intf,
3134 +       .config_erp             = rt2800pci_config_erp,
3135 +       .config_ant             = rt2800pci_config_ant,
3136 +       .config                 = rt2800pci_config,
3137 +};
3138 +
3139 +static const struct data_queue_desc rt2800pci_queue_rx = {
3140 +       .entry_num              = RX_ENTRIES,
3141 +       .data_size              = AGGREGATION_SIZE,
3142 +       .desc_size              = RXD_DESC_SIZE,
3143 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3144 +};
3145 +
3146 +static const struct data_queue_desc rt2800pci_queue_tx = {
3147 +       .entry_num              = TX_ENTRIES,
3148 +       .data_size              = AGGREGATION_SIZE,
3149 +       .desc_size              = TXD_DESC_SIZE,
3150 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3151 +};
3152 +
3153 +static const struct data_queue_desc rt2800pci_queue_bcn = {
3154 +       .entry_num              = 8 * BEACON_ENTRIES,
3155 +       .data_size              = 0, /* No DMA required for beacons */
3156 +       .desc_size              = TXWI_DESC_SIZE,
3157 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3158 +};
3159 +
3160 +static const struct rt2x00_ops rt2800pci_ops = {
3161 +       .name           = KBUILD_MODNAME,
3162 +       .max_sta_intf   = 1,
3163 +       .max_ap_intf    = 8,
3164 +       .eeprom_size    = EEPROM_SIZE,
3165 +       .rf_size        = RF_SIZE,
3166 +       .tx_queues      = NUM_TX_QUEUES,
3167 +       .rx             = &rt2800pci_queue_rx,
3168 +       .tx             = &rt2800pci_queue_tx,
3169 +       .bcn            = &rt2800pci_queue_bcn,
3170 +       .lib            = &rt2800pci_rt2x00_ops,
3171 +       .hw             = &rt2800pci_mac80211_ops,
3172 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3173 +       .debugfs        = &rt2800pci_rt2x00debug,
3174 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3175 +};
3176 +
3177 +/*
3178 + * RT2800pci module information.
3179 + */
3180 +static struct pci_device_id rt2800pci_device_table[] = {
3181 +       /* Edimax */
3182 +       { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3183 +       { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3184 +       { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3185 +       { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3186 +       { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3187 +       { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3188 +       { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3189 +       { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3190 +       { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3191 +       { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3192 +       { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3193 +       { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3194 +       { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3195 +       { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3196 +       { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3197 +       { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3198 +       { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3199 +       /* Awt */
3200 +       { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3201 +       { 0, }
3202 +};
3203 +
3204 +MODULE_AUTHOR(DRV_PROJECT);
3205 +MODULE_VERSION(DRV_VERSION);
3206 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3207 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3208 +#ifdef CONFIG_RT2800PCI_PCI
3209 +MODULE_FIRMWARE(FIRMWARE_RT2860);
3210 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3211 +#endif /* CONFIG_RT2800PCI_PCI */
3212 +MODULE_LICENSE("GPL");
3213 +
3214 +#ifdef CONFIG_RT2800PCI_WISOC
3215 +#if defined(CONFIG_RALINK_RT288X)
3216 +__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3217 +#elif defined(CONFIG_RALINK_RT305X)
3218 +__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3219 +#endif
3220 +
3221 +static struct platform_driver rt2800soc_driver = {
3222 +       .driver         = {
3223 +               .name           = "rt2800_wmac",
3224 +               .owner          = THIS_MODULE,
3225 +               .mod_name       = KBUILD_MODNAME,
3226 +       },
3227 +       .probe          = __rt2x00soc_probe,
3228 +       .remove         = __devexit_p(rt2x00soc_remove),
3229 +       .suspend        = rt2x00soc_suspend,
3230 +       .resume         = rt2x00soc_resume,
3231 +};
3232 +#endif /* CONFIG_RT2800PCI_WISOC */
3233 +
3234 +#ifdef CONFIG_RT2800PCI_PCI
3235 +static struct pci_driver rt2800pci_driver = {
3236 +       .name           = KBUILD_MODNAME,
3237 +       .id_table       = rt2800pci_device_table,
3238 +       .probe          = rt2x00pci_probe,
3239 +       .remove         = __devexit_p(rt2x00pci_remove),
3240 +       .suspend        = rt2x00pci_suspend,
3241 +       .resume         = rt2x00pci_resume,
3242 +};
3243 +#endif /* CONFIG_RT2800PCI_PCI */
3244 +
3245 +static int __init rt2800pci_init(void)
3246 +{
3247 +       int ret = 0;
3248 +
3249 +#ifdef CONFIG_RT2800PCI_WISOC
3250 +       ret = platform_driver_register(&rt2800soc_driver);
3251 +       if (ret)
3252 +               return ret;
3253 +#endif
3254 +#ifdef CONFIG_RT2800PCI_PCI
3255 +       ret = pci_register_driver(&rt2800pci_driver);
3256 +       if (ret) {
3257 +#ifdef CONFIG_RT2800PCI_WISOC
3258 +               platform_driver_unregister(&rt2800soc_driver);
3259 +#endif
3260 +               return ret;
3261 +       }
3262 +#endif
3263 +
3264 +       return ret;
3265 +}
3266 +
3267 +static void __exit rt2800pci_exit(void)
3268 +{
3269 +#ifdef CONFIG_RT2800PCI_PCI
3270 +       pci_unregister_driver(&rt2800pci_driver);
3271 +#endif
3272 +#ifdef CONFIG_RT2800PCI_WISOC
3273 +       platform_driver_unregister(&rt2800soc_driver);
3274 +#endif
3275 +}
3276 +
3277 +module_init(rt2800pci_init);
3278 +module_exit(rt2800pci_exit);
3279 --- /dev/null
3280 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3281 @@ -0,0 +1,1929 @@
3282 +/*
3283 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3284 +       <http://rt2x00.serialmonkey.com>
3285 +
3286 +       This program is free software; you can redistribute it and/or modify
3287 +       it under the terms of the GNU General Public License as published by
3288 +       the Free Software Foundation; either version 2 of the License, or
3289 +       (at your option) any later version.
3290 +
3291 +       This program is distributed in the hope that it will be useful,
3292 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
3293 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3294 +       GNU General Public License for more details.
3295 +
3296 +       You should have received a copy of the GNU General Public License
3297 +       along with this program; if not, write to the
3298 +       Free Software Foundation, Inc.,
3299 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3300 + */
3301 +
3302 +/*
3303 +       Module: rt2800pci
3304 +       Abstract: Data structures and registers for the rt2800pci module.
3305 +       Supported chipsets: RT2800E & RT2800ED.
3306 + */
3307 +
3308 +#ifndef RT2800PCI_H
3309 +#define RT2800PCI_H
3310 +
3311 +/*
3312 + * RF chip defines.
3313 + *
3314 + * RF2820 2.4G 2T3R
3315 + * RF2850 2.4G/5G 2T3R
3316 + * RF2720 2.4G 1T2R
3317 + * RF2750 2.4G/5G 1T2R
3318 + * RF3020 2.4G 1T1R
3319 + * RF2020 2.4G B/G
3320 + * RF3021 2.4G 1T2R
3321 + * RF3022 2.4G 2T2R
3322 + */
3323 +#define RF2820                         0x0001
3324 +#define RF2850                         0x0002
3325 +#define RF2720                         0x0003
3326 +#define RF2750                         0x0004
3327 +#define RF3020                         0x0005
3328 +#define RF2020                         0x0006
3329 +#define RF3021                         0x0007
3330 +#define RF3022                         0x0008
3331 +
3332 +/*
3333 + * RT2860 version
3334 + */
3335 +#define RT2860C_VERSION                        0x28600100
3336 +#define RT2860D_VERSION                        0x28600101
3337 +#define RT2880E_VERSION                        0x28720200
3338 +#define RT2883_VERSION                 0x28830300
3339 +#define RT3070_VERSION                 0x30700200
3340 +
3341 +/*
3342 + * Signal information.
3343 + * Default offset is required for RSSI <-> dBm conversion.
3344 + */
3345 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
3346 +
3347 +/*
3348 + * Register layout information.
3349 + */
3350 +#define CSR_REG_BASE                   0x1000
3351 +#define CSR_REG_SIZE                   0x0800
3352 +#define EEPROM_BASE                    0x0000
3353 +#define EEPROM_SIZE                    0x0110
3354 +#define BBP_BASE                       0x0000
3355 +#define BBP_SIZE                       0x0080
3356 +#define RF_BASE                                0x0004
3357 +#define RF_SIZE                                0x0010
3358 +
3359 +/*
3360 + * Number of TX queues.
3361 + */
3362 +#define NUM_TX_QUEUES                  4
3363 +
3364 +/*
3365 + * PCI registers.
3366 + */
3367 +
3368 +/*
3369 + * E2PROM_CSR: EEPROM control register.
3370 + * RELOAD: Write 1 to reload eeprom content.
3371 + * TYPE: 0: 93c46, 1:93c66.
3372 + * LOAD_STATUS: 1:loading, 0:done.
3373 + */
3374 +#define E2PROM_CSR                     0x0004
3375 +#define E2PROM_CSR_DATA_CLOCK          FIELD32(0x00000001)
3376 +#define E2PROM_CSR_CHIP_SELECT         FIELD32(0x00000002)
3377 +#define E2PROM_CSR_DATA_IN             FIELD32(0x00000004)
3378 +#define E2PROM_CSR_DATA_OUT            FIELD32(0x00000008)
3379 +#define E2PROM_CSR_TYPE                        FIELD32(0x00000030)
3380 +#define E2PROM_CSR_LOAD_STATUS         FIELD32(0x00000040)
3381 +#define E2PROM_CSR_RELOAD              FIELD32(0x00000080)
3382 +
3383 +/*
3384 + * HOST-MCU shared memory
3385 + */
3386 +#define HOST_CMD_CSR                   0x0404
3387 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
3388 +
3389 +/*
3390 + * INT_SOURCE_CSR: Interrupt source register.
3391 + * Write one to clear corresponding bit.
3392 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3393 + */
3394 +#define INT_SOURCE_CSR                 0x0200
3395 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
3396 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
3397 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
3398 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
3399 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
3400 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
3401 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
3402 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
3403 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
3404 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
3405 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
3406 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
3407 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
3408 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
3409 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
3410 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
3411 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
3412 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
3413 +
3414 +/*
3415 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3416 + */
3417 +#define INT_MASK_CSR                   0x0204
3418 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
3419 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
3420 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
3421 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
3422 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
3423 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
3424 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
3425 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
3426 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
3427 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
3428 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
3429 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
3430 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
3431 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
3432 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
3433 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
3434 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
3435 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
3436 +
3437 +/*
3438 + * WPDMA_GLO_CFG
3439 + */
3440 +#define WPDMA_GLO_CFG                  0x0208
3441 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
3442 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
3443 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
3444 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
3445 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
3446 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
3447 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
3448 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
3449 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
3450 +
3451 +/*
3452 + * WPDMA_RST_IDX
3453 + */
3454 +#define WPDMA_RST_IDX                  0x020c
3455 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
3456 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
3457 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
3458 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
3459 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
3460 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
3461 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
3462 +
3463 +/*
3464 + * DELAY_INT_CFG
3465 + */
3466 +#define DELAY_INT_CFG                  0x0210
3467 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
3468 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
3469 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
3470 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
3471 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
3472 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
3473 +
3474 +/*
3475 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3476 + * AIFSN0: AC_BE
3477 + * AIFSN1: AC_BK
3478 + * AIFSN1: AC_VI
3479 + * AIFSN1: AC_VO
3480 + */
3481 +#define WMM_AIFSN_CFG                  0x0214
3482 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3483 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3484 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3485 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3486 +
3487 +/*
3488 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3489 + * CWMIN0: AC_BE
3490 + * CWMIN1: AC_BK
3491 + * CWMIN1: AC_VI
3492 + * CWMIN1: AC_VO
3493 + */
3494 +#define WMM_CWMIN_CFG                  0x0218
3495 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3496 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3497 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3498 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3499 +
3500 +/*
3501 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3502 + * CWMAX0: AC_BE
3503 + * CWMAX1: AC_BK
3504 + * CWMAX1: AC_VI
3505 + * CWMAX1: AC_VO
3506 + */
3507 +#define WMM_CWMAX_CFG                  0x021c
3508 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3509 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3510 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3511 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3512 +
3513 +/*
3514 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3515 + * AC0TXOP: AC_BK in unit of 32us
3516 + * AC1TXOP: AC_BE in unit of 32us
3517 + */
3518 +#define WMM_TXOP0_CFG                  0x0220
3519 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3520 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3521 +
3522 +/*
3523 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3524 + * AC2TXOP: AC_VI in unit of 32us
3525 + * AC3TXOP: AC_VO in unit of 32us
3526 + */
3527 +#define WMM_TXOP1_CFG                  0x0224
3528 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3529 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3530 +
3531 +/*
3532 + * GPIO_CTRL_CFG:
3533 + */
3534 +#define GPIO_CTRL_CFG                  0x0228
3535 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3536 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3537 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3538 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3539 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3540 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3541 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3542 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3543 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3544 +
3545 +/*
3546 + * MCU_CMD_CFG
3547 + */
3548 +#define MCU_CMD_CFG                    0x022c
3549 +
3550 +/*
3551 + * AC_BK register offsets
3552 + */
3553 +#define TX_BASE_PTR0                   0x0230
3554 +#define TX_MAX_CNT0                    0x0234
3555 +#define TX_CTX_IDX0                    0x0238
3556 +#define TX_DTX_IDX0                    0x023c
3557 +
3558 +/*
3559 + * AC_BE register offsets
3560 + */
3561 +#define TX_BASE_PTR1                   0x0240
3562 +#define TX_MAX_CNT1                    0x0244
3563 +#define TX_CTX_IDX1                    0x0248
3564 +#define TX_DTX_IDX1                    0x024c
3565 +
3566 +/*
3567 + * AC_VI register offsets
3568 + */
3569 +#define TX_BASE_PTR2                   0x0250
3570 +#define TX_MAX_CNT2                    0x0254
3571 +#define TX_CTX_IDX2                    0x0258
3572 +#define TX_DTX_IDX2                    0x025c
3573 +
3574 +/*
3575 + * AC_VO register offsets
3576 + */
3577 +#define TX_BASE_PTR3                   0x0260
3578 +#define TX_MAX_CNT3                    0x0264
3579 +#define TX_CTX_IDX3                    0x0268
3580 +#define TX_DTX_IDX3                    0x026c
3581 +
3582 +/*
3583 + * HCCA register offsets
3584 + */
3585 +#define TX_BASE_PTR4                   0x0270
3586 +#define TX_MAX_CNT4                    0x0274
3587 +#define TX_CTX_IDX4                    0x0278
3588 +#define TX_DTX_IDX4                    0x027c
3589 +
3590 +/*
3591 + * MGMT register offsets
3592 + */
3593 +#define TX_BASE_PTR5                   0x0280
3594 +#define TX_MAX_CNT5                    0x0284
3595 +#define TX_CTX_IDX5                    0x0288
3596 +#define TX_DTX_IDX5                    0x028c
3597 +
3598 +/*
3599 + * Queue register offset macros
3600 + */
3601 +#define TX_QUEUE_REG_OFFSET            0x10
3602 +#define TX_BASE_PTR(__x)               TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3603 +#define TX_MAX_CNT(__x)                        TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3604 +#define TX_CTX_IDX(__x)                        TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3605 +#define TX_DTX_IDX(__x)                        TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3606 +
3607 +/*
3608 + * RX register offsets
3609 + */
3610 +#define RX_BASE_PTR                    0x0290
3611 +#define RX_MAX_CNT                     0x0294
3612 +#define RX_CRX_IDX                     0x0298
3613 +#define RX_DRX_IDX                     0x029c
3614 +
3615 +/*
3616 + * PBF_SYS_CTRL
3617 + * HOST_RAM_WRITE: enable Host program ram write selection
3618 + */
3619 +#define PBF_SYS_CTRL                   0x0400
3620 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3621 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3622 +
3623 +/*
3624 + * PBF registers
3625 + * Most are for debug. Driver doesn't touch PBF register.
3626 + */
3627 +#define PBF_CFG                                0x0408
3628 +#define PBF_MAX_PCNT                   0x040c
3629 +#define PBF_CTRL                       0x0410
3630 +#define PBF_INT_STA                    0x0414
3631 +#define PBF_INT_ENA                    0x0418
3632 +
3633 +/*
3634 + * BCN_OFFSET0:
3635 + */
3636 +#define BCN_OFFSET0                    0x042c
3637 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3638 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3639 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3640 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3641 +
3642 +/*
3643 + * BCN_OFFSET1:
3644 + */
3645 +#define BCN_OFFSET1                    0x0430
3646 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3647 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3648 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3649 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3650 +
3651 +/*
3652 + * PBF registers
3653 + * Most are for debug. Driver doesn't touch PBF register.
3654 + */
3655 +#define TXRXQ_PCNT                     0x0438
3656 +#define PBF_DBG                                0x043c
3657 +
3658 +/*
3659 + * RF registers
3660 + */
3661 +#define        RF_CSR_CFG                      0x0500
3662 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
3663 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
3664 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
3665 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
3666 +
3667 +/*
3668 + * MAC Control/Status Registers(CSR).
3669 + * Some values are set in TU, whereas 1 TU == 1024 us.
3670 + */
3671 +
3672 +/*
3673 + * MAC_CSR0: ASIC revision number.
3674 + * ASIC_REV: 0
3675 + * ASIC_VER: 2860
3676 + */
3677 +#define MAC_CSR0                       0x1000
3678 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3679 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3680 +
3681 +/*
3682 + * MAC_SYS_CTRL:
3683 + */
3684 +#define MAC_SYS_CTRL                   0x1004
3685 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3686 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3687 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3688 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3689 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3690 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3691 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3692 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3693 +
3694 +/*
3695 + * MAC_ADDR_DW0: STA MAC register 0
3696 + */
3697 +#define MAC_ADDR_DW0                   0x1008
3698 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3699 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3700 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3701 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3702 +
3703 +/*
3704 + * MAC_ADDR_DW1: STA MAC register 1
3705 + * UNICAST_TO_ME_MASK:
3706 + * Used to mask off bits from byte 5 of the MAC address
3707 + * to determine the UNICAST_TO_ME bit for RX frames.
3708 + * The full mask is complemented by BSS_ID_MASK:
3709 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3710 + */
3711 +#define MAC_ADDR_DW1                   0x100c
3712 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3713 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3714 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3715 +
3716 +/*
3717 + * MAC_BSSID_DW0: BSSID register 0
3718 + */
3719 +#define MAC_BSSID_DW0                  0x1010
3720 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3721 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3722 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3723 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3724 +
3725 +/*
3726 + * MAC_BSSID_DW1: BSSID register 1
3727 + * BSS_ID_MASK:
3728 + *     0: 1-BSSID mode (BSS index = 0)
3729 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3730 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3731 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3732 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3733 + * BSSID. This will make sure that those bits will be ignored
3734 + * when determining the MY_BSS of RX frames.
3735 + */
3736 +#define MAC_BSSID_DW1                  0x1014
3737 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3738 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3739 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3740 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3741 +
3742 +/*
3743 + * MAX_LEN_CFG: Maximum frame length register.
3744 + * MAX_MPDU: rt2860b max 16k bytes
3745 + * MAX_PSDU: Maximum PSDU length
3746 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3747 + */
3748 +#define MAX_LEN_CFG                    0x1018
3749 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3750 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3751 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3752 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3753 +
3754 +/*
3755 + * BBP_CSR_CFG: BBP serial control register
3756 + * VALUE: Register value to program into BBP
3757 + * REG_NUM: Selected BBP register
3758 + * READ_CONTROL: 0 write BBP, 1 read BBP
3759 + * BUSY: ASIC is busy executing BBP commands
3760 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3761 + * BBP_RW_MODE: 0 serial, 1 paralell
3762 + */
3763 +#define BBP_CSR_CFG                    0x101c
3764 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3765 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3766 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3767 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3768 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3769 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3770 +
3771 +/*
3772 + * RF_CSR_CFG0: RF control register
3773 + * REGID_AND_VALUE: Register value to program into RF
3774 + * BITWIDTH: Selected RF register
3775 + * STANDBYMODE: 0 high when standby, 1 low when standby
3776 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3777 + * BUSY: ASIC is busy executing RF commands
3778 + */
3779 +#define RF_CSR_CFG0                    0x1020
3780 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3781 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3782 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3783 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3784 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3785 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3786 +
3787 +/*
3788 + * RF_CSR_CFG1: RF control register
3789 + * REGID_AND_VALUE: Register value to program into RF
3790 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3791 + *        0: 3 system clock cycle (37.5usec)
3792 + *        1: 5 system clock cycle (62.5usec)
3793 + */
3794 +#define RF_CSR_CFG1                    0x1024
3795 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3796 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3797 +
3798 +/*
3799 + * RF_CSR_CFG2: RF control register
3800 + * VALUE: Register value to program into RF
3801 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3802 + *        0: 3 system clock cycle (37.5usec)
3803 + *        1: 5 system clock cycle (62.5usec)
3804 + */
3805 +#define RF_CSR_CFG2                    0x1028
3806 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3807 +
3808 +/*
3809 + * LED_CFG: LED control
3810 + * color LED's:
3811 + *   0: off
3812 + *   1: blinking upon TX2
3813 + *   2: periodic slow blinking
3814 + *   3: always on
3815 + * LED polarity:
3816 + *   0: active low
3817 + *   1: active high
3818 + */
3819 +#define LED_CFG                                0x102c
3820 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3821 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3822 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3823 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3824 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3825 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3826 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3827 +
3828 +/*
3829 + * XIFS_TIME_CFG: MAC timing
3830 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3831 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3832 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3833 + *     when MAC doesn't reference BBP signal BBRXEND
3834 + * EIFS: unit 1us
3835 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3836 + *
3837 + */
3838 +#define XIFS_TIME_CFG                  0x1100
3839 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3840 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3841 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3842 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3843 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3844 +
3845 +/*
3846 + * BKOFF_SLOT_CFG:
3847 + */
3848 +#define BKOFF_SLOT_CFG                 0x1104
3849 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3850 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3851 +
3852 +/*
3853 + * NAV_TIME_CFG:
3854 + */
3855 +#define NAV_TIME_CFG                   0x1108
3856 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3857 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3858 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3859 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3860 +
3861 +/*
3862 + * CH_TIME_CFG: count as channel busy
3863 + */
3864 +#define CH_TIME_CFG                    0x110c
3865 +
3866 +/*
3867 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3868 + */
3869 +#define PBF_LIFE_TIMER                 0x1110
3870 +
3871 +/*
3872 + * BCN_TIME_CFG:
3873 + * BEACON_INTERVAL: in unit of 1/16 TU
3874 + * TSF_TICKING: Enable TSF auto counting
3875 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3876 + * BEACON_GEN: Enable beacon generator
3877 + */
3878 +#define BCN_TIME_CFG                   0x1114
3879 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3880 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3881 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3882 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3883 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3884 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3885 +
3886 +/*
3887 + * TBTT_SYNC_CFG:
3888 + */
3889 +#define TBTT_SYNC_CFG                  0x1118
3890 +
3891 +/*
3892 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3893 + */
3894 +#define TSF_TIMER_DW0                  0x111c
3895 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3896 +
3897 +/*
3898 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3899 + */
3900 +#define TSF_TIMER_DW1                  0x1120
3901 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3902 +
3903 +/*
3904 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3905 + */
3906 +#define TBTT_TIMER                     0x1124
3907 +
3908 +/*
3909 + * INT_TIMER_CFG:
3910 + */
3911 +#define INT_TIMER_CFG                  0x1128
3912 +
3913 +/*
3914 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3915 + */
3916 +#define INT_TIMER_EN                   0x112c
3917 +
3918 +/*
3919 + * CH_IDLE_STA: channel idle time
3920 + */
3921 +#define CH_IDLE_STA                    0x1130
3922 +
3923 +/*
3924 + * CH_BUSY_STA: channel busy time
3925 + */
3926 +#define CH_BUSY_STA                    0x1134
3927 +
3928 +/*
3929 + * MAC_STATUS_CFG:
3930 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3931 + *     if 1 or higher one of the 2 registers is busy.
3932 + */
3933 +#define MAC_STATUS_CFG                 0x1200
3934 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3935 +
3936 +/*
3937 + * PWR_PIN_CFG:
3938 + */
3939 +#define PWR_PIN_CFG                    0x1204
3940 +
3941 +/*
3942 + * AUTOWAKEUP_CFG: Manual power control / status register
3943 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3944 + * AUTOWAKE: 0:sleep, 1:awake
3945 + */
3946 +#define AUTOWAKEUP_CFG                 0x1208
3947 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3948 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3949 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3950 +
3951 +/*
3952 + * EDCA_AC0_CFG:
3953 + */
3954 +#define EDCA_AC0_CFG                   0x1300
3955 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
3956 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3957 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3958 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3959 +
3960 +/*
3961 + * EDCA_AC1_CFG:
3962 + */
3963 +#define EDCA_AC1_CFG                   0x1304
3964 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
3965 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3966 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3967 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3968 +
3969 +/*
3970 + * EDCA_AC2_CFG:
3971 + */
3972 +#define EDCA_AC2_CFG                   0x1308
3973 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
3974 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3975 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3976 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3977 +
3978 +/*
3979 + * EDCA_AC3_CFG:
3980 + */
3981 +#define EDCA_AC3_CFG                   0x130c
3982 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
3983 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3984 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3985 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3986 +
3987 +/*
3988 + * EDCA_TID_AC_MAP:
3989 + */
3990 +#define EDCA_TID_AC_MAP                        0x1310
3991 +
3992 +/*
3993 + * TX_PWR_CFG_0:
3994 + */
3995 +#define TX_PWR_CFG_0                   0x1314
3996 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3997 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3998 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3999 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
4000 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
4001 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
4002 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
4003 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
4004 +
4005 +/*
4006 + * TX_PWR_CFG_1:
4007 + */
4008 +#define TX_PWR_CFG_1                   0x1318
4009 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
4010 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
4011 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
4012 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
4013 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
4014 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
4015 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
4016 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
4017 +
4018 +/*
4019 + * TX_PWR_CFG_2:
4020 + */
4021 +#define TX_PWR_CFG_2                   0x131c
4022 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
4023 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
4024 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
4025 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
4026 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
4027 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
4028 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
4029 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
4030 +
4031 +/*
4032 + * TX_PWR_CFG_3:
4033 + */
4034 +#define TX_PWR_CFG_3                   0x1320
4035 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
4036 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
4037 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
4038 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
4039 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
4040 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
4041 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
4042 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
4043 +
4044 +/*
4045 + * TX_PWR_CFG_4:
4046 + */
4047 +#define TX_PWR_CFG_4                   0x1324
4048 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
4049 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
4050 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
4051 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
4052 +
4053 +/*
4054 + * TX_PIN_CFG:
4055 + */
4056 +#define TX_PIN_CFG                     0x1328
4057 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
4058 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
4059 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
4060 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
4061 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
4062 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
4063 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
4064 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
4065 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
4066 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
4067 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
4068 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
4069 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
4070 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
4071 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
4072 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
4073 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
4074 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
4075 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
4076 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
4077 +
4078 +/*
4079 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
4080 + */
4081 +#define TX_BAND_CFG                    0x132c
4082 +#define TX_BAND_CFG_HT40_PLUS          FIELD32(0x00000001)
4083 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
4084 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
4085 +
4086 +/*
4087 + * TX_SW_CFG0:
4088 + */
4089 +#define TX_SW_CFG0                     0x1330
4090 +
4091 +/*
4092 + * TX_SW_CFG1:
4093 + */
4094 +#define TX_SW_CFG1                     0x1334
4095 +
4096 +/*
4097 + * TX_SW_CFG2:
4098 + */
4099 +#define TX_SW_CFG2                     0x1338
4100 +
4101 +/*
4102 + * TXOP_THRES_CFG:
4103 + */
4104 +#define TXOP_THRES_CFG                 0x133c
4105 +
4106 +/*
4107 + * TXOP_CTRL_CFG:
4108 + */
4109 +#define TXOP_CTRL_CFG                  0x1340
4110 +
4111 +/*
4112 + * TX_RTS_CFG:
4113 + * RTS_THRES: unit:byte
4114 + * RTS_FBK_EN: enable rts rate fallback
4115 + */
4116 +#define TX_RTS_CFG                     0x1344
4117 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
4118 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
4119 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
4120 +
4121 +/*
4122 + * TX_TIMEOUT_CFG:
4123 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
4124 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
4125 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
4126 + *                it is recommended that:
4127 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
4128 + */
4129 +#define TX_TIMEOUT_CFG                 0x1348
4130 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
4131 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
4132 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
4133 +
4134 +/*
4135 + * TX_RTY_CFG:
4136 + * SHORT_RTY_LIMIT: short retry limit
4137 + * LONG_RTY_LIMIT: long retry limit
4138 + * LONG_RTY_THRE: Long retry threshoold
4139 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
4140 + *                   0:expired by retry limit, 1: expired by mpdu life timer
4141 + * AGG_RTY_MODE: Aggregate MPDU retry mode
4142 + *               0:expired by retry limit, 1: expired by mpdu life timer
4143 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
4144 + */
4145 +#define TX_RTY_CFG                     0x134c
4146 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
4147 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
4148 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
4149 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
4150 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
4151 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
4152 +
4153 +/*
4154 + * TX_LINK_CFG:
4155 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
4156 + * MFB_ENABLE: TX apply remote MFB 1:enable
4157 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
4158 + *                     0: not apply remote remote unsolicit (MFS=7)
4159 + * TX_MRQ_EN: MCS request TX enable
4160 + * TX_RDG_EN: RDG TX enable
4161 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
4162 + * REMOTE_MFB: remote MCS feedback
4163 + * REMOTE_MFS: remote MCS feedback sequence number
4164 + */
4165 +#define TX_LINK_CFG                    0x1350
4166 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
4167 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
4168 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
4169 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
4170 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
4171 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
4172 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
4173 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
4174 +
4175 +/*
4176 + * HT_FBK_CFG0:
4177 + */
4178 +#define HT_FBK_CFG0                    0x1354
4179 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
4180 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
4181 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
4182 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
4183 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
4184 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
4185 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
4186 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
4187 +
4188 +/*
4189 + * HT_FBK_CFG1:
4190 + */
4191 +#define HT_FBK_CFG1                    0x1358
4192 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
4193 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
4194 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
4195 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
4196 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
4197 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
4198 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
4199 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
4200 +
4201 +/*
4202 + * LG_FBK_CFG0:
4203 + */
4204 +#define LG_FBK_CFG0                    0x135c
4205 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
4206 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
4207 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
4208 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
4209 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
4210 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
4211 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
4212 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
4213 +
4214 +/*
4215 + * LG_FBK_CFG1:
4216 + */
4217 +#define LG_FBK_CFG1                    0x1360
4218 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
4219 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
4220 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
4221 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
4222 +
4223 +/*
4224 + * CCK_PROT_CFG: CCK Protection
4225 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4226 + * PROTECT_CTRL: Protection control frame type for CCK TX
4227 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
4228 + * PROTECT_NAV: TXOP protection type for CCK TX
4229 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4230 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4231 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4232 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4233 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4234 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4235 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4236 + * RTS_TH_EN: RTS threshold enable on CCK TX
4237 + */
4238 +#define CCK_PROT_CFG                   0x1364
4239 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
4240 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
4241 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
4242 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
4243 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
4244 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
4245 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
4246 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
4247 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
4248 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
4249 +
4250 +/*
4251 + * OFDM_PROT_CFG: OFDM Protection
4252 + */
4253 +#define OFDM_PROT_CFG                  0x1368
4254 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4255 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4256 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4257 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4258 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4259 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4260 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4261 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4262 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4263 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4264 +
4265 +/*
4266 + * MM20_PROT_CFG: MM20 Protection
4267 + */
4268 +#define MM20_PROT_CFG                  0x136c
4269 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4270 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4271 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4272 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4273 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4274 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4275 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4276 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4277 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4278 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4279 +
4280 +/*
4281 + * MM40_PROT_CFG: MM40 Protection
4282 + */
4283 +#define MM40_PROT_CFG                  0x1370
4284 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4285 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4286 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4287 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4288 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4289 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4290 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4291 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4292 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4293 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4294 +
4295 +/*
4296 + * GF20_PROT_CFG: GF20 Protection
4297 + */
4298 +#define GF20_PROT_CFG                  0x1374
4299 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4300 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4301 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4302 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4303 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4304 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4305 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4306 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4307 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4308 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4309 +
4310 +/*
4311 + * GF40_PROT_CFG: GF40 Protection
4312 + */
4313 +#define GF40_PROT_CFG                  0x1378
4314 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4315 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4316 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4317 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4318 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4319 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4320 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4321 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4322 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4323 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4324 +
4325 +/*
4326 + * EXP_CTS_TIME:
4327 + */
4328 +#define EXP_CTS_TIME                   0x137c
4329 +
4330 +/*
4331 + * EXP_ACK_TIME:
4332 + */
4333 +#define EXP_ACK_TIME                   0x1380
4334 +
4335 +/*
4336 + * RX_FILTER_CFG: RX configuration register.
4337 + */
4338 +#define RX_FILTER_CFG                  0x1400
4339 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
4340 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
4341 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
4342 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4343 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
4344 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
4345 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
4346 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
4347 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
4348 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
4349 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
4350 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
4351 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
4352 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
4353 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
4354 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
4355 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
4356 +
4357 +/*
4358 + * AUTO_RSP_CFG:
4359 + * AUTORESPONDER: 0: disable, 1: enable
4360 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4361 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4362 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4363 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4364 + * DUAL_CTS_EN: Power bit value in control frame
4365 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4366 + */
4367 +#define AUTO_RSP_CFG                   0x1404
4368 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
4369 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
4370 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
4371 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
4372 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
4373 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
4374 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
4375 +
4376 +/*
4377 + * LEGACY_BASIC_RATE:
4378 + */
4379 +#define LEGACY_BASIC_RATE              0x1408
4380 +
4381 +/*
4382 + * HT_BASIC_RATE:
4383 + */
4384 +#define HT_BASIC_RATE                  0x140c
4385 +
4386 +/*
4387 + * HT_CTRL_CFG:
4388 + */
4389 +#define HT_CTRL_CFG                    0x1410
4390 +
4391 +/*
4392 + * SIFS_COST_CFG:
4393 + */
4394 +#define SIFS_COST_CFG                  0x1414
4395 +
4396 +/*
4397 + * RX_PARSER_CFG:
4398 + * Set NAV for all received frames
4399 + */
4400 +#define RX_PARSER_CFG                  0x1418
4401 +
4402 +/*
4403 + * TX_SEC_CNT0:
4404 + */
4405 +#define TX_SEC_CNT0                    0x1500
4406 +
4407 +/*
4408 + * RX_SEC_CNT0:
4409 + */
4410 +#define RX_SEC_CNT0                    0x1504
4411 +
4412 +/*
4413 + * CCMP_FC_MUTE:
4414 + */
4415 +#define CCMP_FC_MUTE                   0x1508
4416 +
4417 +/*
4418 + * TXOP_HLDR_ADDR0:
4419 + */
4420 +#define TXOP_HLDR_ADDR0                        0x1600
4421 +
4422 +/*
4423 + * TXOP_HLDR_ADDR1:
4424 + */
4425 +#define TXOP_HLDR_ADDR1                        0x1604
4426 +
4427 +/*
4428 + * TXOP_HLDR_ET:
4429 + */
4430 +#define TXOP_HLDR_ET                   0x1608
4431 +
4432 +/*
4433 + * QOS_CFPOLL_RA_DW0:
4434 + */
4435 +#define QOS_CFPOLL_RA_DW0              0x160c
4436 +
4437 +/*
4438 + * QOS_CFPOLL_RA_DW1:
4439 + */
4440 +#define QOS_CFPOLL_RA_DW1              0x1610
4441 +
4442 +/*
4443 + * QOS_CFPOLL_QC:
4444 + */
4445 +#define QOS_CFPOLL_QC                  0x1614
4446 +
4447 +/*
4448 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4449 + */
4450 +#define RX_STA_CNT0                    0x1700
4451 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
4452 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
4453 +
4454 +/*
4455 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4456 + */
4457 +#define RX_STA_CNT1                    0x1704
4458 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
4459 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
4460 +
4461 +/*
4462 + * RX_STA_CNT2:
4463 + */
4464 +#define RX_STA_CNT2                    0x1708
4465 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
4466 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
4467 +
4468 +/*
4469 + * TX_STA_CNT0: TX Beacon count
4470 + */
4471 +#define TX_STA_CNT0                    0x170c
4472 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
4473 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
4474 +
4475 +/*
4476 + * TX_STA_CNT1: TX tx count
4477 + */
4478 +#define TX_STA_CNT1                    0x1710
4479 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
4480 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
4481 +
4482 +/*
4483 + * TX_STA_CNT2: TX tx count
4484 + */
4485 +#define TX_STA_CNT2                    0x1714
4486 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
4487 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
4488 +
4489 +/*
4490 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4491 + */
4492 +#define TX_STA_FIFO                    0x1718
4493 +#define TX_STA_FIFO_VALID              FIELD32(0x00000001)
4494 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
4495 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
4496 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4497 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4498 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4499 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4500 +
4501 +/*
4502 + * TX_AGG_CNT: Debug counter
4503 + */
4504 +#define TX_AGG_CNT                     0x171c
4505 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4506 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4507 +
4508 +/*
4509 + * TX_AGG_CNT0:
4510 + */
4511 +#define TX_AGG_CNT0                    0x1720
4512 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4513 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4514 +
4515 +/*
4516 + * TX_AGG_CNT1:
4517 + */
4518 +#define TX_AGG_CNT1                    0x1724
4519 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4520 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4521 +
4522 +/*
4523 + * TX_AGG_CNT2:
4524 + */
4525 +#define TX_AGG_CNT2                    0x1728
4526 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4527 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4528 +
4529 +/*
4530 + * TX_AGG_CNT3:
4531 + */
4532 +#define TX_AGG_CNT3                    0x172c
4533 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4534 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4535 +
4536 +/*
4537 + * TX_AGG_CNT4:
4538 + */
4539 +#define TX_AGG_CNT4                    0x1730
4540 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4541 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4542 +
4543 +/*
4544 + * TX_AGG_CNT5:
4545 + */
4546 +#define TX_AGG_CNT5                    0x1734
4547 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4548 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4549 +
4550 +/*
4551 + * TX_AGG_CNT6:
4552 + */
4553 +#define TX_AGG_CNT6                    0x1738
4554 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4555 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4556 +
4557 +/*
4558 + * TX_AGG_CNT7:
4559 + */
4560 +#define TX_AGG_CNT7                    0x173c
4561 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4562 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4563 +
4564 +/*
4565 + * MPDU_DENSITY_CNT:
4566 + * TX_ZERO_DEL: TX zero length delimiter count
4567 + * RX_ZERO_DEL: RX zero length delimiter count
4568 + */
4569 +#define MPDU_DENSITY_CNT               0x1740
4570 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4571 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4572 +
4573 +/*
4574 + * Security key table memory.
4575 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4576 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4577 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4578 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4579 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4580 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4581 + */
4582 +#define MAC_WCID_BASE                  0x1800
4583 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4584 +#define MAC_IVEIV_TABLE_BASE           0x6000
4585 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4586 +#define SHARED_KEY_TABLE_BASE          0x6c00
4587 +#define SHARED_KEY_MODE_BASE           0x7000
4588 +
4589 +#define MAC_WCID_ENTRY(__idx) \
4590 +       ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4591 +#define PAIRWISE_KEY_ENTRY(__idx) \
4592 +       ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4593 +#define MAC_IVEIV_ENTRY(__idx) \
4594 +       ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4595 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4596 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4597 +#define SHARED_KEY_ENTRY(__idx) \
4598 +       ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4599 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4600 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4601 +
4602 +struct mac_wcid_entry {
4603 +       u8 mac[6];
4604 +       u8 reserved[2];
4605 +} __attribute__ ((packed));
4606 +
4607 +struct hw_key_entry {
4608 +       u8 key[16];
4609 +       u8 tx_mic[8];
4610 +       u8 rx_mic[8];
4611 +} __attribute__ ((packed));
4612 +
4613 +struct mac_iveiv_entry {
4614 +       u8 iv[8];
4615 +} __attribute__ ((packed));
4616 +
4617 +/*
4618 + * MAC_WCID_ATTRIBUTE:
4619 + */
4620 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4621 +#define MAC_WCID_ATTRIBUTE_CIPHER      FIELD32(0x0000000e)
4622 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4623 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4624 +
4625 +/*
4626 + * SHARED_KEY_MODE:
4627 + */
4628 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4629 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4630 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4631 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4632 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4633 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4634 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4635 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4636 +
4637 +/*
4638 + * HOST-MCU communication
4639 + */
4640 +
4641 +/*
4642 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4643 + */
4644 +#define H2M_MAILBOX_CSR                        0x7010
4645 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4646 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4647 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4648 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4649 +
4650 +/*
4651 + * H2M_MAILBOX_CID:
4652 + */
4653 +#define H2M_MAILBOX_CID                        0x7014
4654 +#define H2M_MAILBOX_CID_CMD0           FIELD32(0x000000ff)
4655 +#define H2M_MAILBOX_CID_CMD1           FIELD32(0x0000ff00)
4656 +#define H2M_MAILBOX_CID_CMD2           FIELD32(0x00ff0000)
4657 +#define H2M_MAILBOX_CID_CMD3           FIELD32(0xff000000)
4658 +
4659 +/*
4660 + * H2M_MAILBOX_STATUS:
4661 + */
4662 +#define H2M_MAILBOX_STATUS             0x701c
4663 +
4664 +/*
4665 + * H2M_INT_SRC:
4666 + */
4667 +#define H2M_INT_SRC                    0x7024
4668 +
4669 +/*
4670 + * H2M_BBP_AGENT:
4671 + */
4672 +#define H2M_BBP_AGENT                  0x7028
4673 +
4674 +/*
4675 + * MCU_LEDCS: LED control for MCU Mailbox.
4676 + */
4677 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4678 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4679 +
4680 +/*
4681 + * HW_CS_CTS_BASE:
4682 + * Carrier-sense CTS frame base address.
4683 + * It's where mac stores carrier-sense frame for carrier-sense function.
4684 + */
4685 +#define HW_CS_CTS_BASE                 0x7700
4686 +
4687 +/*
4688 + * HW_DFS_CTS_BASE:
4689 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4690 + */
4691 +#define HW_DFS_CTS_BASE                        0x7780
4692 +
4693 +/*
4694 + * TXRX control registers - base address 0x3000
4695 + */
4696 +
4697 +/*
4698 + * TXRX_CSR1:
4699 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4700 + */
4701 +#define TXRX_CSR1                      0x77d0
4702 +
4703 +/*
4704 + * HW_DEBUG_SETTING_BASE:
4705 + * since NULL frame won't be that long (256 byte)
4706 + * We steal 16 tail bytes to save debugging settings
4707 + */
4708 +#define HW_DEBUG_SETTING_BASE          0x77f0
4709 +#define HW_DEBUG_SETTING_BASE2         0x7770
4710 +
4711 +/*
4712 + * HW_BEACON_BASE
4713 + * In order to support maximum 8 MBSS and its maximum length
4714 + * is 512 bytes for each beacon
4715 + * Three section discontinue memory segments will be used.
4716 + * 1. The original region for BCN 0~3
4717 + * 2. Extract memory from FCE table for BCN 4~5
4718 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4719 + *    It occupied those memory of wcid 238~253 for BCN 6
4720 + *    and wcid 222~237 for BCN 7
4721 + *
4722 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4723 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4724 + */
4725 +#define HW_BEACON_BASE0                        0x7800
4726 +#define HW_BEACON_BASE1                        0x7a00
4727 +#define HW_BEACON_BASE2                        0x7c00
4728 +#define HW_BEACON_BASE3                        0x7e00
4729 +#define HW_BEACON_BASE4                        0x7200
4730 +#define HW_BEACON_BASE5                        0x7400
4731 +#define HW_BEACON_BASE6                        0x5dc0
4732 +#define HW_BEACON_BASE7                        0x5bc0
4733 +
4734 +#define HW_BEACON_OFFSET(__index) \
4735 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4736 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4737 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4738 +
4739 +/*
4740 + * 8051 firmware image.
4741 + */
4742 +#define FIRMWARE_RT2860                        "rt2860.bin"
4743 +#define FIRMWARE_IMAGE_BASE            0x2000
4744 +
4745 +/*
4746 + * BBP registers.
4747 + * The wordsize of the BBP is 8 bits.
4748 + */
4749 +
4750 +/*
4751 + * BBP 1: TX Antenna
4752 + */
4753 +#define BBP1_TX_POWER                  FIELD8(0x07)
4754 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4755 +
4756 +/*
4757 + * BBP 3: RX Antenna
4758 + */
4759 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4760 +#define BBP3_HT40_PLUS                 FIELD8(0x20)
4761 +
4762 +/*
4763 + * BBP 4: Bandwidth
4764 + */
4765 +#define BBP4_TX_BF                     FIELD8(0x01)
4766 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
4767 +
4768 +/*
4769 + * RFCSR registers
4770 + * The wordsize of the RFCSR is 8 bits.
4771 + */
4772 +
4773 +/*
4774 + * RFCSR 6:
4775 + */
4776 +#define RFCSR6_R                       FIELD8(0x03)
4777 +
4778 +/*
4779 + * RFCSR 7:
4780 + */
4781 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
4782 +
4783 +/*
4784 + * RFCSR 12:
4785 + */
4786 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
4787 +
4788 +/*
4789 + * RFCSR 22:
4790 + */
4791 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
4792 +
4793 +/*
4794 + * RFCSR 23:
4795 + */
4796 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
4797 +
4798 +/*
4799 + * RFCSR 30:
4800 + */
4801 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
4802 +
4803 +/*
4804 + * RF registers
4805 + */
4806 +
4807 +/*
4808 + * RF 2
4809 + */
4810 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4811 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4812 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4813 +
4814 +/*
4815 + * RF 3
4816 + */
4817 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4818 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4819 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4820 +
4821 +/*
4822 + * RF 4
4823 + */
4824 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4825 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4826 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4827 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4828 +#define RF4_HT40                       FIELD32(0x00200000)
4829 +
4830 +/*
4831 + * EEPROM content.
4832 + * The wordsize of the EEPROM is 16 bits.
4833 + */
4834 +
4835 +/*
4836 + * EEPROM Version
4837 + */
4838 +#define EEPROM_VERSION                 0x0001
4839 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4840 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4841 +
4842 +/*
4843 + * HW MAC address.
4844 + */
4845 +#define EEPROM_MAC_ADDR_0              0x0002
4846 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4847 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4848 +#define EEPROM_MAC_ADDR_1              0x0003
4849 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4850 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4851 +#define EEPROM_MAC_ADDR_2              0x0004
4852 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4853 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4854 +
4855 +/*
4856 + * EEPROM ANTENNA config
4857 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4858 + * TXPATH: 1: 1T, 2: 2T
4859 + */
4860 +#define        EEPROM_ANTENNA                  0x001a
4861 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4862 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4863 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4864 +
4865 +/*
4866 + * EEPROM NIC config
4867 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4868 + */
4869 +#define        EEPROM_NIC                      0x001b
4870 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4871 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4872 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4873 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4874 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4875 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4876 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4877 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4878 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4879 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4880 +
4881 +/*
4882 + * EEPROM frequency
4883 + */
4884 +#define        EEPROM_FREQ                     0x001d
4885 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4886 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4887 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4888 +
4889 +/*
4890 + * EEPROM LED
4891 + * POLARITY_RDY_G: Polarity RDY_G setting.
4892 + * POLARITY_RDY_A: Polarity RDY_A setting.
4893 + * POLARITY_ACT: Polarity ACT setting.
4894 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4895 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4896 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4897 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4898 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4899 + * LED_MODE: Led mode.
4900 + */
4901 +#define EEPROM_LED1                    0x001e
4902 +#define EEPROM_LED2                    0x001f
4903 +#define EEPROM_LED3                    0x0020
4904 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4905 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4906 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4907 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4908 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4909 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4910 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4911 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4912 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4913 +
4914 +/*
4915 + * EEPROM LNA
4916 + */
4917 +#define EEPROM_LNA                     0x0022
4918 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4919 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4920 +
4921 +/*
4922 + * EEPROM RSSI BG offset
4923 + */
4924 +#define EEPROM_RSSI_BG                 0x0023
4925 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4926 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4927 +
4928 +/*
4929 + * EEPROM RSSI BG2 offset
4930 + */
4931 +#define EEPROM_RSSI_BG2                        0x0024
4932 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4933 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4934 +
4935 +/*
4936 + * EEPROM RSSI A offset
4937 + */
4938 +#define EEPROM_RSSI_A                  0x0025
4939 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4940 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4941 +
4942 +/*
4943 + * EEPROM RSSI A2 offset
4944 + */
4945 +#define EEPROM_RSSI_A2                 0x0026
4946 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4947 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4948 +
4949 +/*
4950 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4951 + *     This is delta in 40MHZ.
4952 + * VALUE: Tx Power dalta value (MAX=4)
4953 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4954 + * TXPOWER: Enable:
4955 + */
4956 +#define EEPROM_TXPOWER_DELTA           0x0028
4957 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4958 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4959 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4960 +
4961 +/*
4962 + * EEPROM TXPOWER 802.11BG
4963 + */
4964 +#define        EEPROM_TXPOWER_BG1              0x0029
4965 +#define        EEPROM_TXPOWER_BG2              0x0030
4966 +#define EEPROM_TXPOWER_BG_SIZE         7
4967 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4968 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4969 +
4970 +/*
4971 + * EEPROM TXPOWER 802.11A
4972 + */
4973 +#define EEPROM_TXPOWER_A1              0x003c
4974 +#define EEPROM_TXPOWER_A2              0x0053
4975 +#define EEPROM_TXPOWER_A_SIZE          6
4976 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4977 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4978 +
4979 +/*
4980 + * EEPROM TXpower byrate: 20MHZ power
4981 + */
4982 +#define EEPROM_TXPOWER_BYRATE          0x006f
4983 +
4984 +/*
4985 + * EEPROM BBP.
4986 + */
4987 +#define        EEPROM_BBP_START                0x0078
4988 +#define EEPROM_BBP_SIZE                        16
4989 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4990 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4991 +
4992 +/*
4993 + * MCU mailbox commands.
4994 + */
4995 +#define MCU_SLEEP                      0x30
4996 +#define MCU_WAKEUP                     0x31
4997 +#define MCU_RADIO_OFF                  0x35
4998 +#define MCU_CURRENT                    0x36
4999 +#define MCU_LED                                0x50
5000 +#define MCU_LED_STRENGTH               0x51
5001 +#define MCU_LED_1                      0x52
5002 +#define MCU_LED_2                      0x53
5003 +#define MCU_LED_3                      0x54
5004 +#define MCU_RADAR                      0x60
5005 +#define MCU_BOOT_SIGNAL                        0x72
5006 +#define MCU_BBP_SIGNAL                 0x80
5007 +#define MCU_POWER_SAVE                 0x83
5008 +
5009 +/*
5010 + * MCU mailbox tokens
5011 + */
5012 +#define TOKEN_WAKUP                    3
5013 +
5014 +/*
5015 + * DMA descriptor defines.
5016 + */
5017 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
5018 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
5019 +#define RXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
5020 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
5021 +
5022 +/*
5023 + * TX descriptor format for TX, PRIO and Beacon Ring.
5024 + */
5025 +
5026 +/*
5027 + * Word0
5028 + */
5029 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
5030 +
5031 +/*
5032 + * Word1
5033 + */
5034 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
5035 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
5036 +#define TXD_W1_BURST                   FIELD32(0x00008000)
5037 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
5038 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
5039 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
5040 +
5041 +/*
5042 + * Word2
5043 + */
5044 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
5045 +
5046 +/*
5047 + * Word3
5048 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
5049 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
5050 + *       0:MGMT, 1:HCCA 2:EDCA
5051 + */
5052 +#define TXD_W3_WIV                     FIELD32(0x01000000)
5053 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
5054 +#define TXD_W3_TCO                     FIELD32(0x20000000)
5055 +#define TXD_W3_UCO                     FIELD32(0x40000000)
5056 +#define TXD_W3_ICO                     FIELD32(0x80000000)
5057 +
5058 +/*
5059 + * TX WI structure
5060 + */
5061 +
5062 +/*
5063 + * Word0
5064 + * FRAG: 1 To inform TKIP engine this is a fragment.
5065 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
5066 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
5067 + * BW: Channel bandwidth 20MHz or 40 MHz
5068 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
5069 + */
5070 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
5071 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
5072 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
5073 +#define TXWI_W0_TS                     FIELD32(0x00000008)
5074 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
5075 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
5076 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
5077 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
5078 +#define TXWI_W0_BW                     FIELD32(0x00800000)
5079 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
5080 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
5081 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
5082 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
5083 +
5084 +/*
5085 + * Word1
5086 + */
5087 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
5088 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
5089 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
5090 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
5091 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
5092 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
5093 +
5094 +/*
5095 + * Word2
5096 + */
5097 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
5098 +
5099 +/*
5100 + * Word3
5101 + */
5102 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
5103 +
5104 +/*
5105 + * RX descriptor format for RX Ring.
5106 + */
5107 +
5108 +/*
5109 + * Word0
5110 + */
5111 +#define RXD_W0_SDP0                    FIELD32(0xffffffff)
5112 +
5113 +/*
5114 + * Word1
5115 + */
5116 +#define RXD_W1_SDL1                    FIELD32(0x00003fff)
5117 +#define RXD_W1_SDL0                    FIELD32(0x3fff0000)
5118 +#define RXD_W1_LS0                     FIELD32(0x40000000)
5119 +#define RXD_W1_DMA_DONE                        FIELD32(0x80000000)
5120 +
5121 +/*
5122 + * Word2
5123 + */
5124 +#define RXD_W2_SDP1                    FIELD32(0xffffffff)
5125 +
5126 +/*
5127 + * Word3
5128 + * AMSDU: RX with 802.3 header, not 802.11 header.
5129 + * DECRYPTED: This frame is being decrypted.
5130 + */
5131 +#define RXD_W3_BA                      FIELD32(0x00000001)
5132 +#define RXD_W3_DATA                    FIELD32(0x00000002)
5133 +#define RXD_W3_NULLDATA                        FIELD32(0x00000004)
5134 +#define RXD_W3_FRAG                    FIELD32(0x00000008)
5135 +#define RXD_W3_UNICAST_TO_ME           FIELD32(0x00000010)
5136 +#define RXD_W3_MULTICAST               FIELD32(0x00000020)
5137 +#define RXD_W3_BROADCAST               FIELD32(0x00000040)
5138 +#define RXD_W3_MY_BSS                  FIELD32(0x00000080)
5139 +#define RXD_W3_CRC_ERROR               FIELD32(0x00000100)
5140 +#define RXD_W3_CIPHER_ERROR            FIELD32(0x00000600)
5141 +#define RXD_W3_AMSDU                   FIELD32(0x00000800)
5142 +#define RXD_W3_HTC                     FIELD32(0x00001000)
5143 +#define RXD_W3_RSSI                    FIELD32(0x00002000)
5144 +#define RXD_W3_L2PAD                   FIELD32(0x00004000)
5145 +#define RXD_W3_AMPDU                   FIELD32(0x00008000)
5146 +#define RXD_W3_DECRYPTED               FIELD32(0x00010000)
5147 +#define RXD_W3_PLCP_SIGNAL             FIELD32(0x00020000)
5148 +#define RXD_W3_PLCP_RSSI               FIELD32(0x00040000)
5149 +
5150 +/*
5151 + * RX WI structure
5152 + */
5153 +
5154 +/*
5155 + * Word0
5156 + */
5157 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
5158 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
5159 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
5160 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
5161 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
5162 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
5163 +
5164 +/*
5165 + * Word1
5166 + */
5167 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
5168 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
5169 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
5170 +#define RXWI_W1_BW                     FIELD32(0x00800000)
5171 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
5172 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
5173 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
5174 +
5175 +/*
5176 + * Word2
5177 + */
5178 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
5179 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
5180 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
5181 +
5182 +/*
5183 + * Word3
5184 + */
5185 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
5186 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
5187 +
5188 +/*
5189 + * Macros for converting txpower from EEPROM to mac80211 value
5190 + * and from mac80211 value to register value.
5191 + */
5192 +#define MIN_G_TXPOWER  0
5193 +#define MIN_A_TXPOWER  -7
5194 +#define MAX_G_TXPOWER  31
5195 +#define MAX_A_TXPOWER  15
5196 +#define DEFAULT_TXPOWER        5
5197 +
5198 +#define TXPOWER_G_FROM_DEV(__txpower) \
5199 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5200 +
5201 +#define TXPOWER_G_TO_DEV(__txpower) \
5202 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
5203 +
5204 +#define TXPOWER_A_FROM_DEV(__txpower) \
5205 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5206 +
5207 +#define TXPOWER_A_TO_DEV(__txpower) \
5208 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5209 +
5210 +#endif /* RT2800PCI_H */
5211 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5212 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5213 @@ -158,6 +158,12 @@ struct rt2x00_chip {
5214  #define RT2561         0x0302
5215  #define RT2661         0x0401
5216  #define RT2571         0x1300
5217 +#define RT2860         0x0601  /* 2.4GHz PCI/CB */
5218 +#define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
5219 +#define RT2890         0x0701  /* 2.4GHz PCIe */
5220 +#define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
5221 +#define RT2880         0x2880  /* WSOC */
5222 +#define RT3052         0x3052  /* WSOC */
5223  #define RT2870         0x1600
5224
5225         u16 rf;