package/mac80211/patches/302-rt2x00-Implement-support-for-rt2800pci.patch

   1 From 67432230daedc23f808b79173703e27675fd0659 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Sun, 26 Apr 2009 15:54:03 +0200
   4 Subject: [PATCH 2/4] rt2x00: Implement support for rt2800pci
   5
   6 Add support for the rt2800pci chipset.
   7
   8 Includes various patches from Mattias, Mark, Felix and Xose.
   9
  10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
  11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
  13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  15 ---
  16  drivers/net/wireless/rt2x00/Kconfig     |   26 +
  17  drivers/net/wireless/rt2x00/Makefile    |    1 +
  18  drivers/net/wireless/rt2x00/rt2800pci.c | 3245 +++++++++++++++++++++++++++++++
  19  drivers/net/wireless/rt2x00/rt2800pci.h | 1927 ++++++++++++++++++
  20  drivers/net/wireless/rt2x00/rt2x00.h    |    6 +
  21  5 files changed, 5205 insertions(+), 0 deletions(-)
  22  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
  23  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
  24
  25 --- a/drivers/net/wireless/rt2x00/Makefile
  26 +++ b/drivers/net/wireless/rt2x00/Makefile
  27 @@ -17,6 +17,7 @@ obj-$(CONFIG_RT2X00_LIB_USB)          += rt2x00u
  28  obj-$(CONFIG_RT2400PCI)                        += rt2400pci.o
  29  obj-$(CONFIG_RT2500PCI)                        += rt2500pci.o
  30  obj-$(CONFIG_RT61PCI)                  += rt61pci.o
  31 +obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  32  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  33  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  34  obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  35 --- /dev/null
  36 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  37 @@ -0,0 +1,3245 @@
  38 +/*
  39 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  40 +       <http://rt2x00.serialmonkey.com>
  41 +
  42 +       This program is free software; you can redistribute it and/or modify
  43 +       it under the terms of the GNU General Public License as published by
  44 +       the Free Software Foundation; either version 2 of the License, or
  45 +       (at your option) any later version.
  46 +
  47 +       This program is distributed in the hope that it will be useful,
  48 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  49 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  50 +       GNU General Public License for more details.
  51 +
  52 +       You should have received a copy of the GNU General Public License
  53 +       along with this program; if not, write to the
  54 +       Free Software Foundation, Inc.,
  55 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  56 + */
  57 +
  58 +/*
  59 +       Module: rt2800pci
  60 +       Abstract: rt2800pci device specific routines.
  61 +       Supported chipsets: RT2800E & RT2800ED.
  62 + */
  63 +
  64 +#include <linux/crc-ccitt.h>
  65 +#include <linux/delay.h>
  66 +#include <linux/etherdevice.h>
  67 +#include <linux/init.h>
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +#include <linux/pci.h>
  71 +#include <linux/platform_device.h>
  72 +#include <linux/eeprom_93cx6.h>
  73 +
  74 +#include "rt2x00.h"
  75 +#include "rt2x00pci.h"
  76 +#include "rt2x00soc.h"
  77 +#include "rt2800pci.h"
  78 +
  79 +#ifdef CONFIG_RT2800PCI_PCI_MODULE
  80 +#define CONFIG_RT2800PCI_PCI
  81 +#endif
  82 +
  83 +#ifdef CONFIG_RT2800PCI_WISOC_MODULE
  84 +#define CONFIG_RT2800PCI_WISOC
  85 +#endif
  86 +
  87 +/*
  88 + * Allow hardware encryption to be disabled.
  89 + */
  90 +static int modparam_nohwcrypt = 0;
  91 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  92 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  93 +
  94 +/*
  95 + * Register access.
  96 + * BBP and RF register require indirect register access,
  97 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  98 + * These indirect registers work with busy bits,
  99 + * and we will try maximal REGISTER_BUSY_COUNT times to access
 100 + * the register while taking a REGISTER_BUSY_DELAY us delay
 101 + * between each attampt. When the busy bit is still set at that time,
 102 + * the access attempt is considered to have failed,
 103 + * and we will print an error.
 104 + */
 105 +#define WAIT_FOR_BBP(__dev, __reg) \
 106 +       rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
 107 +#define WAIT_FOR_RFCSR(__dev, __reg) \
 108 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
 109 +#define WAIT_FOR_RF(__dev, __reg) \
 110 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 111 +#define WAIT_FOR_MCU(__dev, __reg) \
 112 +       rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
 113 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 114 +
 115 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
 116 +                               const unsigned int word, const u8 value)
 117 +{
 118 +       u32 reg;
 119 +
 120 +       mutex_lock(&rt2x00dev->csr_mutex);
 121 +
 122 +       /*
 123 +        * Wait until the BBP becomes available, afterwards we
 124 +        * can safely write the new data into the register.
 125 +        */
 126 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 127 +               reg = 0;
 128 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 129 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 132 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133 +
 134 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 135 +       }
 136 +
 137 +       mutex_unlock(&rt2x00dev->csr_mutex);
 138 +}
 139 +
 140 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 141 +                              const unsigned int word, u8 *value)
 142 +{
 143 +       u32 reg;
 144 +
 145 +       mutex_lock(&rt2x00dev->csr_mutex);
 146 +
 147 +       /*
 148 +        * Wait until the BBP becomes available, afterwards we
 149 +        * can safely write the read request into the register.
 150 +        * After the data has been written, we wait until hardware
 151 +        * returns the correct value, if at any time the register
 152 +        * doesn't become available in time, reg will be 0xffffffff
 153 +        * which means we return 0xff to the caller.
 154 +        */
 155 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 156 +               reg = 0;
 157 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 158 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 159 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 160 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 161 +
 162 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 163 +
 164 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 165 +       }
 166 +
 167 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 168 +
 169 +       mutex_unlock(&rt2x00dev->csr_mutex);
 170 +}
 171 +
 172 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 173 +                                 const unsigned int word, const u8 value)
 174 +{
 175 +       u32 reg;
 176 +
 177 +       mutex_lock(&rt2x00dev->csr_mutex);
 178 +
 179 +       /*
 180 +        * Wait until the RFCSR becomes available, afterwards we
 181 +        * can safely write the new data into the register.
 182 +        */
 183 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184 +               reg = 0;
 185 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 186 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 187 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 188 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 189 +
 190 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
 191 +       }
 192 +
 193 +       mutex_unlock(&rt2x00dev->csr_mutex);
 194 +}
 195 +
 196 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 197 +                                const unsigned int word, u8 *value)
 198 +{
 199 +       u32 reg;
 200 +
 201 +       mutex_lock(&rt2x00dev->csr_mutex);
 202 +
 203 +       /*
 204 +        * Wait until the RFCSR becomes available, afterwards we
 205 +        * can safely write the read request into the register.
 206 +        * After the data has been written, we wait until hardware
 207 +        * returns the correct value, if at any time the register
 208 +        * doesn't become available in time, reg will be 0xffffffff
 209 +        * which means we return 0xff to the caller.
 210 +        */
 211 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 212 +               reg = 0;
 213 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 214 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 215 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 216 +
 217 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
 218 +
 219 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 220 +       }
 221 +
 222 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 223 +
 224 +       mutex_unlock(&rt2x00dev->csr_mutex);
 225 +}
 226 +
 227 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 228 +                              const unsigned int word, const u32 value)
 229 +{
 230 +       u32 reg;
 231 +
 232 +       mutex_lock(&rt2x00dev->csr_mutex);
 233 +
 234 +       /*
 235 +        * Wait until the RF becomes available, afterwards we
 236 +        * can safely write the new data into the register.
 237 +        */
 238 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 239 +               reg = 0;
 240 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 241 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 242 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 243 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 244 +
 245 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
 246 +               rt2x00_rf_write(rt2x00dev, word, value);
 247 +       }
 248 +
 249 +       mutex_unlock(&rt2x00dev->csr_mutex);
 250 +}
 251 +
 252 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 253 +                                 const u8 command, const u8 token,
 254 +                                 const u8 arg0, const u8 arg1)
 255 +{
 256 +       u32 reg;
 257 +
 258 +       /*
 259 +        * RT2880 and RT3052 don't support MCU requests.
 260 +        */
 261 +       if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
 262 +           rt2x00_rt(&rt2x00dev->chip, RT3052))
 263 +               return;
 264 +
 265 +       mutex_lock(&rt2x00dev->csr_mutex);
 266 +
 267 +       /*
 268 +        * Wait until the MCU becomes available, afterwards we
 269 +        * can safely write the new data into the register.
 270 +        */
 271 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 272 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 273 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 274 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 275 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 276 +               rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 277 +
 278 +               reg = 0;
 279 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 280 +               rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 281 +       }
 282 +
 283 +       mutex_unlock(&rt2x00dev->csr_mutex);
 284 +}
 285 +
 286 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
 287 +{
 288 +       unsigned int i;
 289 +       u32 reg;
 290 +
 291 +       for (i = 0; i < 200; i++) {
 292 +               rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
 293 +
 294 +               if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
 295 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
 296 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
 297 +                   (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
 298 +                       break;
 299 +
 300 +               udelay(REGISTER_BUSY_DELAY);
 301 +       }
 302 +
 303 +       if (i == 200)
 304 +               ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
 305 +
 306 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 307 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 308 +}
 309 +
 310 +#ifdef CONFIG_RT2800PCI_WISOC
 311 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 312 +{
 313 +       u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
 314 +
 315 +       memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
 316 +}
 317 +#else
 318 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 319 +{
 320 +}
 321 +#endif /* CONFIG_RT2800PCI_WISOC */
 322 +
 323 +#ifdef CONFIG_RT2800PCI_PCI
 324 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 325 +{
 326 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 327 +       u32 reg;
 328 +
 329 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 330 +
 331 +       eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 332 +       eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 333 +       eeprom->reg_data_clock =
 334 +           !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 335 +       eeprom->reg_chip_select =
 336 +           !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 337 +}
 338 +
 339 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 340 +{
 341 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 342 +       u32 reg = 0;
 343 +
 344 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 345 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 346 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 347 +                          !!eeprom->reg_data_clock);
 348 +       rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 349 +                          !!eeprom->reg_chip_select);
 350 +
 351 +       rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 352 +}
 353 +
 354 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 355 +{
 356 +       struct eeprom_93cx6 eeprom;
 357 +       u32 reg;
 358 +
 359 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 360 +
 361 +       eeprom.data = rt2x00dev;
 362 +       eeprom.register_read = rt2800pci_eepromregister_read;
 363 +       eeprom.register_write = rt2800pci_eepromregister_write;
 364 +       eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 365 +           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 366 +       eeprom.reg_data_in = 0;
 367 +       eeprom.reg_data_out = 0;
 368 +       eeprom.reg_data_clock = 0;
 369 +       eeprom.reg_chip_select = 0;
 370 +
 371 +       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 372 +                              EEPROM_SIZE / sizeof(u16));
 373 +}
 374 +#else
 375 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 376 +{
 377 +}
 378 +#endif /* CONFIG_RT2800PCI_PCI */
 379 +
 380 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 381 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
 382 +       .owner  = THIS_MODULE,
 383 +       .csr    = {
 384 +               .read           = rt2x00pci_register_read,
 385 +               .write          = rt2x00pci_register_write,
 386 +               .flags          = RT2X00DEBUGFS_OFFSET,
 387 +               .word_base      = CSR_REG_BASE,
 388 +               .word_size      = sizeof(u32),
 389 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 390 +       },
 391 +       .eeprom = {
 392 +               .read           = rt2x00_eeprom_read,
 393 +               .write          = rt2x00_eeprom_write,
 394 +               .word_base      = EEPROM_BASE,
 395 +               .word_size      = sizeof(u16),
 396 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 397 +       },
 398 +       .bbp    = {
 399 +               .read           = rt2800pci_bbp_read,
 400 +               .write          = rt2800pci_bbp_write,
 401 +               .word_base      = BBP_BASE,
 402 +               .word_size      = sizeof(u8),
 403 +               .word_count     = BBP_SIZE / sizeof(u8),
 404 +       },
 405 +       .rf     = {
 406 +               .read           = rt2x00_rf_read,
 407 +               .write          = rt2800pci_rf_write,
 408 +               .word_base      = RF_BASE,
 409 +               .word_size      = sizeof(u32),
 410 +               .word_count     = RF_SIZE / sizeof(u32),
 411 +       },
 412 +};
 413 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 414 +
 415 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 416 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 417 +{
 418 +       u32 reg;
 419 +
 420 +       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 421 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 422 +}
 423 +#else
 424 +#define rt2800pci_rfkill_poll  NULL
 425 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 426 +
 427 +#ifdef CONFIG_RT2X00_LIB_LEDS
 428 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 429 +                                    enum led_brightness brightness)
 430 +{
 431 +       struct rt2x00_led *led =
 432 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 433 +       unsigned int enabled = brightness != LED_OFF;
 434 +       unsigned int bg_mode =
 435 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 436 +       unsigned int polarity =
 437 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 438 +                                  EEPROM_FREQ_LED_POLARITY);
 439 +       unsigned int ledmode =
 440 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 441 +                                  EEPROM_FREQ_LED_MODE);
 442 +
 443 +       if (led->type == LED_TYPE_RADIO) {
 444 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 445 +                                     enabled ? 0x20 : 0);
 446 +       } else if (led->type == LED_TYPE_ASSOC) {
 447 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 448 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 449 +       } else if (led->type == LED_TYPE_QUALITY) {
 450 +               /*
 451 +                * The brightness is divided into 6 levels (0 - 5),
 452 +                * The specs tell us the following levels:
 453 +                *      0, 1 ,3, 7, 15, 31
 454 +                * to determine the level in a simple way we can simply
 455 +                * work with bitshifting:
 456 +                *      (1 << level) - 1
 457 +                */
 458 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 459 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 460 +                                     polarity);
 461 +       }
 462 +}
 463 +
 464 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 465 +                              unsigned long *delay_on,
 466 +                              unsigned long *delay_off)
 467 +{
 468 +       struct rt2x00_led *led =
 469 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 470 +       u32 reg;
 471 +
 472 +       rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
 473 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 474 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 475 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 476 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 477 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 478 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 479 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 480 +       rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
 481 +
 482 +       return 0;
 483 +}
 484 +
 485 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 486 +                              struct rt2x00_led *led,
 487 +                              enum led_type type)
 488 +{
 489 +       led->rt2x00dev = rt2x00dev;
 490 +       led->type = type;
 491 +       led->led_dev.brightness_set = rt2800pci_brightness_set;
 492 +       led->led_dev.blink_set = rt2800pci_blink_set;
 493 +       led->flags = LED_INITIALIZED;
 494 +}
 495 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 496 +
 497 +/*
 498 + * Configuration handlers.
 499 + */
 500 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 501 +                                      struct rt2x00lib_crypto *crypto,
 502 +                                      struct ieee80211_key_conf *key)
 503 +{
 504 +       struct mac_wcid_entry wcid_entry;
 505 +       struct mac_iveiv_entry iveiv_entry;
 506 +       u32 offset;
 507 +       u32 reg;
 508 +
 509 +       offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 510 +
 511 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 512 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 513 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 514 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 515 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 516 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 517 +                          (crypto->cmd == SET_KEY) * crypto->bssidx);
 518 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 519 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 520 +
 521 +       offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 522 +
 523 +       memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 524 +       if ((crypto->cipher == CIPHER_TKIP) ||
 525 +           (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 526 +           (crypto->cipher == CIPHER_AES))
 527 +               iveiv_entry.iv[3] |= 0x20;
 528 +       iveiv_entry.iv[3] |= key->keyidx << 6;
 529 +       rt2x00pci_register_multiwrite(rt2x00dev, offset,
 530 +                                     &iveiv_entry, sizeof(iveiv_entry));
 531 +
 532 +       offset = MAC_WCID_ENTRY(key->hw_key_idx);
 533 +
 534 +       memset(&wcid_entry, 0, sizeof(wcid_entry));
 535 +       if (crypto->cmd == SET_KEY)
 536 +               memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 537 +       rt2x00pci_register_multiwrite(rt2x00dev, offset,
 538 +                                     &wcid_entry, sizeof(wcid_entry));
 539 +}
 540 +
 541 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 542 +                                      struct rt2x00lib_crypto *crypto,
 543 +                                      struct ieee80211_key_conf *key)
 544 +{
 545 +       struct hw_key_entry key_entry;
 546 +       struct rt2x00_field32 field;
 547 +       u32 offset;
 548 +       u32 reg;
 549 +
 550 +       if (crypto->cmd == SET_KEY) {
 551 +               key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 552 +
 553 +               memcpy(key_entry.key, crypto->key,
 554 +                      sizeof(key_entry.key));
 555 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 556 +                      sizeof(key_entry.tx_mic));
 557 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 558 +                      sizeof(key_entry.rx_mic));
 559 +
 560 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 561 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 562 +                                             &key_entry, sizeof(key_entry));
 563 +       }
 564 +
 565 +       /*
 566 +        * The cipher types are stored over multiple registers
 567 +        * starting with SHARED_KEY_MODE_BASE each word will have
 568 +        * 32 bits and contains the cipher types for 2 bssidx each.
 569 +        * Using the correct defines correctly will cause overhead,
 570 +        * so just calculate the correct offset.
 571 +        */
 572 +       field.bit_offset = 4 * (key->hw_key_idx % 8);
 573 +       field.bit_mask = 0x7 << field.bit_offset;
 574 +
 575 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 576 +
 577 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 578 +       rt2x00_set_field32(&reg, field,
 579 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 580 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 581 +
 582 +       /*
 583 +        * Update WCID information
 584 +        */
 585 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 586 +
 587 +       return 0;
 588 +}
 589 +
 590 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 591 +                                        struct rt2x00lib_crypto *crypto,
 592 +                                        struct ieee80211_key_conf *key)
 593 +{
 594 +       struct hw_key_entry key_entry;
 595 +       u32 offset;
 596 +
 597 +       if (crypto->cmd == SET_KEY) {
 598 +               /*
 599 +                * 1 pairwise key is possible per AID, this means that the AID
 600 +                * equals our hw_key_idx. Make sure the WCID starts _after_ the
 601 +                * last possible shared key entry.
 602 +                */
 603 +               if (crypto->aid > (256 - 32))
 604 +                       return -ENOSPC;
 605 +
 606 +               key->hw_key_idx = 32 + crypto->aid;
 607 +
 608 +
 609 +               memcpy(key_entry.key, crypto->key,
 610 +                      sizeof(key_entry.key));
 611 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 612 +                      sizeof(key_entry.tx_mic));
 613 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 614 +                      sizeof(key_entry.rx_mic));
 615 +
 616 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 617 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 618 +                                             &key_entry, sizeof(key_entry));
 619 +       }
 620 +
 621 +       /*
 622 +        * Update WCID information
 623 +        */
 624 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 625 +
 626 +       return 0;
 627 +}
 628 +
 629 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 630 +                                   const unsigned int filter_flags)
 631 +{
 632 +       u32 reg;
 633 +
 634 +       /*
 635 +        * Start configuration steps.
 636 +        * Note that the version error will always be dropped
 637 +        * and broadcast frames will always be accepted since
 638 +        * there is no filter for it at this time.
 639 +        */
 640 +       rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 641 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 642 +                          !(filter_flags & FIF_FCSFAIL));
 643 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 644 +                          !(filter_flags & FIF_PLCPFAIL));
 645 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 646 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 647 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 648 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 649 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 650 +                          !(filter_flags & FIF_ALLMULTI));
 651 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 652 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 653 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 654 +                          !(filter_flags & FIF_CONTROL));
 655 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 656 +                          !(filter_flags & FIF_CONTROL));
 657 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 658 +                          !(filter_flags & FIF_CONTROL));
 659 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 660 +                          !(filter_flags & FIF_CONTROL));
 661 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 662 +                          !(filter_flags & FIF_CONTROL));
 663 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 664 +                          !(filter_flags & FIF_CONTROL));
 665 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 666 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 667 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 668 +                          !(filter_flags & FIF_CONTROL));
 669 +       rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 670 +}
 671 +
 672 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 673 +                                 struct rt2x00_intf *intf,
 674 +                                 struct rt2x00intf_conf *conf,
 675 +                                 const unsigned int flags)
 676 +{
 677 +       unsigned int beacon_base;
 678 +       u32 reg;
 679 +
 680 +       if (flags & CONFIG_UPDATE_TYPE) {
 681 +               /*
 682 +                * Clear current synchronisation setup.
 683 +                * For the Beacon base registers we only need to clear
 684 +                * the first byte since that byte contains the VALID and OWNER
 685 +                * bits which (when set to 0) will invalidate the entire beacon.
 686 +                */
 687 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 688 +               rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 689 +
 690 +               /*
 691 +                * Enable synchronisation.
 692 +                */
 693 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 694 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 695 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 696 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 697 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 698 +       }
 699 +
 700 +       if (flags & CONFIG_UPDATE_MAC) {
 701 +               reg = le32_to_cpu(conf->mac[1]);
 702 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 703 +               conf->mac[1] = cpu_to_le32(reg);
 704 +
 705 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 706 +                                             conf->mac, sizeof(conf->mac));
 707 +       }
 708 +
 709 +       if (flags & CONFIG_UPDATE_BSSID) {
 710 +               reg = le32_to_cpu(conf->bssid[1]);
 711 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 712 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 713 +               conf->bssid[1] = cpu_to_le32(reg);
 714 +
 715 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 716 +                                             conf->bssid, sizeof(conf->bssid));
 717 +       }
 718 +}
 719 +
 720 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 721 +                                struct rt2x00lib_erp *erp)
 722 +{
 723 +       u32 reg;
 724 +
 725 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 726 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 727 +                          DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
 728 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 729 +
 730 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 731 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 732 +                          !!erp->short_preamble);
 733 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 734 +                          !!erp->short_preamble);
 735 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 736 +
 737 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 738 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 739 +                          erp->cts_protection ? 2 : 0);
 740 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 741 +
 742 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 743 +                                erp->basic_rates);
 744 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 745 +
 746 +       rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 747 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 748 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 749 +       rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 750 +
 751 +       rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 752 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 753 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 754 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 755 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 756 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 757 +       rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 758 +}
 759 +
 760 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 761 +                                struct antenna_setup *ant)
 762 +{
 763 +       u8 r1;
 764 +       u8 r3;
 765 +
 766 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 767 +       rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 768 +
 769 +       /*
 770 +        * Configure the TX antenna.
 771 +        */
 772 +       switch ((int)ant->tx) {
 773 +       case 1:
 774 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 775 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 776 +               break;
 777 +       case 2:
 778 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 779 +               break;
 780 +       case 3:
 781 +               /* Do nothing */
 782 +               break;
 783 +       }
 784 +
 785 +       /*
 786 +        * Configure the RX antenna.
 787 +        */
 788 +       switch ((int)ant->rx) {
 789 +       case 1:
 790 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 791 +               break;
 792 +       case 2:
 793 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 794 +               break;
 795 +       case 3:
 796 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 797 +               break;
 798 +       }
 799 +
 800 +       rt2800pci_bbp_write(rt2x00dev, 3, r3);
 801 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 802 +}
 803 +
 804 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 805 +                                     struct rt2x00lib_conf *libconf)
 806 +{
 807 +       u16 eeprom;
 808 +       short lna_gain;
 809 +
 810 +       if (libconf->rf.channel <= 14) {
 811 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 812 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 813 +       } else if (libconf->rf.channel <= 64) {
 814 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 815 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 816 +       } else if (libconf->rf.channel <= 128) {
 817 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 818 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 819 +       } else {
 820 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 821 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 822 +       }
 823 +
 824 +       rt2x00dev->lna_gain = lna_gain;
 825 +}
 826 +
 827 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 828 +                                         struct ieee80211_conf *conf,
 829 +                                         struct rf_channel *rf,
 830 +                                         struct channel_info *info)
 831 +{
 832 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 833 +
 834 +       if (rt2x00dev->default_ant.tx == 1)
 835 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 836 +
 837 +       if (rt2x00dev->default_ant.rx == 1) {
 838 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 839 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 840 +       } else if (rt2x00dev->default_ant.rx == 2)
 841 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 842 +
 843 +       if (rf->channel > 14) {
 844 +               /*
 845 +                * When TX power is below 0, we should increase it by 7 to
 846 +                * make it a positive value (Minumum value is -7).
 847 +                * However this means that values between 0 and 7 have
 848 +                * double meaning, and we should set a 7DBm boost flag.
 849 +                */
 850 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 851 +                                  (info->tx_power1 >= 0));
 852 +
 853 +               if (info->tx_power1 < 0)
 854 +                       info->tx_power1 += 7;
 855 +
 856 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 857 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 858 +
 859 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 860 +                                  (info->tx_power2 >= 0));
 861 +
 862 +               if (info->tx_power2 < 0)
 863 +                       info->tx_power2 += 7;
 864 +
 865 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 866 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 867 +       } else {
 868 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 869 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 870 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 871 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 872 +       }
 873 +
 874 +       rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 875 +
 876 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 877 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 878 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 879 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 880 +
 881 +       udelay(200);
 882 +
 883 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 884 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 885 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 886 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 887 +
 888 +       udelay(200);
 889 +
 890 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 891 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 892 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 893 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 894 +}
 895 +
 896 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 897 +                                         struct ieee80211_conf *conf,
 898 +                                         struct rf_channel *rf,
 899 +                                         struct channel_info *info)
 900 +{
 901 +       u8 rfcsr;
 902 +
 903 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
 904 +       rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
 905 +
 906 +       rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
 907 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 908 +       rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
 909 +
 910 +       rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
 911 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 912 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 913 +       rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
 914 +
 915 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 916 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 917 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 918 +
 919 +       rt2800pci_rfcsr_write(rt2x00dev, 24,
 920 +                             rt2x00dev->calibration[conf_is_ht40(conf)]);
 921 +
 922 +       rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 923 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 924 +       rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 925 +}
 926 +
 927 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 928 +                                    struct ieee80211_conf *conf,
 929 +                                    struct rf_channel *rf,
 930 +                                    struct channel_info *info)
 931 +{
 932 +       u32 reg;
 933 +       unsigned int tx_pin;
 934 +       u8 bbp;
 935 +
 936 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 937 +               rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
 938 +       else
 939 +               rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
 940 +
 941 +       /*
 942 +        * Change BBP settings
 943 +        */
 944 +       rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 945 +       rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 946 +       rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 947 +       rt2800pci_bbp_write(rt2x00dev, 86, 0);
 948 +
 949 +       if (rf->channel <= 14) {
 950 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 951 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
 952 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 953 +               } else {
 954 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
 955 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 956 +               }
 957 +       } else {
 958 +               rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
 959 +
 960 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 961 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 962 +               else
 963 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 964 +       }
 965 +
 966 +       rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 967 +       rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 968 +       rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 969 +       rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 970 +       rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 971 +
 972 +       tx_pin = 0;
 973 +
 974 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 975 +       if (rt2x00dev->default_ant.tx != 1) {
 976 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 977 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 978 +       }
 979 +
 980 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 981 +       if (rt2x00dev->default_ant.rx != 1) {
 982 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 983 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 984 +       }
 985 +
 986 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 987 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 988 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 989 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 990 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 991 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 992 +
 993 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 994 +
 995 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
 996 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 997 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
 998 +
 999 +       rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1000 +       rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1001 +       rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1002 +
1003 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1004 +               if (conf_is_ht40(conf)) {
1005 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1006 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1007 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1008 +               } else {
1009 +                       rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1010 +                       rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1011 +                       rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1012 +               }
1013 +       }
1014 +
1015 +       msleep(1);
1016 +}
1017 +
1018 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1019 +                                    const int txpower)
1020 +{
1021 +       u32 reg;
1022 +       u32 value = TXPOWER_G_TO_DEV(txpower);
1023 +       u8 r1;
1024 +
1025 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1026 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1027 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
1028 +
1029 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1030 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1031 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1032 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1033 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1034 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1035 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1036 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1037 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1038 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1039 +
1040 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1041 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1042 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1043 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1044 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1045 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1046 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1047 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1048 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1049 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1050 +
1051 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1052 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1053 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1054 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1055 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1056 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1057 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1058 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1059 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1060 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1061 +
1062 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1063 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1064 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1065 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1066 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1067 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1068 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1069 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1070 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1071 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1072 +
1073 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1074 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1075 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1076 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1077 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1078 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1079 +}
1080 +
1081 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1082 +                                        struct rt2x00lib_conf *libconf)
1083 +{
1084 +       u32 reg;
1085 +
1086 +       rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1087 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1088 +                          libconf->conf->short_frame_max_tx_count);
1089 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1090 +                          libconf->conf->long_frame_max_tx_count);
1091 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1092 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1093 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1094 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1095 +       rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1096 +}
1097 +
1098 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
1099 +                                     struct rt2x00lib_conf *libconf)
1100 +{
1101 +       u32 reg;
1102 +
1103 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1104 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1105 +                          libconf->conf->beacon_int * 16);
1106 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1107 +}
1108 +
1109 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1110 +                               struct rt2x00lib_conf *libconf)
1111 +{
1112 +       enum dev_state state =
1113 +           (libconf->conf->flags & IEEE80211_CONF_PS) ?
1114 +               STATE_SLEEP : STATE_AWAKE;
1115 +       u32 reg;
1116 +
1117 +       if (state == STATE_SLEEP) {
1118 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1119 +
1120 +               rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1121 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1122 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1123 +                                  libconf->conf->listen_interval - 1);
1124 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1125 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1126 +
1127 +               rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1128 +       } else {
1129 +               rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1130 +
1131 +               rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1132 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1133 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1134 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1135 +               rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1136 +       }
1137 +}
1138 +
1139 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1140 +                            struct rt2x00lib_conf *libconf,
1141 +                            const unsigned int flags)
1142 +{
1143 +       /* Always recalculate LNA gain before changing configuration */
1144 +       rt2800pci_config_lna_gain(rt2x00dev, libconf);
1145 +
1146 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1147 +               rt2800pci_config_channel(rt2x00dev, libconf->conf,
1148 +                                        &libconf->rf, &libconf->channel);
1149 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1150 +               rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1151 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1152 +               rt2800pci_config_retry_limit(rt2x00dev, libconf);
1153 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1154 +               rt2800pci_config_duration(rt2x00dev, libconf);
1155 +       if (flags & IEEE80211_CONF_CHANGE_PS)
1156 +               rt2800pci_config_ps(rt2x00dev, libconf);
1157 +}
1158 +
1159 +/*
1160 + * Link tuning
1161 + */
1162 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1163 +                                struct link_qual *qual)
1164 +{
1165 +       u32 reg;
1166 +
1167 +       /*
1168 +        * Update FCS error count from register.
1169 +        */
1170 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1171 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1172 +}
1173 +
1174 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1175 +{
1176 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1177 +               return 0x2e + rt2x00dev->lna_gain;
1178 +
1179 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1180 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1181 +       else
1182 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1183 +}
1184 +
1185 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1186 +                                    struct link_qual *qual, u8 vgc_level)
1187 +{
1188 +       if (qual->vgc_level != vgc_level) {
1189 +               rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1190 +               qual->vgc_level = vgc_level;
1191 +               qual->vgc_level_reg = vgc_level;
1192 +       }
1193 +}
1194 +
1195 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1196 +                                 struct link_qual *qual)
1197 +{
1198 +       rt2800pci_set_vgc(rt2x00dev, qual,
1199 +                         rt2800pci_get_default_vgc(rt2x00dev));
1200 +}
1201 +
1202 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1203 +                                struct link_qual *qual, const u32 count)
1204 +{
1205 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1206 +               return;
1207 +
1208 +       /*
1209 +        * When RSSI is better then -80 increase VGC level with 0x10
1210 +        */
1211 +       rt2800pci_set_vgc(rt2x00dev, qual,
1212 +                         rt2800pci_get_default_vgc(rt2x00dev) +
1213 +                         ((qual->rssi > -80) * 0x10));
1214 +}
1215 +
1216 +/*
1217 + * Firmware functions
1218 + */
1219 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1220 +{
1221 +       return FIRMWARE_RT2860;
1222 +}
1223 +
1224 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1225 +                                   const u8 *data, const size_t len)
1226 +{
1227 +       u16 fw_crc;
1228 +       u16 crc;
1229 +
1230 +       /*
1231 +        * Only support 8kb firmware files.
1232 +        */
1233 +       if (len != 8192)
1234 +               return FW_BAD_LENGTH;
1235 +
1236 +       /*
1237 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1238 +        * this means that we should never pass those 2 bytes to the crc
1239 +        * algorithm.
1240 +        */
1241 +       fw_crc = (data[len - 2] << 8 | data[len - 1]);
1242 +
1243 +       /*
1244 +        * Use the crc ccitt algorithm.
1245 +        * This will return the same value as the legacy driver which
1246 +        * used bit ordering reversion on the both the firmware bytes
1247 +        * before input input as well as on the final output.
1248 +        * Obviously using crc ccitt directly is much more efficient.
1249 +        */
1250 +       crc = crc_ccitt(~0, data, len - 2);
1251 +
1252 +       /*
1253 +        * There is a small difference between the crc-itu-t + bitrev and
1254 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1255 +        * will be swapped, use swab16 to convert the crc to the correct
1256 +        * value.
1257 +        */
1258 +       crc = swab16(crc);
1259 +
1260 +       return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1261 +}
1262 +
1263 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1264 +                                  const u8 *data, const size_t len)
1265 +{
1266 +       unsigned int i;
1267 +       u32 reg;
1268 +
1269 +       /*
1270 +        * Wait for stable hardware.
1271 +        */
1272 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1273 +               rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1274 +               if (reg && reg != ~0)
1275 +                       break;
1276 +               msleep(1);
1277 +       }
1278 +
1279 +       if (i == REGISTER_BUSY_COUNT) {
1280 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1281 +               return -EBUSY;
1282 +       }
1283 +
1284 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1285 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1286 +
1287 +       /*
1288 +        * Disable DMA, will be reenabled later when enabling
1289 +        * the radio.
1290 +        */
1291 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1292 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1293 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1294 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1295 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1296 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1297 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1298 +
1299 +       /*
1300 +        * enable Host program ram write selection
1301 +        */
1302 +       reg = 0;
1303 +       rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1304 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1305 +
1306 +       /*
1307 +        * Write firmware to device.
1308 +        */
1309 +       rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1310 +                                     data, len);
1311 +
1312 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1313 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1314 +
1315 +       /*
1316 +        * Wait for device to stabilize.
1317 +        */
1318 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1319 +               rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1320 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1321 +                       break;
1322 +               msleep(1);
1323 +       }
1324 +
1325 +       if (i == REGISTER_BUSY_COUNT) {
1326 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1327 +               return -EBUSY;
1328 +       }
1329 +
1330 +       /*
1331 +        * Disable interrupts
1332 +        */
1333 +       rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1334 +
1335 +       /*
1336 +        * Initialize BBP R/W access agent
1337 +        */
1338 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1339 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1340 +
1341 +       return 0;
1342 +}
1343 +
1344 +/*
1345 + * Initialization functions.
1346 + */
1347 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1348 +{
1349 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1350 +       u32 word;
1351 +
1352 +       if (entry->queue->qid == QID_RX) {
1353 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1354 +
1355 +               return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1356 +       } else {
1357 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1358 +
1359 +               return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1360 +       }
1361 +}
1362 +
1363 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1364 +{
1365 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1366 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1367 +       u32 word;
1368 +
1369 +       if (entry->queue->qid == QID_RX) {
1370 +               rt2x00_desc_read(entry_priv->desc, 0, &word);
1371 +               rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1372 +               rt2x00_desc_write(entry_priv->desc, 0, word);
1373 +
1374 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1375 +               rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1376 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1377 +       } else {
1378 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1379 +               rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1380 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1381 +       }
1382 +}
1383 +
1384 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1385 +{
1386 +       struct queue_entry_priv_pci *entry_priv;
1387 +       u32 reg;
1388 +
1389 +       /*
1390 +        * Initialize registers.
1391 +        */
1392 +       entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1393 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1394 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1395 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1396 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1397 +
1398 +       entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1399 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1400 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1401 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1402 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1403 +
1404 +       entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1405 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1406 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1407 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1408 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1409 +
1410 +       entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1411 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1412 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1413 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1414 +       rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1415 +
1416 +       entry_priv = rt2x00dev->rx->entries[0].priv_data;
1417 +       rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1418 +       rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1419 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1420 +       rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1421 +
1422 +       /*
1423 +        * Enable global DMA configuration
1424 +        */
1425 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1426 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1427 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1428 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1429 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1430 +
1431 +       rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1432 +
1433 +       return 0;
1434 +}
1435 +
1436 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1437 +{
1438 +       u32 reg;
1439 +       unsigned int i;
1440 +
1441 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1442 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1443 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1444 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1445 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1446 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1447 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1448 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1449 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1450 +
1451 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1452 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1453 +
1454 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1455 +
1456 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1457 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1458 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1459 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1460 +
1461 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1462 +
1463 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1464 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1465 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1466 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1467 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1468 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1469 +
1470 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1471 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1472 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1473 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1474 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1475 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1476 +
1477 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1478 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1479 +
1480 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1481 +
1482 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1483 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1484 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1485 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1486 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1487 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1488 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1489 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1490 +
1491 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1492 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1493 +
1494 +       rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1495 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1496 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1497 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1498 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1499 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1500 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1501 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1502 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1503 +       rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1504 +
1505 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1506 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1507 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1508 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1509 +
1510 +       rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1511 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1512 +       if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1513 +           rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1514 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1515 +       else
1516 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1517 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1518 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1519 +       rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1520 +
1521 +       rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1522 +
1523 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1524 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1525 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1526 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1527 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1528 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1529 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1530 +
1531 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1532 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1533 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1534 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1535 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1536 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1537 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1538 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1539 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1540 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1541 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1542 +
1543 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1544 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1545 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1546 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1547 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1548 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1549 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1550 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1551 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1552 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1553 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1554 +
1555 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1556 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1557 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1558 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1559 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1560 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1561 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1562 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1563 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1564 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1565 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1566 +
1567 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1568 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1569 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1570 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1571 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1572 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1573 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1574 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1575 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1576 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1577 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1578 +
1579 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1580 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1581 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1582 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1583 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1584 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1585 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1586 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1587 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1588 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1589 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1590 +
1591 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1592 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1593 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1594 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1595 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1596 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1597 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1598 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1599 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1600 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1601 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1602 +
1603 +       rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1604 +       rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1605 +
1606 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1607 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1608 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1609 +                          IEEE80211_MAX_RTS_THRESHOLD);
1610 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1611 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1612 +
1613 +       rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1614 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1615 +
1616 +       /*
1617 +        * ASIC will keep garbage value after boot, clear encryption keys.
1618 +        */
1619 +       for (i = 0; i < 256; i++) {
1620 +               u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1621 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1622 +                                             wcid, sizeof(wcid));
1623 +
1624 +               rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1625 +               rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1626 +       }
1627 +
1628 +       for (i = 0; i < 16; i++)
1629 +               rt2x00pci_register_write(rt2x00dev,
1630 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1631 +
1632 +       /*
1633 +        * Clear all beacons
1634 +        * For the Beacon base registers we only need to clear
1635 +        * the first byte since that byte contains the VALID and OWNER
1636 +        * bits which (when set to 0) will invalidate the entire beacon.
1637 +        */
1638 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1639 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1640 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1641 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1642 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1643 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1644 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1645 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1646 +
1647 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1648 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1649 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1650 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1651 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1652 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1653 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1654 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1655 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1656 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1657 +
1658 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1659 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1660 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1661 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1662 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1663 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1664 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1665 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1666 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1667 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1668 +
1669 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1670 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1671 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1672 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1673 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1674 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1675 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1676 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1677 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1678 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1679 +
1680 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1681 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1682 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1683 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1684 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1685 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1686 +
1687 +       /*
1688 +        * We must clear the error counters.
1689 +        * These registers are cleared on read,
1690 +        * so we may pass a useless variable to store the value.
1691 +        */
1692 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1693 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1694 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1695 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1696 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1697 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1698 +
1699 +       return 0;
1700 +}
1701 +
1702 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1703 +{
1704 +       unsigned int i;
1705 +       u32 reg;
1706 +
1707 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1708 +               rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1709 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1710 +                       return 0;
1711 +
1712 +               udelay(REGISTER_BUSY_DELAY);
1713 +       }
1714 +
1715 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1716 +       return -EACCES;
1717 +}
1718 +
1719 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1720 +{
1721 +       unsigned int i;
1722 +       u8 value;
1723 +
1724 +       /*
1725 +        * BBP was enabled after firmware was loaded,
1726 +        * but we need to reactivate it now.
1727 +        */
1728 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1729 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1730 +       msleep(1);
1731 +
1732 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1733 +               rt2800pci_bbp_read(rt2x00dev, 0, &value);
1734 +               if ((value != 0xff) && (value != 0x00))
1735 +                       return 0;
1736 +               udelay(REGISTER_BUSY_DELAY);
1737 +       }
1738 +
1739 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1740 +       return -EACCES;
1741 +}
1742 +
1743 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1744 +{
1745 +       unsigned int i;
1746 +       u16 eeprom;
1747 +       u8 reg_id;
1748 +       u8 value;
1749 +
1750 +       if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1751 +                    rt2800pci_wait_bbp_ready(rt2x00dev)))
1752 +               return -EACCES;
1753 +
1754 +       rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1755 +       rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1756 +       rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1757 +       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1758 +       rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1759 +       rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1760 +       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1761 +       rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1762 +       rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1763 +       rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1764 +       rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1765 +       rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1766 +       rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1767 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1768 +
1769 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1770 +               rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1771 +               rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1772 +       }
1773 +
1774 +       if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1775 +               rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1776 +
1777 +       if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1778 +               rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1779 +               rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1780 +               rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1781 +       }
1782 +
1783 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1784 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1785 +
1786 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1787 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1788 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1789 +                       rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1790 +               }
1791 +       }
1792 +
1793 +       return 0;
1794 +}
1795 +
1796 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1797 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
1798 +{
1799 +       unsigned int i;
1800 +       u8 bbp;
1801 +       u8 rfcsr;
1802 +       u8 passband;
1803 +       u8 stopband;
1804 +       u8 overtuned = 0;
1805 +
1806 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1807 +
1808 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1809 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1810 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1811 +
1812 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1813 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1814 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1815 +
1816 +       /*
1817 +        * Set power & frequency of passband test tone
1818 +        */
1819 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
1820 +
1821 +       for (i = 0; i < 100; i++) {
1822 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1823 +               msleep(1);
1824 +
1825 +               rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1826 +               if (passband)
1827 +                       break;
1828 +       }
1829 +
1830 +       /*
1831 +        * Set power & frequency of stopband test tone
1832 +        */
1833 +       rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1834 +
1835 +       for (i = 0; i < 100; i++) {
1836 +               rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1837 +               msleep(1);
1838 +
1839 +               rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1840 +
1841 +               if ((passband - stopband) <= filter_target) {
1842 +                       rfcsr24++;
1843 +                       overtuned += ((passband - stopband) == filter_target);
1844 +               } else
1845 +                       break;
1846 +
1847 +               rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1848 +       }
1849 +
1850 +       rfcsr24 -= !!overtuned;
1851 +
1852 +       rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1853 +       return rfcsr24;
1854 +}
1855 +
1856 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1857 +{
1858 +       u8 rfcsr;
1859 +       u8 bbp;
1860 +
1861 +       if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1862 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1863 +           !rt2x00_rf(&rt2x00dev->chip, RF3022))
1864 +               return 0;
1865 +
1866 +       /*
1867 +        * Init RF calibration.
1868 +        */
1869 +       rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1870 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1871 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1872 +       msleep(1);
1873 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1874 +       rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1875 +
1876 +       rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1877 +       rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1878 +       rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1879 +       rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1880 +       rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1881 +       rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1882 +       rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1883 +       rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1884 +       rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1885 +       rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1886 +       rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1887 +       rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1888 +       rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1889 +       rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1890 +       rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1891 +       rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1892 +       rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1893 +       rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1894 +       rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1895 +       rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1896 +       rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1897 +       rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1898 +       rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1899 +       rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1900 +       rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1901 +       rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1902 +       rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1903 +       rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1904 +       rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1905 +       rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1906 +
1907 +       /*
1908 +        * Set RX Filter calibration for 20MHz and 40MHz
1909 +        */
1910 +       rt2x00dev->calibration[0] =
1911 +           rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1912 +       rt2x00dev->calibration[1] =
1913 +           rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1914 +
1915 +       /*
1916 +        * Set back to initial state
1917 +        */
1918 +       rt2800pci_bbp_write(rt2x00dev, 24, 0);
1919 +
1920 +       rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1921 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1922 +       rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1923 +
1924 +       /*
1925 +        * set BBP back to BW20
1926 +        */
1927 +       rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1928 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1929 +       rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1930 +
1931 +       return 0;
1932 +}
1933 +
1934 +/*
1935 + * Device state switch handlers.
1936 + */
1937 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1938 +                               enum dev_state state)
1939 +{
1940 +       u32 reg;
1941 +
1942 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1943 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1944 +                          (state == STATE_RADIO_RX_ON) ||
1945 +                          (state == STATE_RADIO_RX_ON_LINK));
1946 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1947 +}
1948 +
1949 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1950 +                                enum dev_state state)
1951 +{
1952 +       int mask = (state == STATE_RADIO_IRQ_ON);
1953 +       u32 reg;
1954 +
1955 +       /*
1956 +        * When interrupts are being enabled, the interrupt registers
1957 +        * should clear the register to assure a clean state.
1958 +        */
1959 +       if (state == STATE_RADIO_IRQ_ON) {
1960 +               rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1961 +               rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1962 +       }
1963 +
1964 +       rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1965 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1966 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1967 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1968 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1969 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1970 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1971 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1972 +       rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1973 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1974 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1975 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1976 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1977 +       rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1978 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1979 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1980 +       rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1981 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1982 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1983 +       rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1984 +}
1985 +
1986 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1987 +{
1988 +       unsigned int i;
1989 +       u32 reg;
1990 +
1991 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1992 +               rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1993 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1994 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1995 +                       return 0;
1996 +
1997 +               msleep(1);
1998 +       }
1999 +
2000 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
2001 +       return -EACCES;
2002 +}
2003 +
2004 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
2005 +{
2006 +       u32 reg;
2007 +       u16 word;
2008 +
2009 +       /*
2010 +        * Initialize all registers.
2011 +        */
2012 +       if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2013 +                    rt2800pci_init_queues(rt2x00dev) ||
2014 +                    rt2800pci_init_registers(rt2x00dev) ||
2015 +                    rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2016 +                    rt2800pci_init_bbp(rt2x00dev) ||
2017 +                    rt2800pci_init_rfcsr(rt2x00dev)))
2018 +               return -EIO;
2019 +
2020 +       /*
2021 +        * Send signal to firmware during boot time.
2022 +        */
2023 +       rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2024 +
2025 +       /*
2026 +        * Enable RX.
2027 +        */
2028 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2029 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2030 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2031 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2032 +
2033 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2034 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2035 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2036 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2037 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2038 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2039 +
2040 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2041 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2042 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2043 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2044 +
2045 +       /*
2046 +        * Initialize LED control
2047 +        */
2048 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2049 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2050 +                             word & 0xff, (word >> 8) & 0xff);
2051 +
2052 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2053 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2054 +                             word & 0xff, (word >> 8) & 0xff);
2055 +
2056 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2057 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2058 +                             word & 0xff, (word >> 8) & 0xff);
2059 +
2060 +       return 0;
2061 +}
2062 +
2063 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2064 +{
2065 +       u32 reg;
2066 +
2067 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2068 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2069 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2070 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2071 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2072 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2073 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2074 +
2075 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2076 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2077 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2078 +
2079 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2080 +
2081 +       /* Wait for DMA, ignore error */
2082 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
2083 +}
2084 +
2085 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2086 +                              enum dev_state state)
2087 +{
2088 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2089 +
2090 +       if (state == STATE_AWAKE) {
2091 +               rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2092 +               rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2093 +       } else
2094 +               rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2095 +
2096 +       return 0;
2097 +}
2098 +
2099 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2100 +                                     enum dev_state state)
2101 +{
2102 +       int retval = 0;
2103 +
2104 +       switch (state) {
2105 +       case STATE_RADIO_ON:
2106 +               /*
2107 +                * Before the radio can be enabled, the device first has
2108 +                * to be woken up. After that it needs a bit of time
2109 +                * to be fully awake and the radio can be enabled.
2110 +                */
2111 +               rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2112 +               msleep(1);
2113 +               retval = rt2800pci_enable_radio(rt2x00dev);
2114 +               break;
2115 +       case STATE_RADIO_OFF:
2116 +               /*
2117 +                * After the radio has been disablee, the device should
2118 +                * be put to sleep for powersaving.
2119 +                */
2120 +               rt2800pci_disable_radio(rt2x00dev);
2121 +               rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2122 +               break;
2123 +       case STATE_RADIO_RX_ON:
2124 +       case STATE_RADIO_RX_ON_LINK:
2125 +       case STATE_RADIO_RX_OFF:
2126 +       case STATE_RADIO_RX_OFF_LINK:
2127 +               rt2800pci_toggle_rx(rt2x00dev, state);
2128 +               break;
2129 +       case STATE_RADIO_IRQ_ON:
2130 +       case STATE_RADIO_IRQ_OFF:
2131 +               rt2800pci_toggle_irq(rt2x00dev, state);
2132 +               break;
2133 +       case STATE_DEEP_SLEEP:
2134 +       case STATE_SLEEP:
2135 +       case STATE_STANDBY:
2136 +       case STATE_AWAKE:
2137 +               retval = rt2800pci_set_state(rt2x00dev, state);
2138 +               break;
2139 +       default:
2140 +               retval = -ENOTSUPP;
2141 +               break;
2142 +       }
2143 +
2144 +       if (unlikely(retval))
2145 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2146 +                     state, retval);
2147 +
2148 +       return retval;
2149 +}
2150 +
2151 +/*
2152 + * TX descriptor initialization
2153 + */
2154 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2155 +                                   struct sk_buff *skb,
2156 +                                   struct txentry_desc *txdesc)
2157 +{
2158 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2159 +       __le32 *txd = skbdesc->desc;
2160 +       __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2161 +       u32 word;
2162 +
2163 +       /*
2164 +        * Initialize TX Info descriptor
2165 +        */
2166 +       rt2x00_desc_read(txwi, 0, &word);
2167 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
2168 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2169 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2170 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2171 +       rt2x00_set_field32(&word, TXWI_W0_TS,
2172 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2173 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2174 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2175 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2176 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2177 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2178 +       rt2x00_set_field32(&word, TXWI_W0_BW,
2179 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2180 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2181 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2182 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2183 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2184 +       rt2x00_desc_write(txwi, 0, word);
2185 +
2186 +       rt2x00_desc_read(txwi, 1, &word);
2187 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2188 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2189 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2190 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2191 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2192 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2193 +                          test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2194 +                              txdesc->key_idx : 0xff);
2195 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2196 +                          skb->len - txdesc->l2pad);
2197 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2198 +                          skbdesc->entry->queue->qid);
2199 +       rt2x00_desc_write(txwi, 1, word);
2200 +
2201 +       /*
2202 +        * Always write 0 to IV/EIV fields, hardware will insert the IV
2203 +        * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2204 +        * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2205 +        * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2206 +        * crypto entry in the registers should be used to encrypt the frame.
2207 +        */
2208 +       _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2209 +       _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2210 +
2211 +       /*
2212 +        * Initialize TX descriptor
2213 +        */
2214 +       rt2x00_desc_read(txd, 0, &word);
2215 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2216 +       rt2x00_desc_write(txd, 0, word);
2217 +
2218 +       rt2x00_desc_read(txd, 1, &word);
2219 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2220 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2221 +       rt2x00_set_field32(&word, TXD_W1_BURST,
2222 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2223 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2224 +                          rt2x00dev->hw->extra_tx_headroom);
2225 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2226 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2227 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2228 +       rt2x00_desc_write(txd, 1, word);
2229 +
2230 +       rt2x00_desc_read(txd, 2, &word);
2231 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2232 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2233 +       rt2x00_desc_write(txd, 2, word);
2234 +
2235 +       rt2x00_desc_read(txd, 3, &word);
2236 +       rt2x00_set_field32(&word, TXD_W3_WIV,
2237 +                          !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2238 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2239 +       rt2x00_desc_write(txd, 3, word);
2240 +}
2241 +
2242 +/*
2243 + * TX data initialization
2244 + */
2245 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2246 +{
2247 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2248 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2249 +       unsigned int beacon_base;
2250 +       u32 reg;
2251 +
2252 +       /*
2253 +        * Disable beaconing while we are reloading the beacon data,
2254 +        * otherwise we might be sending out invalid data.
2255 +        */
2256 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2257 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2258 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2259 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2260 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2261 +
2262 +       /*
2263 +        * Write entire beacon with descriptor to register.
2264 +        */
2265 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2266 +       rt2x00pci_register_multiwrite(rt2x00dev,
2267 +                                     beacon_base,
2268 +                                     skbdesc->desc, skbdesc->desc_len);
2269 +       rt2x00pci_register_multiwrite(rt2x00dev,
2270 +                                     beacon_base + skbdesc->desc_len,
2271 +                                     entry->skb->data, entry->skb->len);
2272 +
2273 +       /*
2274 +        * Clean up beacon skb.
2275 +        */
2276 +       dev_kfree_skb_any(entry->skb);
2277 +       entry->skb = NULL;
2278 +}
2279 +
2280 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2281 +                                   const enum data_queue_qid queue_idx)
2282 +{
2283 +       struct data_queue *queue;
2284 +       unsigned int idx, qidx = 0;
2285 +       u32 reg;
2286 +
2287 +       if (queue_idx == QID_BEACON) {
2288 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2289 +               if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2290 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2291 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2292 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2293 +                       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2294 +               }
2295 +               return;
2296 +       }
2297 +
2298 +       if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2299 +               return;
2300 +
2301 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2302 +       idx = queue->index[Q_INDEX];
2303 +
2304 +       if (queue_idx == QID_MGMT)
2305 +               qidx = 5;
2306 +       else
2307 +               qidx = queue_idx;
2308 +
2309 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2310 +}
2311 +
2312 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2313 +                                   const enum data_queue_qid qid)
2314 +{
2315 +       u32 reg;
2316 +
2317 +       if (qid == QID_BEACON) {
2318 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2319 +               return;
2320 +       }
2321 +
2322 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2323 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2324 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2325 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2326 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2327 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2328 +}
2329 +
2330 +/*
2331 + * RX control handlers
2332 + */
2333 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2334 +                                 struct rxdone_entry_desc *rxdesc)
2335 +{
2336 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2337 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2338 +       __le32 *rxd = entry_priv->desc;
2339 +       __le32 *rxwi = (__le32 *)entry->skb->data;
2340 +       u32 rxd3;
2341 +       u32 rxwi0;
2342 +       u32 rxwi1;
2343 +       u32 rxwi2;
2344 +       u32 rxwi3;
2345 +
2346 +       rt2x00_desc_read(rxd, 3, &rxd3);
2347 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2348 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2349 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2350 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2351 +
2352 +       if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2353 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2354 +
2355 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2356 +               /*
2357 +                * Unfortunately we don't know the cipher type used during
2358 +                * decryption. This prevents us from correct providing
2359 +                * correct statistics through debugfs.
2360 +                */
2361 +               rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2362 +               rxdesc->cipher_status =
2363 +                   rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2364 +       }
2365 +
2366 +       if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2367 +               /*
2368 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2369 +                * decryption. Unfortunately the descriptor doesn't contain
2370 +                * any fields with the EIV/IV data either, so they can't
2371 +                * be restored by rt2x00lib.
2372 +                */
2373 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2374 +
2375 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2376 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2377 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2378 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2379 +       }
2380 +
2381 +       if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2382 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2383 +
2384 +       if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
2385 +               rxdesc->dev_flags |= RXDONE_L2PAD;
2386 +
2387 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2388 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
2389 +
2390 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2391 +               rxdesc->flags |= RX_FLAG_40MHZ;
2392 +
2393 +       /*
2394 +        * Detect RX rate, always use MCS as signal type.
2395 +        */
2396 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2397 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2398 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2399 +
2400 +       /*
2401 +        * Mask of 0x8 bit to remove the short preamble flag.
2402 +        */
2403 +       if (rxdesc->rate_mode == RATE_MODE_CCK)
2404 +               rxdesc->signal &= ~0x8;
2405 +
2406 +       rxdesc->rssi =
2407 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2408 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2409 +
2410 +       rxdesc->noise =
2411 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2412 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2413 +
2414 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2415 +
2416 +       /*
2417 +        * Set RX IDX in register to inform hardware that we have handled
2418 +        * this entry and it is available for reuse again.
2419 +        */
2420 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2421 +
2422 +       /*
2423 +        * Remove TXWI descriptor from start of buffer.
2424 +        */
2425 +       skb_pull(entry->skb, RXWI_DESC_SIZE);
2426 +       skb_trim(entry->skb, rxdesc->size);
2427 +}
2428 +
2429 +/*
2430 + * Interrupt functions.
2431 + */
2432 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2433 +{
2434 +       struct data_queue *queue;
2435 +       struct queue_entry *entry;
2436 +       struct queue_entry *entry_done;
2437 +       struct queue_entry_priv_pci *entry_priv;
2438 +       struct txdone_entry_desc txdesc;
2439 +       u32 word;
2440 +       u32 reg;
2441 +       u32 old_reg;
2442 +       int type;
2443 +       int index;
2444 +
2445 +       /*
2446 +        * During each loop we will compare the freshly read
2447 +        * TX_STA_FIFO register value with the value read from
2448 +        * the previous loop. If the 2 values are equal then
2449 +        * we should stop processing because the chance it
2450 +        * quite big that the device has been unplugged and
2451 +        * we risk going into an endless loop.
2452 +        */
2453 +       old_reg = 0;
2454 +
2455 +       while (1) {
2456 +               rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2457 +               if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2458 +                       break;
2459 +
2460 +               if (old_reg == reg)
2461 +                       break;
2462 +               old_reg = reg;
2463 +
2464 +               /*
2465 +                * Skip this entry when it contains an invalid
2466 +                * queue identication number.
2467 +                */
2468 +               type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2469 +               queue = rt2x00queue_get_queue(rt2x00dev, type);
2470 +               if (unlikely(!queue))
2471 +                       continue;
2472 +
2473 +               /*
2474 +                * Skip this entry when it contains an invalid
2475 +                * index number.
2476 +                */
2477 +               index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2478 +               if (unlikely(index >= queue->limit))
2479 +                       continue;
2480 +
2481 +               entry = &queue->entries[index];
2482 +               entry_priv = entry->priv_data;
2483 +               rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2484 +
2485 +               entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2486 +               while (entry != entry_done) {
2487 +                       /*
2488 +                        * Catch up.
2489 +                        * Just report any entries we missed as failed.
2490 +                        */
2491 +                       WARNING(rt2x00dev,
2492 +                               "TX status report missed for entry %d\n",
2493 +                               entry_done->entry_idx);
2494 +
2495 +                       txdesc.flags = 0;
2496 +                       __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2497 +                       txdesc.retry = 0;
2498 +
2499 +                       rt2x00lib_txdone(entry_done, &txdesc);
2500 +                       entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2501 +               }
2502 +
2503 +               /*
2504 +                * Obtain the status about this packet.
2505 +                */
2506 +               txdesc.flags = 0;
2507 +               if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2508 +                       __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2509 +               else
2510 +                       __set_bit(TXDONE_FAILURE, &txdesc.flags);
2511 +               txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2512 +
2513 +               rt2x00lib_txdone(entry, &txdesc);
2514 +       }
2515 +}
2516 +
2517 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2518 +{
2519 +       struct rt2x00_dev *rt2x00dev = dev_instance;
2520 +       u32 reg;
2521 +
2522 +       /* Read status and ACK all interrupts */
2523 +       rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2524 +       rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2525 +
2526 +       if (!reg)
2527 +               return IRQ_NONE;
2528 +
2529 +       if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2530 +               return IRQ_HANDLED;
2531 +
2532 +       /*
2533 +        * 1 - Rx ring done interrupt.
2534 +        */
2535 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2536 +               rt2x00pci_rxdone(rt2x00dev);
2537 +
2538 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2539 +               rt2800pci_txdone(rt2x00dev);
2540 +
2541 +       return IRQ_HANDLED;
2542 +}
2543 +
2544 +/*
2545 + * Device probe functions.
2546 + */
2547 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2548 +{
2549 +       u16 word;
2550 +       u8 *mac;
2551 +       u8 default_lna_gain;
2552 +
2553 +       /*
2554 +        * Read EEPROM into buffer
2555 +        */
2556 +       switch(rt2x00dev->chip.rt) {
2557 +       case RT2880:
2558 +       case RT3052:
2559 +               rt2800pci_read_eeprom_soc(rt2x00dev);
2560 +               break;
2561 +       default:
2562 +               rt2800pci_read_eeprom_pci(rt2x00dev);
2563 +               break;
2564 +       }
2565 +
2566 +       /*
2567 +        * Start validation of the data that has been read.
2568 +        */
2569 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2570 +       if (!is_valid_ether_addr(mac)) {
2571 +               DECLARE_MAC_BUF(macbuf);
2572 +
2573 +               random_ether_addr(mac);
2574 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2575 +       }
2576 +
2577 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2578 +       if (word == 0xffff) {
2579 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2580 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2581 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2582 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2583 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2584 +       } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2585 +               /*
2586 +                * There is a max of 2 RX streams for RT2860 series
2587 +                */
2588 +               if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2589 +                       rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2590 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2591 +       }
2592 +
2593 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2594 +       if (word == 0xffff) {
2595 +               rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2596 +               rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2597 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2598 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2599 +               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2600 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2601 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2602 +               rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2603 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2604 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2605 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2606 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2607 +       }
2608 +
2609 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2610 +       if ((word & 0x00ff) == 0x00ff) {
2611 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2612 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2613 +                                  LED_MODE_TXRX_ACTIVITY);
2614 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2615 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2616 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2617 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2618 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2619 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2620 +       }
2621 +
2622 +       /*
2623 +        * During the LNA validation we are going to use
2624 +        * lna0 as correct value. Note that EEPROM_LNA
2625 +        * is never validated.
2626 +        */
2627 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2628 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2629 +
2630 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2631 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2632 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2633 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2634 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2635 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2636 +
2637 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2638 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2639 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2640 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2641 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2642 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2643 +                                  default_lna_gain);
2644 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2645 +
2646 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2647 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2648 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2649 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2650 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2651 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2652 +
2653 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2654 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2655 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2656 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2657 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2658 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2659 +                                  default_lna_gain);
2660 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2661 +
2662 +       return 0;
2663 +}
2664 +
2665 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2666 +{
2667 +       u32 reg;
2668 +       u16 value;
2669 +       u16 eeprom;
2670 +
2671 +       /*
2672 +        * Read EEPROM word for configuration.
2673 +        */
2674 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2675 +
2676 +       /*
2677 +        * Identify RF chipset.
2678 +        */
2679 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2680 +       rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2681 +       rt2x00_set_chip_rf(rt2x00dev, value, reg);
2682 +
2683 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2684 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2685 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2686 +           !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2687 +           !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2688 +           !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2689 +           !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2690 +           !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2691 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2692 +               return -ENODEV;
2693 +       }
2694 +
2695 +       /*
2696 +        * Identify default antenna configuration.
2697 +        */
2698 +       rt2x00dev->default_ant.tx =
2699 +           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2700 +       rt2x00dev->default_ant.rx =
2701 +           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2702 +
2703 +       /*
2704 +        * Read frequency offset and RF programming sequence.
2705 +        */
2706 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2707 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2708 +
2709 +       /*
2710 +        * Read external LNA informations.
2711 +        */
2712 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2713 +
2714 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2715 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2716 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2717 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2718 +
2719 +       /*
2720 +        * Detect if this device has an hardware controlled radio.
2721 +        */
2722 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2723 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2724 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2725 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2726 +
2727 +       /*
2728 +        * Store led settings, for correct led behaviour.
2729 +        */
2730 +#ifdef CONFIG_RT2X00_LIB_LEDS
2731 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2732 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2733 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2734 +
2735 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2736 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2737 +
2738 +       return 0;
2739 +}
2740 +
2741 +/*
2742 + * RF value list for rt2860
2743 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2744 + */
2745 +static const struct rf_channel rf_vals[] = {
2746 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2747 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2748 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2749 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2750 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2751 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2752 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2753 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2754 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2755 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2756 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2757 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2758 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2759 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2760 +
2761 +       /* 802.11 UNI / HyperLan 2 */
2762 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2763 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2764 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2765 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2766 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2767 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2768 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2769 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2770 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2771 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2772 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2773 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2774 +
2775 +       /* 802.11 HyperLan 2 */
2776 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2777 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2778 +       { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2779 +       { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2780 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2781 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2782 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2783 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2784 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2785 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2786 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2787 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2788 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2789 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2790 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2791 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2792 +
2793 +       /* 802.11 UNII */
2794 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2795 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2796 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2797 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2798 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2799 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2800 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2801 +
2802 +       /* 802.11 Japan */
2803 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2804 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2805 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2806 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2807 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2808 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2809 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2810 +};
2811 +
2812 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2813 +{
2814 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2815 +       struct channel_info *info;
2816 +       char *tx_power1;
2817 +       char *tx_power2;
2818 +       unsigned int i;
2819 +       u16 eeprom;
2820 +
2821 +       /*
2822 +        * Initialize all hw fields.
2823 +        */
2824 +       rt2x00dev->hw->flags =
2825 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2826 +           IEEE80211_HW_SIGNAL_DBM |
2827 +           IEEE80211_HW_SUPPORTS_PS |
2828 +           IEEE80211_HW_PS_NULLFUNC_STACK;
2829 +       rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2830 +
2831 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2832 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2833 +                               rt2x00_eeprom_addr(rt2x00dev,
2834 +                                                  EEPROM_MAC_ADDR_0));
2835 +
2836 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2837 +
2838 +       /*
2839 +        * Initialize hw_mode information.
2840 +        */
2841 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2842 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2843 +
2844 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2845 +           rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2846 +           rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2847 +           rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2848 +               spec->num_channels = 14;
2849 +               spec->channels = rf_vals;
2850 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2851 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2852 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2853 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2854 +               spec->channels = rf_vals;
2855 +       }
2856 +
2857 +       /*
2858 +        * Initialize HT information.
2859 +        */
2860 +       spec->ht.ht_supported = true;
2861 +       spec->ht.cap =
2862 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2863 +           IEEE80211_HT_CAP_GRN_FLD |
2864 +           IEEE80211_HT_CAP_SGI_20 |
2865 +           IEEE80211_HT_CAP_SGI_40 |
2866 +           IEEE80211_HT_CAP_TX_STBC |
2867 +           IEEE80211_HT_CAP_RX_STBC |
2868 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2869 +       spec->ht.ampdu_factor = 3;
2870 +       spec->ht.ampdu_density = 4;
2871 +       spec->ht.mcs.tx_params =
2872 +           IEEE80211_HT_MCS_TX_DEFINED |
2873 +           IEEE80211_HT_MCS_TX_RX_DIFF |
2874 +           ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2875 +               IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2876 +
2877 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2878 +       case 3:
2879 +               spec->ht.mcs.rx_mask[2] = 0xff;
2880 +       case 2:
2881 +               spec->ht.mcs.rx_mask[1] = 0xff;
2882 +       case 1:
2883 +               spec->ht.mcs.rx_mask[0] = 0xff;
2884 +               spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2885 +               break;
2886 +       }
2887 +
2888 +       /*
2889 +        * Create channel information array
2890 +        */
2891 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2892 +       if (!info)
2893 +               return -ENOMEM;
2894 +
2895 +       spec->channels_info = info;
2896 +
2897 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2898 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2899 +
2900 +       for (i = 0; i < 14; i++) {
2901 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2902 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2903 +       }
2904 +
2905 +       if (spec->num_channels > 14) {
2906 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2907 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2908 +
2909 +               for (i = 14; i < spec->num_channels; i++) {
2910 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2911 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2912 +               }
2913 +       }
2914 +
2915 +       return 0;
2916 +}
2917 +
2918 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2919 +{
2920 +       int retval;
2921 +
2922 +       /*
2923 +        * Allocate eeprom data.
2924 +        */
2925 +       retval = rt2800pci_validate_eeprom(rt2x00dev);
2926 +       if (retval)
2927 +               return retval;
2928 +
2929 +       retval = rt2800pci_init_eeprom(rt2x00dev);
2930 +       if (retval)
2931 +               return retval;
2932 +
2933 +       /*
2934 +        * Initialize hw specifications.
2935 +        */
2936 +       retval = rt2800pci_probe_hw_mode(rt2x00dev);
2937 +       if (retval)
2938 +               return retval;
2939 +
2940 +       /*
2941 +        * This device requires firmware.
2942 +        */
2943 +       if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2944 +           !rt2x00_rt(&rt2x00dev->chip, RT3052))
2945 +               __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2946 +       __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2947 +       if (!modparam_nohwcrypt)
2948 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2949 +
2950 +       /*
2951 +        * Set the rssi offset.
2952 +        */
2953 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2954 +
2955 +       return 0;
2956 +}
2957 +
2958 +/*
2959 + * IEEE80211 stack callback functions.
2960 + */
2961 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2962 +                                  u32 *iv32, u16 *iv16)
2963 +{
2964 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2965 +       struct mac_iveiv_entry iveiv_entry;
2966 +       u32 offset;
2967 +
2968 +       offset = MAC_IVEIV_ENTRY(hw_key_idx);
2969 +       rt2x00pci_register_multiread(rt2x00dev, offset,
2970 +                                     &iveiv_entry, sizeof(iveiv_entry));
2971 +
2972 +       memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2973 +       memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2974 +}
2975 +
2976 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2977 +{
2978 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2979 +       u32 reg;
2980 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2981 +
2982 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2983 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2984 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2985 +
2986 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2987 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2988 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2989 +
2990 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2991 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2992 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2993 +
2994 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2995 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2996 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2997 +
2998 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2999 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3000 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3001 +
3002 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3003 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3004 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3005 +
3006 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3007 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3008 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3009 +
3010 +       return 0;
3011 +}
3012 +
3013 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3014 +                            const struct ieee80211_tx_queue_params *params)
3015 +{
3016 +       struct rt2x00_dev *rt2x00dev = hw->priv;
3017 +       struct data_queue *queue;
3018 +       struct rt2x00_field32 field;
3019 +       int retval;
3020 +       u32 reg;
3021 +       u32 offset;
3022 +
3023 +       /*
3024 +        * First pass the configuration through rt2x00lib, that will
3025 +        * update the queue settings and validate the input. After that
3026 +        * we are free to update the registers based on the value
3027 +        * in the queue parameter.
3028 +        */
3029 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3030 +       if (retval)
3031 +               return retval;
3032 +
3033 +       /*
3034 +        * We only need to perform additional register initialization
3035 +        * for WMM queues/
3036 +        */
3037 +       if (queue_idx >= 4)
3038 +               return 0;
3039 +
3040 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3041 +
3042 +       /* Update WMM TXOP register */
3043 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3044 +       field.bit_offset = (queue_idx & 1) * 16;
3045 +       field.bit_mask = 0xffff << field.bit_offset;
3046 +
3047 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
3048 +       rt2x00_set_field32(&reg, field, queue->txop);
3049 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
3050 +
3051 +       /* Update WMM registers */
3052 +       field.bit_offset = queue_idx * 4;
3053 +       field.bit_mask = 0xf << field.bit_offset;
3054 +
3055 +       rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3056 +       rt2x00_set_field32(&reg, field, queue->aifs);
3057 +       rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3058 +
3059 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3060 +       rt2x00_set_field32(&reg, field, queue->cw_min);
3061 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3062 +
3063 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3064 +       rt2x00_set_field32(&reg, field, queue->cw_max);
3065 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3066 +
3067 +       /* Update EDCA registers */
3068 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3069 +
3070 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
3071 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3072 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3073 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3074 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3075 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
3076 +
3077 +       return 0;
3078 +}
3079 +
3080 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3081 +{
3082 +       struct rt2x00_dev *rt2x00dev = hw->priv;
3083 +       u64 tsf;
3084 +       u32 reg;
3085 +
3086 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3087 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3088 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3089 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3090 +
3091 +       return tsf;
3092 +}
3093 +
3094 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3095 +       .tx                     = rt2x00mac_tx,
3096 +       .start                  = rt2x00mac_start,
3097 +       .stop                   = rt2x00mac_stop,
3098 +       .add_interface          = rt2x00mac_add_interface,
3099 +       .remove_interface       = rt2x00mac_remove_interface,
3100 +       .config                 = rt2x00mac_config,
3101 +       .config_interface       = rt2x00mac_config_interface,
3102 +       .configure_filter       = rt2x00mac_configure_filter,
3103 +       .set_key                = rt2x00mac_set_key,
3104 +       .get_stats              = rt2x00mac_get_stats,
3105 +       .get_tkip_seq           = rt2800pci_get_tkip_seq,
3106 +       .set_rts_threshold      = rt2800pci_set_rts_threshold,
3107 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
3108 +       .conf_tx                = rt2800pci_conf_tx,
3109 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
3110 +       .get_tsf                = rt2800pci_get_tsf,
3111 +};
3112 +
3113 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3114 +       .irq_handler            = rt2800pci_interrupt,
3115 +       .probe_hw               = rt2800pci_probe_hw,
3116 +       .get_firmware_name      = rt2800pci_get_firmware_name,
3117 +       .check_firmware         = rt2800pci_check_firmware,
3118 +       .load_firmware          = rt2800pci_load_firmware,
3119 +       .initialize             = rt2x00pci_initialize,
3120 +       .uninitialize           = rt2x00pci_uninitialize,
3121 +       .get_entry_state        = rt2800pci_get_entry_state,
3122 +       .clear_entry            = rt2800pci_clear_entry,
3123 +       .set_device_state       = rt2800pci_set_device_state,
3124 +       .rfkill_poll            = rt2800pci_rfkill_poll,
3125 +       .link_stats             = rt2800pci_link_stats,
3126 +       .reset_tuner            = rt2800pci_reset_tuner,
3127 +       .link_tuner             = rt2800pci_link_tuner,
3128 +       .write_tx_desc          = rt2800pci_write_tx_desc,
3129 +       .write_tx_data          = rt2x00pci_write_tx_data,
3130 +       .write_beacon           = rt2800pci_write_beacon,
3131 +       .kick_tx_queue          = rt2800pci_kick_tx_queue,
3132 +       .kill_tx_queue          = rt2800pci_kill_tx_queue,
3133 +       .fill_rxdone            = rt2800pci_fill_rxdone,
3134 +       .config_shared_key      = rt2800pci_config_shared_key,
3135 +       .config_pairwise_key    = rt2800pci_config_pairwise_key,
3136 +       .config_filter          = rt2800pci_config_filter,
3137 +       .config_intf            = rt2800pci_config_intf,
3138 +       .config_erp             = rt2800pci_config_erp,
3139 +       .config_ant             = rt2800pci_config_ant,
3140 +       .config                 = rt2800pci_config,
3141 +};
3142 +
3143 +static const struct data_queue_desc rt2800pci_queue_rx = {
3144 +       .entry_num              = RX_ENTRIES,
3145 +       .data_size              = AGGREGATION_SIZE,
3146 +       .desc_size              = RXD_DESC_SIZE,
3147 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3148 +};
3149 +
3150 +static const struct data_queue_desc rt2800pci_queue_tx = {
3151 +       .entry_num              = TX_ENTRIES,
3152 +       .data_size              = AGGREGATION_SIZE,
3153 +       .desc_size              = TXD_DESC_SIZE,
3154 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3155 +};
3156 +
3157 +static const struct data_queue_desc rt2800pci_queue_bcn = {
3158 +       .entry_num              = 8 * BEACON_ENTRIES,
3159 +       .data_size              = 0, /* No DMA required for beacons */
3160 +       .desc_size              = TXWI_DESC_SIZE,
3161 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
3162 +};
3163 +
3164 +static const struct rt2x00_ops rt2800pci_ops = {
3165 +       .name           = KBUILD_MODNAME,
3166 +       .max_sta_intf   = 1,
3167 +       .max_ap_intf    = 8,
3168 +       .eeprom_size    = EEPROM_SIZE,
3169 +       .rf_size        = RF_SIZE,
3170 +       .tx_queues      = NUM_TX_QUEUES,
3171 +       .rx             = &rt2800pci_queue_rx,
3172 +       .tx             = &rt2800pci_queue_tx,
3173 +       .bcn            = &rt2800pci_queue_bcn,
3174 +       .lib            = &rt2800pci_rt2x00_ops,
3175 +       .hw             = &rt2800pci_mac80211_ops,
3176 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3177 +       .debugfs        = &rt2800pci_rt2x00debug,
3178 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3179 +};
3180 +
3181 +/*
3182 + * RT2800pci module information.
3183 + */
3184 +static struct pci_device_id rt2800pci_device_table[] = {
3185 +       /* Edimax */
3186 +       { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3187 +       { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3188 +       { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3189 +       { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3190 +       { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3191 +       { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3192 +       { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3193 +       { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3194 +       { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3195 +       { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3196 +       { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3197 +       { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3198 +       { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3199 +       { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3200 +       { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3201 +       { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3202 +       { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3203 +       /* Awt */
3204 +       { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3205 +       { 0, }
3206 +};
3207 +
3208 +MODULE_AUTHOR(DRV_PROJECT);
3209 +MODULE_VERSION(DRV_VERSION);
3210 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3211 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3212 +#ifdef CONFIG_RT2800PCI_PCI
3213 +MODULE_FIRMWARE(FIRMWARE_RT2860);
3214 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3215 +#endif /* CONFIG_RT2800PCI_PCI */
3216 +MODULE_LICENSE("GPL");
3217 +
3218 +#ifdef CONFIG_RT2800PCI_WISOC
3219 +#if defined(CONFIG_RALINK_RT288X)
3220 +__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3221 +#elif defined(CONFIG_RALINK_RT305X)
3222 +__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3223 +#endif
3224 +
3225 +static struct platform_driver rt2800soc_driver = {
3226 +       .driver         = {
3227 +               .name           = "rt2800_wmac",
3228 +               .owner          = THIS_MODULE,
3229 +               .mod_name       = KBUILD_MODNAME,
3230 +       },
3231 +       .probe          = __rt2x00soc_probe,
3232 +       .remove         = __devexit_p(rt2x00soc_remove),
3233 +       .suspend        = rt2x00soc_suspend,
3234 +       .resume         = rt2x00soc_resume,
3235 +};
3236 +#endif /* CONFIG_RT2800PCI_WISOC */
3237 +
3238 +#ifdef CONFIG_RT2800PCI_PCI
3239 +static struct pci_driver rt2800pci_driver = {
3240 +       .name           = KBUILD_MODNAME,
3241 +       .id_table       = rt2800pci_device_table,
3242 +       .probe          = rt2x00pci_probe,
3243 +       .remove         = __devexit_p(rt2x00pci_remove),
3244 +       .suspend        = rt2x00pci_suspend,
3245 +       .resume         = rt2x00pci_resume,
3246 +};
3247 +#endif /* CONFIG_RT2800PCI_PCI */
3248 +
3249 +static int __init rt2800pci_init(void)
3250 +{
3251 +       int ret = 0;
3252 +
3253 +#ifdef CONFIG_RT2800PCI_WISOC
3254 +       ret = platform_driver_register(&rt2800soc_driver);
3255 +       if (ret)
3256 +               return ret;
3257 +#endif
3258 +#ifdef CONFIG_RT2800PCI_PCI
3259 +       ret = pci_register_driver(&rt2800pci_driver);
3260 +       if (ret) {
3261 +#ifdef CONFIG_RT2800PCI_WISOC
3262 +               platform_driver_unregister(&rt2800soc_driver);
3263 +#endif
3264 +               return ret;
3265 +       }
3266 +#endif
3267 +
3268 +       return ret;
3269 +}
3270 +
3271 +static void __exit rt2800pci_exit(void)
3272 +{
3273 +#ifdef CONFIG_RT2800PCI_PCI
3274 +       pci_unregister_driver(&rt2800pci_driver);
3275 +#endif
3276 +#ifdef CONFIG_RT2800PCI_WISOC
3277 +       platform_driver_unregister(&rt2800soc_driver);
3278 +#endif
3279 +}
3280 +
3281 +module_init(rt2800pci_init);
3282 +module_exit(rt2800pci_exit);
3283 --- /dev/null
3284 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3285 @@ -0,0 +1,1927 @@
3286 +/*
3287 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3288 +       <http://rt2x00.serialmonkey.com>
3289 +
3290 +       This program is free software; you can redistribute it and/or modify
3291 +       it under the terms of the GNU General Public License as published by
3292 +       the Free Software Foundation; either version 2 of the License, or
3293 +       (at your option) any later version.
3294 +
3295 +       This program is distributed in the hope that it will be useful,
3296 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
3297 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3298 +       GNU General Public License for more details.
3299 +
3300 +       You should have received a copy of the GNU General Public License
3301 +       along with this program; if not, write to the
3302 +       Free Software Foundation, Inc.,
3303 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3304 + */
3305 +
3306 +/*
3307 +       Module: rt2800pci
3308 +       Abstract: Data structures and registers for the rt2800pci module.
3309 +       Supported chipsets: RT2800E & RT2800ED.
3310 + */
3311 +
3312 +#ifndef RT2800PCI_H
3313 +#define RT2800PCI_H
3314 +
3315 +/*
3316 + * RF chip defines.
3317 + *
3318 + * RF2820 2.4G 2T3R
3319 + * RF2850 2.4G/5G 2T3R
3320 + * RF2720 2.4G 1T2R
3321 + * RF2750 2.4G/5G 1T2R
3322 + * RF3020 2.4G 1T1R
3323 + * RF2020 2.4G B/G
3324 + * RF3021 2.4G 1T2R
3325 + * RF3022 2.4G 2T2R
3326 + */
3327 +#define RF2820                         0x0001
3328 +#define RF2850                         0x0002
3329 +#define RF2720                         0x0003
3330 +#define RF2750                         0x0004
3331 +#define RF3020                         0x0005
3332 +#define RF2020                         0x0006
3333 +#define RF3021                         0x0007
3334 +#define RF3022                         0x0008
3335 +
3336 +/*
3337 + * RT2860 version
3338 + */
3339 +#define RT2860C_VERSION                        0x28600100
3340 +#define RT2860D_VERSION                        0x28600101
3341 +#define RT2880E_VERSION                        0x28720200
3342 +#define RT2883_VERSION                 0x28830300
3343 +#define RT3070_VERSION                 0x30700200
3344 +
3345 +/*
3346 + * Signal information.
3347 + * Defaul offset is required for RSSI <-> dBm conversion.
3348 + */
3349 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
3350 +
3351 +/*
3352 + * Register layout information.
3353 + */
3354 +#define CSR_REG_BASE                   0x1000
3355 +#define CSR_REG_SIZE                   0x0800
3356 +#define EEPROM_BASE                    0x0000
3357 +#define EEPROM_SIZE                    0x0110
3358 +#define BBP_BASE                       0x0000
3359 +#define BBP_SIZE                       0x0080
3360 +#define RF_BASE                                0x0004
3361 +#define RF_SIZE                                0x0010
3362 +
3363 +/*
3364 + * Number of TX queues.
3365 + */
3366 +#define NUM_TX_QUEUES                  4
3367 +
3368 +/*
3369 + * PCI registers.
3370 + */
3371 +
3372 +/*
3373 + * E2PROM_CSR: EEPROM control register.
3374 + * RELOAD: Write 1 to reload eeprom content.
3375 + * TYPE: 0: 93c46, 1:93c66.
3376 + * LOAD_STATUS: 1:loading, 0:done.
3377 + */
3378 +#define E2PROM_CSR                     0x0004
3379 +#define E2PROM_CSR_DATA_CLOCK          FIELD32(0x00000001)
3380 +#define E2PROM_CSR_CHIP_SELECT         FIELD32(0x00000002)
3381 +#define E2PROM_CSR_DATA_IN             FIELD32(0x00000004)
3382 +#define E2PROM_CSR_DATA_OUT            FIELD32(0x00000008)
3383 +#define E2PROM_CSR_TYPE                        FIELD32(0x00000030)
3384 +#define E2PROM_CSR_LOAD_STATUS         FIELD32(0x00000040)
3385 +#define E2PROM_CSR_RELOAD              FIELD32(0x00000080)
3386 +
3387 +/*
3388 + * HOST-MCU shared memory
3389 + */
3390 +#define HOST_CMD_CSR                   0x0404
3391 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
3392 +
3393 +/*
3394 + * INT_SOURCE_CSR: Interrupt source register.
3395 + * Write one to clear corresponding bit.
3396 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3397 + */
3398 +#define INT_SOURCE_CSR                 0x0200
3399 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
3400 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
3401 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
3402 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
3403 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
3404 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
3405 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
3406 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
3407 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
3408 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
3409 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
3410 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
3411 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
3412 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
3413 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
3414 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
3415 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
3416 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
3417 +
3418 +/*
3419 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3420 + */
3421 +#define INT_MASK_CSR                   0x0204
3422 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
3423 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
3424 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
3425 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
3426 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
3427 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
3428 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
3429 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
3430 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
3431 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
3432 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
3433 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
3434 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
3435 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
3436 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
3437 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
3438 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
3439 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
3440 +
3441 +/*
3442 + * WPDMA_GLO_CFG
3443 + */
3444 +#define WPDMA_GLO_CFG                  0x0208
3445 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
3446 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
3447 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
3448 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
3449 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
3450 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
3451 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
3452 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
3453 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
3454 +
3455 +/*
3456 + * WPDMA_RST_IDX
3457 + */
3458 +#define WPDMA_RST_IDX                  0x020c
3459 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
3460 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
3461 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
3462 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
3463 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
3464 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
3465 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
3466 +
3467 +/*
3468 + * DELAY_INT_CFG
3469 + */
3470 +#define DELAY_INT_CFG                  0x0210
3471 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
3472 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
3473 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
3474 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
3475 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
3476 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
3477 +
3478 +/*
3479 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3480 + * AIFSN0: AC_BE
3481 + * AIFSN1: AC_BK
3482 + * AIFSN1: AC_VI
3483 + * AIFSN1: AC_VO
3484 + */
3485 +#define WMM_AIFSN_CFG                  0x0214
3486 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3487 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3488 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3489 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3490 +
3491 +/*
3492 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3493 + * CWMIN0: AC_BE
3494 + * CWMIN1: AC_BK
3495 + * CWMIN1: AC_VI
3496 + * CWMIN1: AC_VO
3497 + */
3498 +#define WMM_CWMIN_CFG                  0x0218
3499 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3500 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3501 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3502 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3503 +
3504 +/*
3505 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3506 + * CWMAX0: AC_BE
3507 + * CWMAX1: AC_BK
3508 + * CWMAX1: AC_VI
3509 + * CWMAX1: AC_VO
3510 + */
3511 +#define WMM_CWMAX_CFG                  0x021c
3512 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3513 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3514 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3515 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3516 +
3517 +/*
3518 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3519 + * AC0TXOP: AC_BK in unit of 32us
3520 + * AC1TXOP: AC_BE in unit of 32us
3521 + */
3522 +#define WMM_TXOP0_CFG                  0x0220
3523 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3524 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3525 +
3526 +/*
3527 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3528 + * AC2TXOP: AC_VI in unit of 32us
3529 + * AC3TXOP: AC_VO in unit of 32us
3530 + */
3531 +#define WMM_TXOP1_CFG                  0x0224
3532 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3533 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3534 +
3535 +/*
3536 + * GPIO_CTRL_CFG:
3537 + */
3538 +#define GPIO_CTRL_CFG                  0x0228
3539 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3540 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3541 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3542 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3543 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3544 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3545 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3546 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3547 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3548 +
3549 +/*
3550 + * MCU_CMD_CFG
3551 + */
3552 +#define MCU_CMD_CFG                    0x022c
3553 +
3554 +/*
3555 + * AC_BK register offsets
3556 + */
3557 +#define TX_BASE_PTR0                   0x0230
3558 +#define TX_MAX_CNT0                    0x0234
3559 +#define TX_CTX_IDX0                    0x0238
3560 +#define TX_DTX_IDX0                    0x023c
3561 +
3562 +/*
3563 + * AC_BE register offsets
3564 + */
3565 +#define TX_BASE_PTR1                   0x0240
3566 +#define TX_MAX_CNT1                    0x0244
3567 +#define TX_CTX_IDX1                    0x0248
3568 +#define TX_DTX_IDX1                    0x024c
3569 +
3570 +/*
3571 + * AC_VI register offsets
3572 + */
3573 +#define TX_BASE_PTR2                   0x0250
3574 +#define TX_MAX_CNT2                    0x0254
3575 +#define TX_CTX_IDX2                    0x0258
3576 +#define TX_DTX_IDX2                    0x025c
3577 +
3578 +/*
3579 + * AC_VO register offsets
3580 + */
3581 +#define TX_BASE_PTR3                   0x0260
3582 +#define TX_MAX_CNT3                    0x0264
3583 +#define TX_CTX_IDX3                    0x0268
3584 +#define TX_DTX_IDX3                    0x026c
3585 +
3586 +/*
3587 + * HCCA register offsets
3588 + */
3589 +#define TX_BASE_PTR4                   0x0270
3590 +#define TX_MAX_CNT4                    0x0274
3591 +#define TX_CTX_IDX4                    0x0278
3592 +#define TX_DTX_IDX4                    0x027c
3593 +
3594 +/*
3595 + * MGMT register offsets
3596 + */
3597 +#define TX_BASE_PTR5                   0x0280
3598 +#define TX_MAX_CNT5                    0x0284
3599 +#define TX_CTX_IDX5                    0x0288
3600 +#define TX_DTX_IDX5                    0x028c
3601 +
3602 +/*
3603 + * Queue register offset macros
3604 + */
3605 +#define TX_QUEUE_REG_OFFSET            0x10
3606 +#define TX_BASE_PTR(__x)               TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3607 +#define TX_MAX_CNT(__x)                        TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3608 +#define TX_CTX_IDX(__x)                        TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3609 +#define TX_DTX_IDX(__x)                        TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3610 +
3611 +/*
3612 + * RX register offsets
3613 + */
3614 +#define RX_BASE_PTR                    0x0290
3615 +#define RX_MAX_CNT                     0x0294
3616 +#define RX_CRX_IDX                     0x0298
3617 +#define RX_DRX_IDX                     0x029c
3618 +
3619 +/*
3620 + * PBF_SYS_CTRL
3621 + * HOST_RAM_WRITE: enable Host program ram write selection
3622 + */
3623 +#define PBF_SYS_CTRL                   0x0400
3624 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3625 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3626 +
3627 +/*
3628 + * PBF registers
3629 + * Most are for debug. Driver doesn't touch PBF register.
3630 + */
3631 +#define PBF_CFG                                0x0408
3632 +#define PBF_MAX_PCNT                   0x040c
3633 +#define PBF_CTRL                       0x0410
3634 +#define PBF_INT_STA                    0x0414
3635 +#define PBF_INT_ENA                    0x0418
3636 +
3637 +/*
3638 + * BCN_OFFSET0:
3639 + */
3640 +#define BCN_OFFSET0                    0x042c
3641 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3642 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3643 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3644 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3645 +
3646 +/*
3647 + * BCN_OFFSET1:
3648 + */
3649 +#define BCN_OFFSET1                    0x0430
3650 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3651 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3652 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3653 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3654 +
3655 +/*
3656 + * PBF registers
3657 + * Most are for debug. Driver doesn't touch PBF register.
3658 + */
3659 +#define TXRXQ_PCNT                     0x0438
3660 +#define PBF_DBG                                0x043c
3661 +
3662 +/*
3663 + * RF registers
3664 + */
3665 +#define        RF_CSR_CFG                      0x0500
3666 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
3667 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
3668 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
3669 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
3670 +
3671 +/*
3672 + * MAC Control/Status Registers(CSR).
3673 + * Some values are set in TU, whereas 1 TU == 1024 us.
3674 + */
3675 +
3676 +/*
3677 + * MAC_CSR0: ASIC revision number.
3678 + * ASIC_REV: 0
3679 + * ASIC_VER: 2860
3680 + */
3681 +#define MAC_CSR0                       0x1000
3682 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3683 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3684 +
3685 +/*
3686 + * MAC_SYS_CTRL:
3687 + */
3688 +#define MAC_SYS_CTRL                   0x1004
3689 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3690 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3691 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3692 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3693 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3694 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3695 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3696 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3697 +
3698 +/*
3699 + * MAC_ADDR_DW0: STA MAC register 0
3700 + */
3701 +#define MAC_ADDR_DW0                   0x1008
3702 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3703 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3704 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3705 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3706 +
3707 +/*
3708 + * MAC_ADDR_DW1: STA MAC register 1
3709 + * UNICAST_TO_ME_MASK:
3710 + * Used to mask off bits from byte 5 of the MAC address
3711 + * to determine the UNICAST_TO_ME bit for RX frames.
3712 + * The full mask is complemented by BSS_ID_MASK:
3713 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3714 + */
3715 +#define MAC_ADDR_DW1                   0x100c
3716 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3717 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3718 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3719 +
3720 +/*
3721 + * MAC_BSSID_DW0: BSSID register 0
3722 + */
3723 +#define MAC_BSSID_DW0                  0x1010
3724 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3725 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3726 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3727 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3728 +
3729 +/*
3730 + * MAC_BSSID_DW1: BSSID register 1
3731 + * BSS_ID_MASK:
3732 + *     0: 1-BSSID mode (BSS index = 0)
3733 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3734 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3735 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3736 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3737 + * BSSID. This will make sure that those bits will be ignored
3738 + * when determining the MY_BSS of RX frames.
3739 + */
3740 +#define MAC_BSSID_DW1                  0x1014
3741 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3742 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3743 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3744 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3745 +
3746 +/*
3747 + * MAX_LEN_CFG: Maximum frame length register.
3748 + * MAX_MPDU: rt2860b max 16k bytes
3749 + * MAX_PSDU: Maximum PSDU length
3750 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3751 + */
3752 +#define MAX_LEN_CFG                    0x1018
3753 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3754 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3755 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3756 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3757 +
3758 +/*
3759 + * BBP_CSR_CFG: BBP serial control register
3760 + * VALUE: Register value to program into BBP
3761 + * REG_NUM: Selected BBP register
3762 + * READ_CONTROL: 0 write BBP, 1 read BBP
3763 + * BUSY: ASIC is busy executing BBP commands
3764 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3765 + * BBP_RW_MODE: 0 serial, 1 paralell
3766 + */
3767 +#define BBP_CSR_CFG                    0x101c
3768 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3769 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3770 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3771 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3772 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3773 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3774 +
3775 +/*
3776 + * RF_CSR_CFG0: RF control register
3777 + * REGID_AND_VALUE: Register value to program into RF
3778 + * BITWIDTH: Selected RF register
3779 + * STANDBYMODE: 0 high when standby, 1 low when standby
3780 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3781 + * BUSY: ASIC is busy executing RF commands
3782 + */
3783 +#define RF_CSR_CFG0                    0x1020
3784 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3785 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3786 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3787 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3788 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3789 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3790 +
3791 +/*
3792 + * RF_CSR_CFG1: RF control register
3793 + * REGID_AND_VALUE: Register value to program into RF
3794 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3795 + *        0: 3 system clock cycle (37.5usec)
3796 + *        1: 5 system clock cycle (62.5usec)
3797 + */
3798 +#define RF_CSR_CFG1                    0x1024
3799 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3800 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3801 +
3802 +/*
3803 + * RF_CSR_CFG2: RF control register
3804 + * VALUE: Register value to program into RF
3805 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3806 + *        0: 3 system clock cycle (37.5usec)
3807 + *        1: 5 system clock cycle (62.5usec)
3808 + */
3809 +#define RF_CSR_CFG2                    0x1028
3810 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3811 +
3812 +/*
3813 + * LED_CFG: LED control
3814 + * color LED's:
3815 + *   0: off
3816 + *   1: blinking upon TX2
3817 + *   2: periodic slow blinking
3818 + *   3: always on
3819 + * LED polarity:
3820 + *   0: active low
3821 + *   1: active high
3822 + */
3823 +#define LED_CFG                                0x102c
3824 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3825 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3826 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3827 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3828 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3829 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3830 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3831 +
3832 +/*
3833 + * XIFS_TIME_CFG: MAC timing
3834 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3835 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3836 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3837 + *     when MAC doesn't reference BBP signal BBRXEND
3838 + * EIFS: unit 1us
3839 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3840 + *
3841 + */
3842 +#define XIFS_TIME_CFG                  0x1100
3843 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3844 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3845 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3846 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3847 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3848 +
3849 +/*
3850 + * BKOFF_SLOT_CFG:
3851 + */
3852 +#define BKOFF_SLOT_CFG                 0x1104
3853 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3854 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3855 +
3856 +/*
3857 + * NAV_TIME_CFG:
3858 + */
3859 +#define NAV_TIME_CFG                   0x1108
3860 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3861 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3862 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3863 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3864 +
3865 +/*
3866 + * CH_TIME_CFG: count as channel busy
3867 + */
3868 +#define CH_TIME_CFG                    0x110c
3869 +
3870 +/*
3871 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3872 + */
3873 +#define PBF_LIFE_TIMER                 0x1110
3874 +
3875 +/*
3876 + * BCN_TIME_CFG:
3877 + * BEACON_INTERVAL: in unit of 1/16 TU
3878 + * TSF_TICKING: Enable TSF auto counting
3879 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3880 + * BEACON_GEN: Enable beacon generator
3881 + */
3882 +#define BCN_TIME_CFG                   0x1114
3883 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3884 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3885 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3886 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3887 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3888 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3889 +
3890 +/*
3891 + * TBTT_SYNC_CFG:
3892 + */
3893 +#define TBTT_SYNC_CFG                  0x1118
3894 +
3895 +/*
3896 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3897 + */
3898 +#define TSF_TIMER_DW0                  0x111c
3899 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3900 +
3901 +/*
3902 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3903 + */
3904 +#define TSF_TIMER_DW1                  0x1120
3905 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3906 +
3907 +/*
3908 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3909 + */
3910 +#define TBTT_TIMER                     0x1124
3911 +
3912 +/*
3913 + * INT_TIMER_CFG:
3914 + */
3915 +#define INT_TIMER_CFG                  0x1128
3916 +
3917 +/*
3918 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3919 + */
3920 +#define INT_TIMER_EN                   0x112c
3921 +
3922 +/*
3923 + * CH_IDLE_STA: channel idle time
3924 + */
3925 +#define CH_IDLE_STA                    0x1130
3926 +
3927 +/*
3928 + * CH_BUSY_STA: channel busy time
3929 + */
3930 +#define CH_BUSY_STA                    0x1134
3931 +
3932 +/*
3933 + * MAC_STATUS_CFG:
3934 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3935 + *     if 1 or higher one of the 2 registers is busy.
3936 + */
3937 +#define MAC_STATUS_CFG                 0x1200
3938 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3939 +
3940 +/*
3941 + * PWR_PIN_CFG:
3942 + */
3943 +#define PWR_PIN_CFG                    0x1204
3944 +
3945 +/*
3946 + * AUTOWAKEUP_CFG: Manual power control / status register
3947 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3948 + * AUTOWAKE: 0:sleep, 1:awake
3949 + */
3950 +#define AUTOWAKEUP_CFG                 0x1208
3951 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3952 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3953 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3954 +
3955 +/*
3956 + * EDCA_AC0_CFG:
3957 + */
3958 +#define EDCA_AC0_CFG                   0x1300
3959 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
3960 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3961 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3962 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3963 +
3964 +/*
3965 + * EDCA_AC1_CFG:
3966 + */
3967 +#define EDCA_AC1_CFG                   0x1304
3968 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
3969 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3970 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3971 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3972 +
3973 +/*
3974 + * EDCA_AC2_CFG:
3975 + */
3976 +#define EDCA_AC2_CFG                   0x1308
3977 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
3978 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3979 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3980 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3981 +
3982 +/*
3983 + * EDCA_AC3_CFG:
3984 + */
3985 +#define EDCA_AC3_CFG                   0x130c
3986 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
3987 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3988 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3989 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3990 +
3991 +/*
3992 + * EDCA_TID_AC_MAP:
3993 + */
3994 +#define EDCA_TID_AC_MAP                        0x1310
3995 +
3996 +/*
3997 + * TX_PWR_CFG_0:
3998 + */
3999 +#define TX_PWR_CFG_0                   0x1314
4000 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
4001 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
4002 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
4003 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
4004 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
4005 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
4006 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
4007 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
4008 +
4009 +/*
4010 + * TX_PWR_CFG_1:
4011 + */
4012 +#define TX_PWR_CFG_1                   0x1318
4013 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
4014 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
4015 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
4016 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
4017 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
4018 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
4019 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
4020 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
4021 +
4022 +/*
4023 + * TX_PWR_CFG_2:
4024 + */
4025 +#define TX_PWR_CFG_2                   0x131c
4026 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
4027 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
4028 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
4029 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
4030 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
4031 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
4032 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
4033 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
4034 +
4035 +/*
4036 + * TX_PWR_CFG_3:
4037 + */
4038 +#define TX_PWR_CFG_3                   0x1320
4039 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
4040 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
4041 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
4042 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
4043 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
4044 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
4045 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
4046 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
4047 +
4048 +/*
4049 + * TX_PWR_CFG_4:
4050 + */
4051 +#define TX_PWR_CFG_4                   0x1324
4052 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
4053 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
4054 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
4055 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
4056 +
4057 +/*
4058 + * TX_PIN_CFG:
4059 + */
4060 +#define TX_PIN_CFG                     0x1328
4061 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
4062 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
4063 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
4064 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
4065 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
4066 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
4067 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
4068 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
4069 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
4070 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
4071 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
4072 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
4073 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
4074 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
4075 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
4076 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
4077 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
4078 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
4079 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
4080 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
4081 +
4082 +/*
4083 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
4084 + */
4085 +#define TX_BAND_CFG                    0x132c
4086 +#define TX_BAND_CFG_HT40_PLUS          FIELD32(0x00000001)
4087 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
4088 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
4089 +
4090 +/*
4091 + * TX_SW_CFG0:
4092 + */
4093 +#define TX_SW_CFG0                     0x1330
4094 +
4095 +/*
4096 + * TX_SW_CFG1:
4097 + */
4098 +#define TX_SW_CFG1                     0x1334
4099 +
4100 +/*
4101 + * TX_SW_CFG2:
4102 + */
4103 +#define TX_SW_CFG2                     0x1338
4104 +
4105 +/*
4106 + * TXOP_THRES_CFG:
4107 + */
4108 +#define TXOP_THRES_CFG                 0x133c
4109 +
4110 +/*
4111 + * TXOP_CTRL_CFG:
4112 + */
4113 +#define TXOP_CTRL_CFG                  0x1340
4114 +
4115 +/*
4116 + * TX_RTS_CFG:
4117 + * RTS_THRES: unit:byte
4118 + * RTS_FBK_EN: enable rts rate fallback
4119 + */
4120 +#define TX_RTS_CFG                     0x1344
4121 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
4122 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
4123 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
4124 +
4125 +/*
4126 + * TX_TIMEOUT_CFG:
4127 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
4128 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
4129 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
4130 + *                it is recommended that:
4131 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
4132 + */
4133 +#define TX_TIMEOUT_CFG                 0x1348
4134 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
4135 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
4136 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
4137 +
4138 +/*
4139 + * TX_RTY_CFG:
4140 + * SHORT_RTY_LIMIT: short retry limit
4141 + * LONG_RTY_LIMIT: long retry limit
4142 + * LONG_RTY_THRE: Long retry threshoold
4143 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
4144 + *                   0:expired by retry limit, 1: expired by mpdu life timer
4145 + * AGG_RTY_MODE: Aggregate MPDU retry mode
4146 + *               0:expired by retry limit, 1: expired by mpdu life timer
4147 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
4148 + */
4149 +#define TX_RTY_CFG                     0x134c
4150 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
4151 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
4152 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
4153 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
4154 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
4155 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
4156 +
4157 +/*
4158 + * TX_LINK_CFG:
4159 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
4160 + * MFB_ENABLE: TX apply remote MFB 1:enable
4161 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
4162 + *                     0: not apply remote remote unsolicit (MFS=7)
4163 + * TX_MRQ_EN: MCS request TX enable
4164 + * TX_RDG_EN: RDG TX enable
4165 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
4166 + * REMOTE_MFB: remote MCS feedback
4167 + * REMOTE_MFS: remote MCS feedback sequence number
4168 + */
4169 +#define TX_LINK_CFG                    0x1350
4170 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
4171 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
4172 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
4173 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
4174 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
4175 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
4176 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
4177 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
4178 +
4179 +/*
4180 + * HT_FBK_CFG0:
4181 + */
4182 +#define HT_FBK_CFG0                    0x1354
4183 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
4184 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
4185 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
4186 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
4187 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
4188 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
4189 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
4190 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
4191 +
4192 +/*
4193 + * HT_FBK_CFG1:
4194 + */
4195 +#define HT_FBK_CFG1                    0x1358
4196 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
4197 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
4198 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
4199 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
4200 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
4201 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
4202 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
4203 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
4204 +
4205 +/*
4206 + * LG_FBK_CFG0:
4207 + */
4208 +#define LG_FBK_CFG0                    0x135c
4209 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
4210 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
4211 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
4212 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
4213 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
4214 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
4215 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
4216 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
4217 +
4218 +/*
4219 + * LG_FBK_CFG1:
4220 + */
4221 +#define LG_FBK_CFG1                    0x1360
4222 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
4223 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
4224 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
4225 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
4226 +
4227 +/*
4228 + * CCK_PROT_CFG: CCK Protection
4229 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4230 + * PROTECT_CTRL: Protection control frame type for CCK TX
4231 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
4232 + * PROTECT_NAV: TXOP protection type for CCK TX
4233 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4234 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4235 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4236 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4237 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4238 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4239 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4240 + * RTS_TH_EN: RTS threshold enable on CCK TX
4241 + */
4242 +#define CCK_PROT_CFG                   0x1364
4243 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
4244 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
4245 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
4246 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
4247 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
4248 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
4249 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
4250 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
4251 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
4252 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
4253 +
4254 +/*
4255 + * OFDM_PROT_CFG: OFDM Protection
4256 + */
4257 +#define OFDM_PROT_CFG                  0x1368
4258 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4259 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4260 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4261 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4262 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4263 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4264 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4265 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4266 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4267 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4268 +
4269 +/*
4270 + * MM20_PROT_CFG: MM20 Protection
4271 + */
4272 +#define MM20_PROT_CFG                  0x136c
4273 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4274 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4275 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4276 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4277 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4278 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4279 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4280 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4281 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4282 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4283 +
4284 +/*
4285 + * MM40_PROT_CFG: MM40 Protection
4286 + */
4287 +#define MM40_PROT_CFG                  0x1370
4288 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4289 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4290 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4291 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4292 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4293 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4294 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4295 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4296 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4297 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4298 +
4299 +/*
4300 + * GF20_PROT_CFG: GF20 Protection
4301 + */
4302 +#define GF20_PROT_CFG                  0x1374
4303 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4304 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4305 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4306 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4307 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4308 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4309 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4310 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4311 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4312 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4313 +
4314 +/*
4315 + * GF40_PROT_CFG: GF40 Protection
4316 + */
4317 +#define GF40_PROT_CFG                  0x1378
4318 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4319 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4320 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4321 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4322 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4323 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4324 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4325 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4326 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4327 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4328 +
4329 +/*
4330 + * EXP_CTS_TIME:
4331 + */
4332 +#define EXP_CTS_TIME                   0x137c
4333 +
4334 +/*
4335 + * EXP_ACK_TIME:
4336 + */
4337 +#define EXP_ACK_TIME                   0x1380
4338 +
4339 +/*
4340 + * RX_FILTER_CFG: RX configuration register.
4341 + */
4342 +#define RX_FILTER_CFG                  0x1400
4343 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
4344 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
4345 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
4346 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4347 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
4348 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
4349 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
4350 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
4351 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
4352 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
4353 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
4354 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
4355 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
4356 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
4357 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
4358 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
4359 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
4360 +
4361 +/*
4362 + * AUTO_RSP_CFG:
4363 + * AUTORESPONDER: 0: disable, 1: enable
4364 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4365 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4366 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4367 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4368 + * DUAL_CTS_EN: Power bit value in control frame
4369 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4370 + */
4371 +#define AUTO_RSP_CFG                   0x1404
4372 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
4373 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
4374 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
4375 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
4376 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
4377 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
4378 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
4379 +
4380 +/*
4381 + * LEGACY_BASIC_RATE:
4382 + */
4383 +#define LEGACY_BASIC_RATE              0x1408
4384 +
4385 +/*
4386 + * HT_BASIC_RATE:
4387 + */
4388 +#define HT_BASIC_RATE                  0x140c
4389 +
4390 +/*
4391 + * HT_CTRL_CFG:
4392 + */
4393 +#define HT_CTRL_CFG                    0x1410
4394 +
4395 +/*
4396 + * SIFS_COST_CFG:
4397 + */
4398 +#define SIFS_COST_CFG                  0x1414
4399 +
4400 +/*
4401 + * RX_PARSER_CFG:
4402 + * Set NAV for all received frames
4403 + */
4404 +#define RX_PARSER_CFG                  0x1418
4405 +
4406 +/*
4407 + * TX_SEC_CNT0:
4408 + */
4409 +#define TX_SEC_CNT0                    0x1500
4410 +
4411 +/*
4412 + * RX_SEC_CNT0:
4413 + */
4414 +#define RX_SEC_CNT0                    0x1504
4415 +
4416 +/*
4417 + * CCMP_FC_MUTE:
4418 + */
4419 +#define CCMP_FC_MUTE                   0x1508
4420 +
4421 +/*
4422 + * TXOP_HLDR_ADDR0:
4423 + */
4424 +#define TXOP_HLDR_ADDR0                        0x1600
4425 +
4426 +/*
4427 + * TXOP_HLDR_ADDR1:
4428 + */
4429 +#define TXOP_HLDR_ADDR1                        0x1604
4430 +
4431 +/*
4432 + * TXOP_HLDR_ET:
4433 + */
4434 +#define TXOP_HLDR_ET                   0x1608
4435 +
4436 +/*
4437 + * QOS_CFPOLL_RA_DW0:
4438 + */
4439 +#define QOS_CFPOLL_RA_DW0              0x160c
4440 +
4441 +/*
4442 + * QOS_CFPOLL_RA_DW1:
4443 + */
4444 +#define QOS_CFPOLL_RA_DW1              0x1610
4445 +
4446 +/*
4447 + * QOS_CFPOLL_QC:
4448 + */
4449 +#define QOS_CFPOLL_QC                  0x1614
4450 +
4451 +/*
4452 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4453 + */
4454 +#define RX_STA_CNT0                    0x1700
4455 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
4456 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
4457 +
4458 +/*
4459 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4460 + */
4461 +#define RX_STA_CNT1                    0x1704
4462 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
4463 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
4464 +
4465 +/*
4466 + * RX_STA_CNT2:
4467 + */
4468 +#define RX_STA_CNT2                    0x1708
4469 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
4470 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
4471 +
4472 +/*
4473 + * TX_STA_CNT0: TX Beacon count
4474 + */
4475 +#define TX_STA_CNT0                    0x170c
4476 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
4477 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
4478 +
4479 +/*
4480 + * TX_STA_CNT1: TX tx count
4481 + */
4482 +#define TX_STA_CNT1                    0x1710
4483 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
4484 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
4485 +
4486 +/*
4487 + * TX_STA_CNT2: TX tx count
4488 + */
4489 +#define TX_STA_CNT2                    0x1714
4490 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
4491 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
4492 +
4493 +/*
4494 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4495 + */
4496 +#define TX_STA_FIFO                    0x1718
4497 +#define TX_STA_FIFO_VALID              FIELD32(0x00000001)
4498 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
4499 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
4500 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4501 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4502 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4503 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4504 +
4505 +/*
4506 + * TX_AGG_CNT: Debug counter
4507 + */
4508 +#define TX_AGG_CNT                     0x171c
4509 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4510 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4511 +
4512 +/*
4513 + * TX_AGG_CNT0:
4514 + */
4515 +#define TX_AGG_CNT0                    0x1720
4516 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4517 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4518 +
4519 +/*
4520 + * TX_AGG_CNT1:
4521 + */
4522 +#define TX_AGG_CNT1                    0x1724
4523 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4524 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4525 +
4526 +/*
4527 + * TX_AGG_CNT2:
4528 + */
4529 +#define TX_AGG_CNT2                    0x1728
4530 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4531 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4532 +
4533 +/*
4534 + * TX_AGG_CNT3:
4535 + */
4536 +#define TX_AGG_CNT3                    0x172c
4537 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4538 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4539 +
4540 +/*
4541 + * TX_AGG_CNT4:
4542 + */
4543 +#define TX_AGG_CNT4                    0x1730
4544 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4545 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4546 +
4547 +/*
4548 + * TX_AGG_CNT5:
4549 + */
4550 +#define TX_AGG_CNT5                    0x1734
4551 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4552 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4553 +
4554 +/*
4555 + * TX_AGG_CNT6:
4556 + */
4557 +#define TX_AGG_CNT6                    0x1738
4558 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4559 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4560 +
4561 +/*
4562 + * TX_AGG_CNT7:
4563 + */
4564 +#define TX_AGG_CNT7                    0x173c
4565 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4566 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4567 +
4568 +/*
4569 + * MPDU_DENSITY_CNT:
4570 + * TX_ZERO_DEL: TX zero length delimiter count
4571 + * RX_ZERO_DEL: RX zero length delimiter count
4572 + */
4573 +#define MPDU_DENSITY_CNT               0x1740
4574 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4575 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4576 +
4577 +/*
4578 + * Security key table memory.
4579 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4580 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4581 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4582 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4583 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4584 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4585 + */
4586 +#define MAC_WCID_BASE                  0x1800
4587 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4588 +#define MAC_IVEIV_TABLE_BASE           0x6000
4589 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4590 +#define SHARED_KEY_TABLE_BASE          0x6c00
4591 +#define SHARED_KEY_MODE_BASE           0x7000
4592 +
4593 +#define MAC_WCID_ENTRY(__idx) \
4594 +       ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4595 +#define PAIRWISE_KEY_ENTRY(__idx) \
4596 +       ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4597 +#define MAC_IVEIV_ENTRY(__idx) \
4598 +       ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4599 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4600 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4601 +#define SHARED_KEY_ENTRY(__idx) \
4602 +       ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4603 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4604 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4605 +
4606 +struct mac_wcid_entry {
4607 +       u8 mac[6];
4608 +       u8 reserved[2];
4609 +} __attribute__ ((packed));
4610 +
4611 +struct hw_key_entry {
4612 +       u8 key[16];
4613 +       u8 tx_mic[8];
4614 +       u8 rx_mic[8];
4615 +} __attribute__ ((packed));
4616 +
4617 +struct mac_iveiv_entry {
4618 +       u8 iv[8];
4619 +} __attribute__ ((packed));
4620 +
4621 +/*
4622 + * MAC_WCID_ATTRIBUTE:
4623 + */
4624 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4625 +#define MAC_WCID_ATTRIBUTE_CIPHER      FIELD32(0x0000000e)
4626 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4627 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4628 +
4629 +/*
4630 + * SHARED_KEY_MODE:
4631 + */
4632 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4633 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4634 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4635 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4636 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4637 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4638 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4639 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4640 +
4641 +/*
4642 + * HOST-MCU communication
4643 + */
4644 +
4645 +/*
4646 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4647 + */
4648 +#define H2M_MAILBOX_CSR                        0x7010
4649 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4650 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4651 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4652 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4653 +
4654 +/*
4655 + * H2M_MAILBOX_CID:
4656 + */
4657 +#define H2M_MAILBOX_CID                        0x7014
4658 +#define H2M_MAILBOX_CID_CMD0           FIELD32(0x000000ff)
4659 +#define H2M_MAILBOX_CID_CMD1           FIELD32(0x0000ff00)
4660 +#define H2M_MAILBOX_CID_CMD2           FIELD32(0x00ff0000)
4661 +#define H2M_MAILBOX_CID_CMD3           FIELD32(0xff000000)
4662 +
4663 +/*
4664 + * H2M_MAILBOX_STATUS:
4665 + */
4666 +#define H2M_MAILBOX_STATUS             0x701c
4667 +
4668 +/*
4669 + * H2M_INT_SRC:
4670 + */
4671 +#define H2M_INT_SRC                    0x7024
4672 +
4673 +/*
4674 + * H2M_BBP_AGENT:
4675 + */
4676 +#define H2M_BBP_AGENT                  0x7028
4677 +
4678 +/*
4679 + * MCU_LEDCS: LED control for MCU Mailbox.
4680 + */
4681 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4682 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4683 +
4684 +/*
4685 + * HW_CS_CTS_BASE:
4686 + * Carrier-sense CTS frame base address.
4687 + * It's where mac stores carrier-sense frame for carrier-sense function.
4688 + */
4689 +#define HW_CS_CTS_BASE                 0x7700
4690 +
4691 +/*
4692 + * HW_DFS_CTS_BASE:
4693 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4694 + */
4695 +#define HW_DFS_CTS_BASE                        0x7780
4696 +
4697 +/*
4698 + * TXRX control registers - base address 0x3000
4699 + */
4700 +
4701 +/*
4702 + * TXRX_CSR1:
4703 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4704 + */
4705 +#define TXRX_CSR1                      0x77d0
4706 +
4707 +/*
4708 + * HW_DEBUG_SETTING_BASE:
4709 + * since NULL frame won't be that long (256 byte)
4710 + * We steal 16 tail bytes to save debugging settings
4711 + */
4712 +#define HW_DEBUG_SETTING_BASE          0x77f0
4713 +#define HW_DEBUG_SETTING_BASE2         0x7770
4714 +
4715 +/*
4716 + * HW_BEACON_BASE
4717 + * In order to support maximum 8 MBSS and its maximum length
4718 + * is 512 bytes for each beacon
4719 + * Three section discontinue memory segments will be used.
4720 + * 1. The original region for BCN 0~3
4721 + * 2. Extract memory from FCE table for BCN 4~5
4722 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4723 + *    It occupied those memory of wcid 238~253 for BCN 6
4724 + *    and wcid 222~237 for BCN 7
4725 + *
4726 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4727 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4728 + */
4729 +#define HW_BEACON_BASE0                        0x7800
4730 +#define HW_BEACON_BASE1                        0x7a00
4731 +#define HW_BEACON_BASE2                        0x7c00
4732 +#define HW_BEACON_BASE3                        0x7e00
4733 +#define HW_BEACON_BASE4                        0x7200
4734 +#define HW_BEACON_BASE5                        0x7400
4735 +#define HW_BEACON_BASE6                        0x5dc0
4736 +#define HW_BEACON_BASE7                        0x5bc0
4737 +
4738 +#define HW_BEACON_OFFSET(__index) \
4739 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4740 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4741 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4742 +
4743 +/*
4744 + * 8051 firmware image.
4745 + */
4746 +#define FIRMWARE_RT2860                        "rt2860.bin"
4747 +#define FIRMWARE_IMAGE_BASE            0x2000
4748 +
4749 +/*
4750 + * BBP registers.
4751 + * The wordsize of the BBP is 8 bits.
4752 + */
4753 +
4754 +/*
4755 + * BBP 1: TX Antenna
4756 + */
4757 +#define BBP1_TX_POWER                  FIELD8(0x07)
4758 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4759 +
4760 +/*
4761 + * BBP 3: RX Antenna
4762 + */
4763 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4764 +#define BBP3_HT40_PLUS                 FIELD8(0x20)
4765 +
4766 +/*
4767 + * BBP 4: Bandwidth
4768 + */
4769 +#define BBP4_TX_BF                     FIELD8(0x01)
4770 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
4771 +
4772 +/*
4773 + * RFCSR registers
4774 + * The wordsize of the RFCSR is 8 bits.
4775 + */
4776 +
4777 +/*
4778 + * RFCSR 6:
4779 + */
4780 +#define RFCSR6_R                       FIELD8(0x03)
4781 +
4782 +/*
4783 + * RFCSR 7:
4784 + */
4785 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
4786 +
4787 +/*
4788 + * RFCSR 12:
4789 + */
4790 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
4791 +
4792 +/*
4793 + * RFCSR 22:
4794 + */
4795 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
4796 +
4797 +/*
4798 + * RFCSR 23:
4799 + */
4800 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
4801 +
4802 +/*
4803 + * RFCSR 30:
4804 + */
4805 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
4806 +
4807 +/*
4808 + * RF registers
4809 + */
4810 +
4811 +/*
4812 + * RF 2
4813 + */
4814 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4815 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4816 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4817 +
4818 +/*
4819 + * RF 3
4820 + */
4821 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4822 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4823 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4824 +
4825 +/*
4826 + * RF 4
4827 + */
4828 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4829 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4830 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4831 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4832 +#define RF4_HT40                       FIELD32(0x00200000)
4833 +
4834 +/*
4835 + * EEPROM content.
4836 + * The wordsize of the EEPROM is 16 bits.
4837 + */
4838 +
4839 +/*
4840 + * EEPROM Version
4841 + */
4842 +#define EEPROM_VERSION                 0x0001
4843 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4844 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4845 +
4846 +/*
4847 + * HW MAC address.
4848 + */
4849 +#define EEPROM_MAC_ADDR_0              0x0002
4850 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4851 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4852 +#define EEPROM_MAC_ADDR_1              0x0003
4853 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4854 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4855 +#define EEPROM_MAC_ADDR_2              0x0004
4856 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4857 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4858 +
4859 +/*
4860 + * EEPROM ANTENNA config
4861 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4862 + * TXPATH: 1: 1T, 2: 2T
4863 + */
4864 +#define        EEPROM_ANTENNA                  0x001a
4865 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4866 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4867 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4868 +
4869 +/*
4870 + * EEPROM NIC config
4871 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4872 + */
4873 +#define        EEPROM_NIC                      0x001b
4874 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4875 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4876 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4877 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4878 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4879 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4880 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4881 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4882 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4883 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4884 +
4885 +/*
4886 + * EEPROM frequency
4887 + */
4888 +#define        EEPROM_FREQ                     0x001d
4889 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4890 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4891 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4892 +
4893 +/*
4894 + * EEPROM LED
4895 + * POLARITY_RDY_G: Polarity RDY_G setting.
4896 + * POLARITY_RDY_A: Polarity RDY_A setting.
4897 + * POLARITY_ACT: Polarity ACT setting.
4898 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4899 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4900 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4901 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4902 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4903 + * LED_MODE: Led mode.
4904 + */
4905 +#define EEPROM_LED1                    0x001e
4906 +#define EEPROM_LED2                    0x001f
4907 +#define EEPROM_LED3                    0x0020
4908 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4909 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4910 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4911 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4912 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4913 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4914 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4915 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4916 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4917 +
4918 +/*
4919 + * EEPROM LNA
4920 + */
4921 +#define EEPROM_LNA                     0x0022
4922 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4923 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4924 +
4925 +/*
4926 + * EEPROM RSSI BG offset
4927 + */
4928 +#define EEPROM_RSSI_BG                 0x0023
4929 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4930 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4931 +
4932 +/*
4933 + * EEPROM RSSI BG2 offset
4934 + */
4935 +#define EEPROM_RSSI_BG2                        0x0024
4936 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4937 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4938 +
4939 +/*
4940 + * EEPROM RSSI A offset
4941 + */
4942 +#define EEPROM_RSSI_A                  0x0025
4943 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4944 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4945 +
4946 +/*
4947 + * EEPROM RSSI A2 offset
4948 + */
4949 +#define EEPROM_RSSI_A2                 0x0026
4950 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4951 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4952 +
4953 +/*
4954 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4955 + *     This is delta in 40MHZ.
4956 + * VALUE: Tx Power dalta value (MAX=4)
4957 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4958 + * TXPOWER: Enable:
4959 + */
4960 +#define EEPROM_TXPOWER_DELTA           0x0028
4961 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4962 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4963 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4964 +
4965 +/*
4966 + * EEPROM TXPOWER 802.11BG
4967 + */
4968 +#define        EEPROM_TXPOWER_BG1              0x0029
4969 +#define        EEPROM_TXPOWER_BG2              0x0030
4970 +#define EEPROM_TXPOWER_BG_SIZE         7
4971 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4972 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4973 +
4974 +/*
4975 + * EEPROM TXPOWER 802.11A
4976 + */
4977 +#define EEPROM_TXPOWER_A1              0x003c
4978 +#define EEPROM_TXPOWER_A2              0x0053
4979 +#define EEPROM_TXPOWER_A_SIZE          6
4980 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4981 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4982 +
4983 +/*
4984 + * EEPROM TXpower byrate: 20MHZ power
4985 + */
4986 +#define EEPROM_TXPOWER_BYRATE          0x006f
4987 +
4988 +/*
4989 + * EEPROM BBP.
4990 + */
4991 +#define        EEPROM_BBP_START                0x0078
4992 +#define EEPROM_BBP_SIZE                        16
4993 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4994 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4995 +
4996 +/*
4997 + * MCU mailbox commands.
4998 + */
4999 +#define MCU_SLEEP                      0x30
5000 +#define MCU_WAKEUP                     0x31
5001 +#define MCU_RADIO_OFF                  0x35
5002 +#define MCU_LED                                0x50
5003 +#define MCU_LED_STRENGTH               0x51
5004 +#define MCU_LED_1                      0x52
5005 +#define MCU_LED_2                      0x53
5006 +#define MCU_LED_3                      0x54
5007 +#define MCU_RADAR                      0x60
5008 +#define MCU_BOOT_SIGNAL                        0x72
5009 +#define MCU_BBP_SIGNAL                 0x80
5010 +
5011 +/*
5012 + * MCU mailbox tokens
5013 + */
5014 +#define TOKEN_WAKUP                    3
5015 +
5016 +/*
5017 + * DMA descriptor defines.
5018 + */
5019 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
5020 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
5021 +#define RXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
5022 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
5023 +
5024 +/*
5025 + * TX descriptor format for TX, PRIO and Beacon Ring.
5026 + */
5027 +
5028 +/*
5029 + * Word0
5030 + */
5031 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
5032 +
5033 +/*
5034 + * Word1
5035 + */
5036 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
5037 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
5038 +#define TXD_W1_BURST                   FIELD32(0x00008000)
5039 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
5040 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
5041 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
5042 +
5043 +/*
5044 + * Word2
5045 + */
5046 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
5047 +
5048 +/*
5049 + * Word3
5050 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
5051 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
5052 + *       0:MGMT, 1:HCCA 2:EDCA
5053 + */
5054 +#define TXD_W3_WIV                     FIELD32(0x01000000)
5055 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
5056 +#define TXD_W3_TCO                     FIELD32(0x20000000)
5057 +#define TXD_W3_UCO                     FIELD32(0x40000000)
5058 +#define TXD_W3_ICO                     FIELD32(0x80000000)
5059 +
5060 +/*
5061 + * TX WI structure
5062 + */
5063 +
5064 +/*
5065 + * Word0
5066 + * FRAG: 1 To inform TKIP engine this is a fragment.
5067 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
5068 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
5069 + * BW: Channel bandwidth 20MHz or 40 MHz
5070 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
5071 + */
5072 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
5073 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
5074 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
5075 +#define TXWI_W0_TS                     FIELD32(0x00000008)
5076 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
5077 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
5078 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
5079 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
5080 +#define TXWI_W0_BW                     FIELD32(0x00800000)
5081 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
5082 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
5083 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
5084 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
5085 +
5086 +/*
5087 + * Word1
5088 + */
5089 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
5090 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
5091 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
5092 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
5093 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
5094 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
5095 +
5096 +/*
5097 + * Word2
5098 + */
5099 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
5100 +
5101 +/*
5102 + * Word3
5103 + */
5104 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
5105 +
5106 +/*
5107 + * RX descriptor format for RX Ring.
5108 + */
5109 +
5110 +/*
5111 + * Word0
5112 + */
5113 +#define RXD_W0_SDP0                    FIELD32(0xffffffff)
5114 +
5115 +/*
5116 + * Word1
5117 + */
5118 +#define RXD_W1_SDL1                    FIELD32(0x00003fff)
5119 +#define RXD_W1_SDL0                    FIELD32(0x3fff0000)
5120 +#define RXD_W1_LS0                     FIELD32(0x40000000)
5121 +#define RXD_W1_DMA_DONE                        FIELD32(0x80000000)
5122 +
5123 +/*
5124 + * Word2
5125 + */
5126 +#define RXD_W2_SDP1                    FIELD32(0xffffffff)
5127 +
5128 +/*
5129 + * Word3
5130 + * AMSDU: RX with 802.3 header, not 802.11 header.
5131 + * DECRYPTED: This frame is being decrypted.
5132 + */
5133 +#define RXD_W3_BA                      FIELD32(0x00000001)
5134 +#define RXD_W3_DATA                    FIELD32(0x00000002)
5135 +#define RXD_W3_NULLDATA                        FIELD32(0x00000004)
5136 +#define RXD_W3_FRAG                    FIELD32(0x00000008)
5137 +#define RXD_W3_UNICAST_TO_ME           FIELD32(0x00000010)
5138 +#define RXD_W3_MULTICAST               FIELD32(0x00000020)
5139 +#define RXD_W3_BROADCAST               FIELD32(0x00000040)
5140 +#define RXD_W3_MY_BSS                  FIELD32(0x00000080)
5141 +#define RXD_W3_CRC_ERROR               FIELD32(0x00000100)
5142 +#define RXD_W3_CIPHER_ERROR            FIELD32(0x00000600)
5143 +#define RXD_W3_AMSDU                   FIELD32(0x00000800)
5144 +#define RXD_W3_HTC                     FIELD32(0x00001000)
5145 +#define RXD_W3_RSSI                    FIELD32(0x00002000)
5146 +#define RXD_W3_L2PAD                   FIELD32(0x00004000)
5147 +#define RXD_W3_AMPDU                   FIELD32(0x00008000)
5148 +#define RXD_W3_DECRYPTED               FIELD32(0x00010000)
5149 +#define RXD_W3_PLCP_SIGNAL             FIELD32(0x00020000)
5150 +#define RXD_W3_PLCP_RSSI               FIELD32(0x00040000)
5151 +
5152 +/*
5153 + * RX WI structure
5154 + */
5155 +
5156 +/*
5157 + * Word0
5158 + */
5159 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
5160 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
5161 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
5162 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
5163 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
5164 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
5165 +
5166 +/*
5167 + * Word1
5168 + */
5169 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
5170 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
5171 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
5172 +#define RXWI_W1_BW                     FIELD32(0x00800000)
5173 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
5174 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
5175 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
5176 +
5177 +/*
5178 + * Word2
5179 + */
5180 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
5181 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
5182 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
5183 +
5184 +/*
5185 + * Word3
5186 + */
5187 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
5188 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
5189 +
5190 +/*
5191 + * Macro's for converting txpower from EEPROM to mac80211 value
5192 + * and from mac80211 value to register value.
5193 + */
5194 +#define MIN_G_TXPOWER  0
5195 +#define MIN_A_TXPOWER  -7
5196 +#define MAX_G_TXPOWER  31
5197 +#define MAX_A_TXPOWER  15
5198 +#define DEFAULT_TXPOWER        5
5199 +
5200 +#define TXPOWER_G_FROM_DEV(__txpower) \
5201 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5202 +
5203 +#define TXPOWER_G_TO_DEV(__txpower) \
5204 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
5205 +
5206 +#define TXPOWER_A_FROM_DEV(__txpower) \
5207 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5208 +
5209 +#define TXPOWER_A_TO_DEV(__txpower) \
5210 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5211 +
5212 +#endif /* RT2800PCI_H */
5213 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5214 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5215 @@ -147,6 +147,12 @@ struct rt2x00_chip {
5216  #define RT2561         0x0302
5217  #define RT2661         0x0401
5218  #define RT2571         0x1300
5219 +#define RT2860         0x0601  /* 2.4GHz PCI/CB */
5220 +#define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
5221 +#define RT2890         0x0701  /* 2.4GHz PCIe */
5222 +#define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
5223 +#define RT2880         0x2880  /* WSOC */
5224 +#define RT3052         0x3052  /* WSOC */
5225  #define RT2870         0x1600
5226
5227         u16 rf;