1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_vr9.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include <ifx_types.h>
50 #include <common_routines.h>
53 #include "ifxmips_atm_core.h"
54 #include "ifxmips_atm_fw_vr9.h"
59 * ####################################
61 * ####################################
67 * ####################################
69 * ####################################
73 * Hardware Init/Uninit Functions
75 static inline void init_pmu(void);
76 static inline void uninit_pmu(void);
77 static inline void reset_ppe(void);
78 static inline void init_pdma(void);
79 static inline void init_mailbox(void);
80 static inline void init_atm_tc(void);
81 static inline void clear_share_buffer(void);
86 * ####################################
88 * ####################################
94 * ####################################
96 * ####################################
99 static inline void init_pmu(void)
101 //*PMU_PWDCR &= ~((1 << 29) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18));
102 //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
103 PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
104 PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
105 PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
106 PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
107 PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
108 DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
111 static inline void uninit_pmu(void)
113 PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
114 PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
115 PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
116 PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
117 PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
118 DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
119 //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
122 static inline void reset_ppe(void)
126 ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
128 ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
130 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
132 *PP32_SRST &= ~0x000303CF;
134 *PP32_SRST |= 0x000303CF;
139 static inline void init_pdma(void)
141 IFX_REG_W32(0x08, PDMA_CFG);
142 IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
143 IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
146 static inline void init_mailbox(void)
148 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
149 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
150 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
151 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
154 static inline void init_atm_tc(void)
156 /* clear sync state */
160 /* enable keep IDLE */
161 // *SFSM_CFG0 |= 1 << 15;
162 // *SFSM_CFG1 |= 1 << 15;
165 static inline void clear_share_buffer(void)
171 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
175 for ( i = 0; i < SB_RAM6_DWLEN; i++ )
181 * Download PPE firmware binary code.
183 * pp32 --- int, which pp32 core
184 * src --- u32 *, binary code buffer
185 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
187 * int --- IFX_SUCCESS: Success
190 static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
192 unsigned int clr, set;
195 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
196 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
199 clr = pp32 ? 0xF0 : 0x0F;
200 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
201 set = pp32 ? (3 << 6): (2 << 2);
204 IFX_REG_W32_MASK(clr, set, CDM_CFG);
207 dest = CDM_CODE_MEMORY(pp32, 0);
208 while ( code_dword_len-- > 0 )
209 IFX_REG_W32(*code_src++, dest++);
212 dest = CDM_DATA_MEMORY(pp32, 0);
213 while ( data_dword_len-- > 0 )
214 IFX_REG_W32(*data_src++, dest++);
222 * ####################################
224 * ####################################
227 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
229 ASSERT(major != NULL, "pointer is NULL");
230 ASSERT(minor != NULL, "pointer is NULL");
232 #ifdef VER_IN_FIRMWARE
233 *major = FW_VER_ID->major;
234 *minor = FW_VER_ID->minor;
236 *major = ATM_FW_VER_MAJOR;
237 *minor = ATM_FW_VER_MINOR;
241 void ifx_atm_init_chip(void)
253 clear_share_buffer();
256 void ifx_atm_uninit_chip(void)
263 * Initialize and start up PP32.
267 * int --- IFX_SUCCESS: Success
270 int ifx_pp32_start(int pp32)
272 unsigned int mask = 1 << (pp32 << 4);
275 /* download firmware */
276 ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
277 if ( ret != IFX_SUCCESS )
281 IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
283 /* idle for a while to let PP32 init itself */
297 void ifx_pp32_stop(int pp32)
299 unsigned int mask = 1 << (pp32 << 4);
302 IFX_REG_W32_MASK(0, mask, PP32_FREEZE);