1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_fw_regs_common.h
5 ** MODULES : ATM (ADSL)
9 ** DESCRIPTION : ATM Driver (Firmware Register Structures)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
28 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
29 #define IFXMIPS_ATM_FW_REGS_COMMON_H
33 #if defined(CONFIG_DANUBE)
34 #include "ifxmips_atm_fw_regs_danube.h"
35 #elif defined(CONFIG_AMAZON_SE)
36 #include "ifxmips_atm_fw_regs_amazon_se.h"
37 #elif defined(CONFIG_AR9)
38 #include "ifxmips_atm_fw_regs_ar9.h"
39 #elif defined(CONFIG_VR9)
40 #include "ifxmips_atm_fw_regs_vr9.h"
42 #error Platform is not specified!
50 #if defined(__BIG_ENDIAN)
51 struct uni_cell_header {
59 struct uni_cell_header {
66 #endif // defined(__BIG_ENDIAN)
69 * Inband Header and Trailer
71 #if defined(__BIG_ENDIAN)
72 struct rx_inband_trailer {
76 unsigned int stw_res1:4;
77 unsigned int stw_clp :1;
78 unsigned int stw_ec :1;
79 unsigned int stw_uu :1;
80 unsigned int stw_cpi :1;
81 unsigned int stw_ovz :1;
82 unsigned int stw_mfl :1;
83 unsigned int stw_usz :1;
84 unsigned int stw_crc :1;
85 unsigned int stw_il :1;
86 unsigned int stw_ra :1;
87 unsigned int stw_res2:2;
96 struct tx_inband_header {
100 unsigned int vci :16;
107 unsigned int res1 :8;
110 struct rx_inband_trailer {
112 unsigned int stw_res2:2;
113 unsigned int stw_ra :1;
114 unsigned int stw_il :1;
115 unsigned int stw_crc :1;
116 unsigned int stw_usz :1;
117 unsigned int stw_mfl :1;
118 unsigned int stw_ovz :1;
119 unsigned int stw_cpi :1;
120 unsigned int stw_uu :1;
121 unsigned int stw_ec :1;
122 unsigned int stw_clp :1;
123 unsigned int stw_res1:4;
129 unsigned int vci :16;
134 struct tx_inband_header {
138 unsigned int vci :16;
142 unsigned int res1 :8;
147 #endif // defined(__BIG_ENDIAN)
150 * MIB Table Maintained by Firmware
152 struct wan_mib_table {
154 u32 wrx_drophtu_cell;
158 u32 wrx_dropdes_cell;
159 u32 wrx_correct_cell;
169 * Host-PPE Communication Data Structure
172 #if defined(__BIG_ENDIAN)
174 unsigned int family :4;
175 unsigned int fwtype :4;
176 unsigned int interface :4;
177 unsigned int fwmode :4;
178 unsigned int major :8;
179 unsigned int minor :8;
182 struct wrx_queue_config {
184 unsigned int res2 :27;
185 unsigned int dmach :4;
186 unsigned int errdp :1;
188 unsigned int oversize :16;
189 unsigned int undersize :16;
191 unsigned int res1 :16;
192 unsigned int mfs :16;
194 unsigned int uumask :8;
195 unsigned int cpimask :8;
196 unsigned int uuexp :8;
197 unsigned int cpiexp :8;
200 struct wrx_queue_context {
202 unsigned int curr_len :16;
203 unsigned int res0 :12;
206 unsigned int clp1 :1;
207 unsigned int aal5dp :1;
213 unsigned int curr_des0;
214 unsigned int curr_des1;
217 unsigned int res1[11];
219 unsigned int last_dword;
222 struct wtx_port_config {
223 unsigned int res1 :27;
225 unsigned int qsben :1;
228 struct wtx_queue_config {
229 unsigned int res1 :25;
230 unsigned int sbid :1;
231 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
232 unsigned int res2 :1;
233 unsigned int qsben :1;
236 struct wrx_desc_context {
237 unsigned int dmach_wrptr : 16;
238 unsigned int dmach_rdptr : 16;
240 unsigned int res0 : 16;
241 unsigned int dmach_fcnt : 16;
243 unsigned int res1 : 11;
244 unsigned int desbuf_wrptr : 5;
245 unsigned int res2 : 11;
246 unsigned int desbuf_rdptr : 5;
248 unsigned int res3 : 27;
249 unsigned int desbuf_vcnt : 5;
252 struct wrx_dma_channel_config {
254 unsigned int res1 :1;
255 unsigned int mode :2;
256 unsigned int rlcfg :1;
257 unsigned int desba :28;
259 unsigned int chrl :16;
260 unsigned int clp1th :16;
262 unsigned int deslen :16;
263 unsigned int vlddes :16;
266 struct wtx_dma_channel_config {
268 unsigned int res2 :1;
269 unsigned int mode :2;
270 unsigned int res3 :1;
271 unsigned int desba :28;
273 unsigned int res1 :32;
275 unsigned int deslen :16;
276 unsigned int vlddes :16;
280 unsigned int res1 :1;
284 unsigned int vci :16;
292 unsigned int pid_mask :2;
293 unsigned int vpi_mask :8;
294 unsigned int vci_mask :16;
295 unsigned int pti_mask :3;
296 unsigned int clear :1;
300 unsigned int res1 :12;
301 unsigned int cellid :4;
302 unsigned int res2 :5;
303 unsigned int type :1;
305 unsigned int res3 :5;
309 struct rx_descriptor {
315 unsigned int res1 :3;
316 unsigned int byteoff :2;
317 unsigned int res2 :2;
320 unsigned int datalen :16;
322 unsigned int res3 :4;
323 unsigned int dataptr :28;
326 struct tx_descriptor {
332 unsigned int byteoff :5;
333 unsigned int res1 :5;
334 unsigned int iscell :1;
336 unsigned int datalen :16;
338 unsigned int res2 :4;
339 unsigned int dataptr :28;
342 struct wrx_queue_config {
344 unsigned int errdp :1;
345 unsigned int dmach :4;
346 unsigned int res2 :27;
348 unsigned int undersize :16;
349 unsigned int oversize :16;
351 unsigned int mfs :16;
352 unsigned int res1 :16;
354 unsigned int cpiexp :8;
355 unsigned int uuexp :8;
356 unsigned int cpimask :8;
357 unsigned int uumask :8;
360 struct wtx_port_config {
361 unsigned int qsben :1;
363 unsigned int res1 :27;
366 struct wtx_queue_config {
367 unsigned int qsben :1;
368 unsigned int res2 :1;
369 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
370 unsigned int sbid :1;
371 unsigned int res1 :25;
374 struct wrx_dma_channel_config
377 unsigned int desba :28;
378 unsigned int rlcfg :1;
379 unsigned int mode :2;
380 unsigned int res1 :1;
382 unsigned int clp1th :16;
383 unsigned int chrl :16;
385 unsigned int vlddes :16;
386 unsigned int deslen :16;
389 struct wtx_dma_channel_config {
391 unsigned int desba :28;
392 unsigned int res3 :1;
393 unsigned int mode :2;
394 unsigned int res2 :1;
396 unsigned int res1 :32;
398 unsigned int vlddes :16;
399 unsigned int deslen :16;
402 struct rx_descriptor {
404 unsigned int dataptr :28;
405 unsigned int res3 :4;
407 unsigned int datalen :16;
410 unsigned int res2 :2;
411 unsigned int byteoff :2;
412 unsigned int res1 :3;
419 struct tx_descriptor {
421 unsigned int dataptr :28;
422 unsigned int res2 :4;
424 unsigned int datalen :16;
426 unsigned int iscell :1;
427 unsigned int res1 :5;
428 unsigned int byteoff :5;
434 #endif // defined(__BIG_ENDIAN)
436 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
437 #if defined(__BIG_ENDIAN)
439 struct Retx_adsl_ppe_intf {
440 unsigned int res0_0 : 16;
441 unsigned int dtu_sid : 8;
442 unsigned int dtu_timestamp : 8;
444 unsigned int res1_0 : 16;
445 unsigned int local_time : 8;
446 unsigned int res1_1 : 5;
447 unsigned int is_last_cw : 1;
448 unsigned int reinit_flag : 1;
449 unsigned int is_bad_cw : 1;
452 struct Retx_adsl_ppe_intf_rec {
454 unsigned int local_time : 8;
455 unsigned int res1_1 : 5;
456 unsigned int is_last_cw : 1;
457 unsigned int reinit_flag : 1;
458 unsigned int is_bad_cw : 1;
460 unsigned int dtu_sid : 8;
461 unsigned int dtu_timestamp : 8;
465 struct Retx_mode_cfg {
466 unsigned int res0 :8;
467 unsigned int invld_range :8; // used for rejecting the too late arrival of the retransmitted DTU
468 unsigned int buff_size :8; // the total number of cells in playout buffer is 32 * buff_size
469 unsigned int res1 :7;
470 unsigned int retx_en :1;
473 struct Retx_Tsync_cfg {
474 unsigned int fw_alpha :16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)
475 unsigned int sync_inp :16; // reserved
479 unsigned int res0 :8;
480 unsigned int td_max :8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
481 unsigned int res1 :8;
482 unsigned int td_min :8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
485 struct Retx_MIB_Timer_cfg {
486 unsigned int ticks_per_sec : 16;
487 unsigned int tick_cycle : 16;
490 struct DTU_stat_info {
491 unsigned int complete : 1;
492 unsigned int bad : 1;
493 unsigned int res0_0 : 14;
494 unsigned int time_stamp : 8;
495 unsigned int cell_cnt : 8;
497 unsigned int dtu_rd_ptr : 16;
498 unsigned int dtu_wr_ptr : 16;
501 struct Retx_ctrl_field {
502 unsigned int res0 : 1;
504 unsigned int l2_drop : 1;
505 unsigned int res1 : 13;
506 unsigned int retx : 1;
508 unsigned int dtu_sid : 8;
509 unsigned int cell_sid : 8;
513 #error Little Endian is not supported yet.
517 unsigned int update_flag; // 00
518 unsigned int res0; // 04
519 unsigned int MinDelayrt; // 08
520 unsigned int MaxDelayrt; // 0C
521 unsigned int res1; // 10
522 unsigned int res2; // 14
523 unsigned int RetxEnable; // 18
524 unsigned int ServiceSpecificReTx; // 1C
525 unsigned int res3; // 20
526 unsigned int ReTxPVC; // 24
527 unsigned int res4; // 28
528 unsigned int res5; // 2C
529 unsigned int res6; // 30
530 unsigned int res7; // 34
531 unsigned int res8; // 38
532 unsigned int res9; // 3C
533 unsigned int res10; // 40
534 unsigned int res11; // 44
535 unsigned int res12; // 48
536 unsigned int res13; // 4C
537 unsigned int RxDtuCorruptedCNT; // 50
538 unsigned int RxRetxDtuUnCorrectedCNT;// 54
539 unsigned int RxLastEFB; // 58
540 unsigned int RxDtuCorrectedCNT; // 5C
546 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H