1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_danube.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include <lantiq_soc.h>
49 #include "ifxmips_compat.h"
50 #include "ifxmips_atm_core.h"
51 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
52 #include "ifxmips_atm_fw_danube_retx.h"
54 #include "ifxmips_atm_fw_danube.h"
58 * ####################################
60 * ####################################
66 #define EMA_CMD_BUF_LEN 0x0040
67 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
68 #define EMA_DATA_BUF_LEN 0x0100
69 #define EMA_DATA_BASE_ADDR (0x00001900 << 2)
70 #define EMA_WRITE_BURST 0x2
71 #define EMA_READ_BURST 0x2
76 * ####################################
78 * ####################################
82 * Hardware Init/Uninit Functions
84 static inline void init_pmu(void);
85 static inline void uninit_pmu(void);
86 static inline void reset_ppe(void);
87 static inline void init_ema(void);
88 static inline void init_mailbox(void);
89 static inline void init_atm_tc(void);
90 static inline void clear_share_buffer(void);
95 * ####################################
97 * ####################################
103 * ####################################
105 * ####################################
108 static inline void init_pmu(void)
110 //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
111 //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
112 PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
113 PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
114 PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
115 PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
116 PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
117 DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
120 static inline void uninit_pmu(void)
122 PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
123 PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
124 PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
125 PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
126 PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
127 DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
128 //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
131 static inline void reset_ppe(void)
134 unsigned int etop_cfg;
135 unsigned int etop_mdio_cfg;
136 unsigned int etop_ig_plen_ctrl;
137 unsigned int enet_mac_cfg;
139 etop_cfg = *IFX_PP32_ETOP_CFG;
140 etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
141 etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
142 enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
144 *IFX_PP32_ETOP_CFG &= ~0x03C0;
147 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
149 *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
150 *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
151 *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
152 *IFX_PP32_ETOP_CFG = etop_cfg;
156 static inline void init_ema(void)
158 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
159 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
160 IFX_REG_W32(0x000000FF, EMA_IER);
161 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
164 static inline void init_mailbox(void)
166 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
167 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
168 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
169 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
172 static inline void init_atm_tc(void)
174 IFX_REG_W32(0x0000, DREG_AT_CTRL);
175 IFX_REG_W32(0x0000, DREG_AR_CTRL);
176 IFX_REG_W32(0x0, DREG_AT_IDLE0);
177 IFX_REG_W32(0x0, DREG_AT_IDLE1);
178 IFX_REG_W32(0x0, DREG_AR_IDLE0);
179 IFX_REG_W32(0x0, DREG_AR_IDLE1);
180 IFX_REG_W32(0x40, RFBI_CFG);
181 IFX_REG_W32(0x1600, SFSM_DBA0);
182 IFX_REG_W32(0x1718, SFSM_DBA1);
183 IFX_REG_W32(0x1830, SFSM_CBA0);
184 IFX_REG_W32(0x1844, SFSM_CBA1);
185 IFX_REG_W32(0x14014, SFSM_CFG0);
186 IFX_REG_W32(0x14014, SFSM_CFG1);
187 IFX_REG_W32(0x1858, FFSM_DBA0);
188 IFX_REG_W32(0x18AC, FFSM_DBA1);
189 IFX_REG_W32(0x10006, FFSM_CFG0);
190 IFX_REG_W32(0x10006, FFSM_CFG1);
191 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
192 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
195 static inline void clear_share_buffer(void)
197 volatile u32 *p = SB_RAM0_ADDR(0);
200 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
206 * Download PPE firmware binary code.
208 * src --- u32 *, binary code buffer
209 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
211 * int --- IFX_SUCCESS: Success
214 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
218 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
219 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
222 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
223 IFX_REG_W32(0x00, CDM_CFG);
225 IFX_REG_W32(0x04, CDM_CFG);
228 dest = CDM_CODE_MEMORY(0, 0);
229 while ( code_dword_len-- > 0 )
230 IFX_REG_W32(*code_src++, dest++);
233 dest = CDM_DATA_MEMORY(0, 0);
234 while ( data_dword_len-- > 0 )
235 IFX_REG_W32(*data_src++, dest++);
243 * ####################################
245 * ####################################
248 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
250 ASSERT(major != NULL, "pointer is NULL");
251 ASSERT(minor != NULL, "pointer is NULL");
253 #if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE)
254 *major = FW_VER_ID->major;
255 *minor = FW_VER_ID->minor;
257 *major = ATM_FW_VER_MAJOR;
258 *minor = ATM_FW_VER_MINOR;
262 void ifx_atm_init_chip(void)
274 clear_share_buffer();
277 void ifx_atm_uninit_chip(void)
284 * Initialize and start up PP32.
288 * int --- IFX_SUCCESS: Success
291 int ifx_pp32_start(int pp32)
295 /* download firmware */
296 ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
297 if ( ret != IFX_SUCCESS )
301 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
303 /* idle for a while to let PP32 init itself */
317 void ifx_pp32_stop(int pp32)
320 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);