ath9k: fix more-data flag for buffered multicast packets
[oweals/openwrt.git] / package / kernel / mac80211 / patches / 020-19-rt2x00-add-support-for-MT7620.patch
1 From 41977e86c984fcdddb454a3d7887de5d47b5f530 Mon Sep 17 00:00:00 2001
2 From: Roman Yeryomin <roman@advem.lv>
3 Date: Tue, 21 Mar 2017 00:43:00 +0100
4 Subject: [PATCH 19/19] rt2x00: add support for MT7620
5
6 Basic support for MT7620 built-in wireless radio was added to
7 OpenWrt in r41441. It has seen some heavy cleaning and refactoring
8 since in order to match the Kernel's code quality standards.
9
10 Signed-off-by: Roman Yeryomin <roman@advem.lv>
11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
12 Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
13 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
14 ---
15  drivers/net/wireless/ralink/rt2x00/Kconfig     |    2 +-
16  drivers/net/wireless/ralink/rt2x00/rt2800.h    |  177 +++
17  drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 1421 +++++++++++++++++++++++-
18  drivers/net/wireless/ralink/rt2x00/rt2800lib.h |    4 +
19  drivers/net/wireless/ralink/rt2x00/rt2x00.h    |    1 +
20  5 files changed, 1578 insertions(+), 27 deletions(-)
21
22 --- a/drivers/net/wireless/ralink/rt2x00/Kconfig
23 +++ b/drivers/net/wireless/ralink/rt2x00/Kconfig
24 @@ -210,7 +210,7 @@ endif
25  config RT2800SOC
26         tristate "Ralink WiSoC support"
27         depends on m
28 -       depends on SOC_RT288X || SOC_RT305X
29 +       depends on SOC_RT288X || SOC_RT305X || SOC_MT7620
30         select RT2X00_LIB_SOC
31         select RT2X00_LIB_MMIO
32         select RT2X00_LIB_CRYPTO
33 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
34 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
35 @@ -79,6 +79,7 @@
36  #define RF5372                         0x5372
37  #define RF5390                         0x5390
38  #define RF5392                         0x5392
39 +#define RF7620                         0x7620
40  
41  /*
42   * Chipset revisions.
43 @@ -639,6 +640,24 @@
44  #define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
45  
46  /*
47 + * MT7620 RF registers (reversed order)
48 + */
49 +#define RF_CSR_CFG_DATA_MT7620         FIELD32(0x0000ff00)
50 +#define RF_CSR_CFG_REGNUM_MT7620       FIELD32(0x03ff0000)
51 +#define RF_CSR_CFG_WRITE_MT7620                FIELD32(0x00000010)
52 +#define RF_CSR_CFG_BUSY_MT7620         FIELD32(0x00000001)
53 +
54 +/* undocumented registers for calibration of new MAC */
55 +#define RF_CONTROL0                    0x0518
56 +#define RF_BYPASS0                     0x051c
57 +#define RF_CONTROL1                    0x0520
58 +#define RF_BYPASS1                     0x0524
59 +#define RF_CONTROL2                    0x0528
60 +#define RF_BYPASS2                     0x052c
61 +#define RF_CONTROL3                    0x0530
62 +#define RF_BYPASS3                     0x0534
63 +
64 +/*
65   * EFUSE_CSR: RT30x0 EEPROM
66   */
67  #define EFUSE_CTRL                     0x0580
68 @@ -1022,6 +1041,16 @@
69  #define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
70  
71  /*
72 + * MIMO_PS_CFG: MIMO Power-save Configuration
73 + */
74 +#define MIMO_PS_CFG                    0x1210
75 +#define MIMO_PS_CFG_MMPS_BB_EN         FIELD32(0x00000001)
76 +#define MIMO_PS_CFG_MMPS_RX_ANT_NUM    FIELD32(0x00000006)
77 +#define MIMO_PS_CFG_MMPS_RF_EN         FIELD32(0x00000008)
78 +#define MIMO_PS_CFG_RX_STBY_POL                FIELD32(0x00000010)
79 +#define MIMO_PS_CFG_RX_RX_STBY0                FIELD32(0x00000020)
80 +
81 +/*
82   * EDCA_AC0_CFG:
83   */
84  #define EDCA_AC0_CFG                   0x1300
85 @@ -1095,6 +1124,12 @@
86  #define TX_PWR_CFG_0_OFDM6_CH1         FIELD32(0x00f00000)
87  #define TX_PWR_CFG_0_OFDM12_CH0                FIELD32(0x0f000000)
88  #define TX_PWR_CFG_0_OFDM12_CH1                FIELD32(0xf0000000)
89 +/* bits for new 2T devices */
90 +#define TX_PWR_CFG_0B_1MBS_2MBS                FIELD32(0x000000ff)
91 +#define TX_PWR_CFG_0B_5MBS_11MBS               FIELD32(0x0000ff00)
92 +#define TX_PWR_CFG_0B_6MBS_9MBS                FIELD32(0x00ff0000)
93 +#define TX_PWR_CFG_0B_12MBS_18MBS      FIELD32(0xff000000)
94 +
95  
96  /*
97   * TX_PWR_CFG_1:
98 @@ -1117,6 +1152,11 @@
99  #define TX_PWR_CFG_1_MCS0_CH1          FIELD32(0x00f00000)
100  #define TX_PWR_CFG_1_MCS2_CH0          FIELD32(0x0f000000)
101  #define TX_PWR_CFG_1_MCS2_CH1          FIELD32(0xf0000000)
102 +/* bits for new 2T devices */
103 +#define TX_PWR_CFG_1B_24MBS_36MBS      FIELD32(0x000000ff)
104 +#define TX_PWR_CFG_1B_48MBS            FIELD32(0x0000ff00)
105 +#define TX_PWR_CFG_1B_MCS0_MCS1                FIELD32(0x00ff0000)
106 +#define TX_PWR_CFG_1B_MCS2_MCS3                FIELD32(0xff000000)
107  
108  /*
109   * TX_PWR_CFG_2:
110 @@ -1139,6 +1179,11 @@
111  #define TX_PWR_CFG_2_MCS8_CH1          FIELD32(0x00f00000)
112  #define TX_PWR_CFG_2_MCS10_CH0         FIELD32(0x0f000000)
113  #define TX_PWR_CFG_2_MCS10_CH1         FIELD32(0xf0000000)
114 +/* bits for new 2T devices */
115 +#define TX_PWR_CFG_2B_MCS4_MCS5                FIELD32(0x000000ff)
116 +#define TX_PWR_CFG_2B_MCS6_MCS7                FIELD32(0x0000ff00)
117 +#define TX_PWR_CFG_2B_MCS8_MCS9                FIELD32(0x00ff0000)
118 +#define TX_PWR_CFG_2B_MCS10_MCS11      FIELD32(0xff000000)
119  
120  /*
121   * TX_PWR_CFG_3:
122 @@ -1161,6 +1206,11 @@
123  #define TX_PWR_CFG_3_STBC0_CH1         FIELD32(0x00f00000)
124  #define TX_PWR_CFG_3_STBC2_CH0         FIELD32(0x0f000000)
125  #define TX_PWR_CFG_3_STBC2_CH1         FIELD32(0xf0000000)
126 +/* bits for new 2T devices */
127 +#define TX_PWR_CFG_3B_MCS12_MCS13      FIELD32(0x000000ff)
128 +#define TX_PWR_CFG_3B_MCS14            FIELD32(0x0000ff00)
129 +#define TX_PWR_CFG_3B_STBC_MCS0_MCS1   FIELD32(0x00ff0000)
130 +#define TX_PWR_CFG_3B_STBC_MCS2_MSC3   FIELD32(0xff000000)
131  
132  /*
133   * TX_PWR_CFG_4:
134 @@ -1175,6 +1225,9 @@
135  #define TX_PWR_CFG_4_STBC4_CH1         FIELD32(0x000000f0)
136  #define TX_PWR_CFG_4_STBC6_CH0         FIELD32(0x00000f00)
137  #define TX_PWR_CFG_4_STBC6_CH1         FIELD32(0x0000f000)
138 +/* bits for new 2T devices */
139 +#define TX_PWR_CFG_4B_STBC_MCS4_MCS5   FIELD32(0x000000ff)
140 +#define TX_PWR_CFG_4B_STBC_MCS6                FIELD32(0x0000ff00)
141  
142  /*
143   * TX_PIN_CFG:
144 @@ -1201,6 +1254,8 @@
145  #define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
146  #define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
147  #define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
148 +#define TX_PIN_CFG_RFRX_EN             FIELD32(0x00100000)
149 +#define TX_PIN_CFG_RFRX_POL            FIELD32(0x00200000)
150  #define TX_PIN_CFG_PA_PE_A2_EN         FIELD32(0x01000000)
151  #define TX_PIN_CFG_PA_PE_G2_EN         FIELD32(0x02000000)
152  #define TX_PIN_CFG_PA_PE_A2_POL                FIELD32(0x04000000)
153 @@ -1547,6 +1602,95 @@
154  #define TX_PWR_CFG_4_EXT_STBC4_CH2     FIELD32(0x0000000f)
155  #define TX_PWR_CFG_4_EXT_STBC6_CH2     FIELD32(0x00000f00)
156  
157 +/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
158 + * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
159 + */
160 +#define TX0_RF_GAIN_CORRECT            0x13a0
161 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
162 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
163 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
164 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
165 +
166 +#define TX1_RF_GAIN_CORRECT            0x13a4
167 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
168 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
169 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
170 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
171 +
172 +/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
173 + * Format: 7-bit, signed value
174 + * Unit: 0.5 dB, Range: -20 dB to -5 dB
175 + */
176 +#define TX0_RF_GAIN_ATTEN              0x13a8
177 +#define TX0_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
178 +#define TX0_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
179 +#define TX0_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
180 +#define TX0_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
181 +#define TX1_RF_GAIN_ATTEN              0x13ac
182 +#define TX1_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
183 +#define TX1_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
184 +#define TX1_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
185 +#define TX1_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
186 +
187 +/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
188 + * TX_ALC_LIMIT_n: TXn upper limit
189 + * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
190 + * Unit: 0.5 dB, Range: 0 to 23.5 dB
191 + */
192 +#define TX_ALC_CFG_0                   0x13b0
193 +#define TX_ALC_CFG_0_CH_INIT_0         FIELD32(0x0000003f)
194 +#define TX_ALC_CFG_0_CH_INIT_1         FIELD32(0x00003f00)
195 +#define TX_ALC_CFG_0_LIMIT_0           FIELD32(0x003f0000)
196 +#define TX_ALC_CFG_0_LIMIT_1           FIELD32(0x3f000000)
197 +
198 +/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
199 + * TX_TEMP_COMP:      TX Power Temperature Compensation
200 + *                    Unit: 0.5 dB, Range: -10 dB to 10 dB
201 + * TXn_GAIN_FINE:     TXn Gain Fine Adjustment
202 + *                    Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
203 + * RF_TOS_DLY:        Sets the RF_TOS_EN assertion delay after
204 + *                    deassertion of PA_PE.
205 + *                    Unit: 0.25 usec
206 + * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
207 + * RF_TOS_TIMEOUT:    time-out value for RF_TOS_ENABLE
208 + *                    deassertion if RF_TOS_DONE is missing.
209 + *                    Unit: 0.25 usec
210 + * RF_TOS_ENABLE:     TX offset calibration enable
211 + * ROS_BUSY_EN:       RX offset calibration busy enable
212 + */
213 +#define TX_ALC_CFG_1                   0x13b4
214 +#define TX_ALC_CFG_1_TX_TEMP_COMP      FIELD32(0x0000003f)
215 +#define TX_ALC_CFG_1_TX0_GAIN_FINE     FIELD32(0x00000f00)
216 +#define TX_ALC_CFG_1_TX1_GAIN_FINE     FIELD32(0x0000f000)
217 +#define TX_ALC_CFG_1_RF_TOS_DLY                FIELD32(0x00070000)
218 +#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
219 +#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
220 +#define TX_ALC_CFG_1_RF_TOS_TIMEOUT    FIELD32(0x3f000000)
221 +#define TX_ALC_CFG_1_RF_TOS_ENABLE     FIELD32(0x40000000)
222 +#define TX_ALC_CFG_1_ROS_BUSY_EN       FIELD32(0x80000000)
223 +
224 +/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
225 + * Format: 5-bit signed values
226 + * Unit: 0.5 dB, Range: -8 dB to 7 dB
227 + */
228 +#define TX0_BB_GAIN_ATTEN              0x13c0
229 +#define TX0_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
230 +#define TX0_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
231 +#define TX0_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
232 +#define TX0_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
233 +#define TX1_BB_GAIN_ATTEN              0x13c4
234 +#define TX1_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
235 +#define TX1_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
236 +#define TX1_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
237 +#define TX1_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
238 +
239 +/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
240 +#define TX_ALC_VGA3                    0x13c8
241 +#define TX_ALC_VGA3_TX0_ALC_VGA3       FIELD32(0x0000001f)
242 +#define TX_ALC_VGA3_TX1_ALC_VGA3       FIELD32(0x00001f00)
243 +#define TX_ALC_VGA3_TX0_ALC_VGA2       FIELD32(0x001f0000)
244 +#define TX_ALC_VGA3_TX1_ALC_VGA2       FIELD32(0x1f000000)
245 +
246  /* TX_PWR_CFG_7 */
247  #define TX_PWR_CFG_7                   0x13d4
248  #define TX_PWR_CFG_7_OFDM54_CH0                FIELD32(0x0000000f)
249 @@ -1555,6 +1699,10 @@
250  #define TX_PWR_CFG_7_MCS7_CH0          FIELD32(0x000f0000)
251  #define TX_PWR_CFG_7_MCS7_CH1          FIELD32(0x00f00000)
252  #define TX_PWR_CFG_7_MCS7_CH2          FIELD32(0x0f000000)
253 +/* bits for new 2T devices */
254 +#define TX_PWR_CFG_7B_54MBS            FIELD32(0x000000ff)
255 +#define TX_PWR_CFG_7B_MCS7             FIELD32(0x00ff0000)
256 +
257  
258  /* TX_PWR_CFG_8 */
259  #define TX_PWR_CFG_8                   0x13d8
260 @@ -1564,12 +1712,17 @@
261  #define TX_PWR_CFG_8_MCS23_CH0         FIELD32(0x000f0000)
262  #define TX_PWR_CFG_8_MCS23_CH1         FIELD32(0x00f00000)
263  #define TX_PWR_CFG_8_MCS23_CH2         FIELD32(0x0f000000)
264 +/* bits for new 2T devices */
265 +#define TX_PWR_CFG_8B_MCS15            FIELD32(0x000000ff)
266 +
267  
268  /* TX_PWR_CFG_9 */
269  #define TX_PWR_CFG_9                   0x13dc
270  #define TX_PWR_CFG_9_STBC7_CH0         FIELD32(0x0000000f)
271  #define TX_PWR_CFG_9_STBC7_CH1         FIELD32(0x000000f0)
272  #define TX_PWR_CFG_9_STBC7_CH2         FIELD32(0x00000f00)
273 +/* bits for new 2T devices */
274 +#define TX_PWR_CFG_9B_STBC_MCS7                FIELD32(0x000000ff)
275  
276  /*
277   * RX_FILTER_CFG: RX configuration register.
278 @@ -2137,11 +2290,14 @@ struct mac_iveiv_entry {
279  #define RFCSR1_TX1_PD                  FIELD8(0x20)
280  #define RFCSR1_RX2_PD                  FIELD8(0x40)
281  #define RFCSR1_TX2_PD                  FIELD8(0x80)
282 +#define RFCSR1_TX2_EN_MT7620           FIELD8(0x02)
283  
284  /*
285   * RFCSR 2:
286   */
287  #define RFCSR2_RESCAL_EN               FIELD8(0x80)
288 +#define RFCSR2_RX2_EN_MT7620           FIELD8(0x02)
289 +#define RFCSR2_TX2_EN_MT7620           FIELD8(0x20)
290  
291  /*
292   * RFCSR 3:
293 @@ -2160,6 +2316,12 @@ struct mac_iveiv_entry {
294  #define RFCSR3_BIT5                    FIELD8(0x20)
295  
296  /*
297 + * RFCSR 4:
298 + * VCOCAL_EN used by MT7620
299 + */
300 +#define RFCSR4_VCOCAL_EN               FIELD8(0x80)
301 +
302 +/*
303   * FRCSR 5:
304   */
305  #define RFCSR5_R1                      FIELD8(0x0c)
306 @@ -2214,6 +2376,7 @@ struct mac_iveiv_entry {
307   */
308  #define RFCSR13_TX_POWER               FIELD8(0x1f)
309  #define RFCSR13_DR0                    FIELD8(0xe0)
310 +#define RFCSR13_RDIV_MT7620            FIELD8(0x03)
311  
312  /*
313   * RFCSR 15:
314 @@ -2224,6 +2387,8 @@ struct mac_iveiv_entry {
315   * RFCSR 16:
316   */
317  #define RFCSR16_TXMIXER_GAIN           FIELD8(0x07)
318 +#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
319 +#define RFCSR16_SDM_MODE_MT7620                FIELD8(0xE0)
320  
321  /*
322   * RFCSR 17:
323 @@ -2236,6 +2401,8 @@ struct mac_iveiv_entry {
324  /* RFCSR 18 */
325  #define RFCSR18_XO_TUNE_BYPASS         FIELD8(0x40)
326  
327 +/* RFCSR 19 */
328 +#define RFCSR19_K                      FIELD8(0x03)
329  
330  /*
331   * RFCSR 20:
332 @@ -2246,11 +2413,14 @@ struct mac_iveiv_entry {
333   * RFCSR 21:
334   */
335  #define RFCSR21_RX_LO2_EN              FIELD8(0x08)
336 +#define RFCSR21_BIT1                   FIELD8(0x01)
337 +#define RFCSR21_BIT8                   FIELD8(0x80)
338  
339  /*
340   * RFCSR 22:
341   */
342  #define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
343 +#define RFCSR22_FREQPLAN_D_MT7620      FIELD8(0x07)
344  
345  /*
346   * RFCSR 23:
347 @@ -2273,6 +2443,11 @@ struct mac_iveiv_entry {
348  #define RFCSR27_R4                     FIELD8(0x40)
349  
350  /*
351 + * RFCSR 28:
352 + */
353 +#define RFCSR28_CH11_HT40              FIELD8(0x04)
354 +
355 +/*
356   * RFCSR 29:
357   */
358  #define RFCSR29_ADC6_TEST              FIELD8(0x01)
359 @@ -2333,6 +2508,7 @@ struct mac_iveiv_entry {
360   */
361  #define RFCSR42_BIT1                   FIELD8(0x01)
362  #define RFCSR42_BIT4                   FIELD8(0x08)
363 +#define RFCSR42_TX2_EN_MT7620          FIELD8(0x40)
364  
365  /*
366   * RFCSR 49:
367 @@ -2435,6 +2611,7 @@ enum rt2800_eeprom_word {
368         EEPROM_TSSI_BOUND_BG5,
369         EEPROM_TXPOWER_A1,
370         EEPROM_TXPOWER_A2,
371 +       EEPROM_TXPOWER_INIT,
372         EEPROM_TSSI_BOUND_A1,
373         EEPROM_TSSI_BOUND_A2,
374         EEPROM_TSSI_BOUND_A3,
375 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
376 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
377 @@ -59,6 +59,9 @@
378         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
379  #define WAIT_FOR_RFCSR(__dev, __reg) \
380         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
381 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
382 +       rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
383 +                           (__reg))
384  #define WAIT_FOR_RF(__dev, __reg) \
385         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
386  #define WAIT_FOR_MCU(__dev, __reg) \
387 @@ -150,19 +153,56 @@ static void rt2800_rfcsr_write(struct rt
388          * Wait until the RFCSR becomes available, afterwards we
389          * can safely write the new data into the register.
390          */
391 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
392 -               reg = 0;
393 -               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
394 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
395 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
396 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
397 +       switch (rt2x00dev->chip.rt) {
398 +       case RT6352:
399 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
400 +                       reg = 0;
401 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
402 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
403 +                                          word);
404 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
405 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
406 +
407 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
408 +               }
409 +               break;
410 +
411 +       default:
412 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
413 +                       reg = 0;
414 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
415 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
416 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
417 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
418  
419 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
420 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
421 +               }
422 +               break;
423         }
424  
425         mutex_unlock(&rt2x00dev->csr_mutex);
426  }
427  
428 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
429 +                                   const unsigned int reg, const u8 value)
430 +{
431 +       rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
432 +}
433 +
434 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
435 +                                      const unsigned int reg, const u8 value)
436 +{
437 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
438 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
439 +}
440 +
441 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
442 +                                    const unsigned int reg, const u8 value)
443 +{
444 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
445 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
446 +}
447 +
448  static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
449                               const unsigned int word, u8 *value)
450  {
451 @@ -178,22 +218,48 @@ static void rt2800_rfcsr_read(struct rt2
452          * doesn't become available in time, reg will be 0xffffffff
453          * which means we return 0xff to the caller.
454          */
455 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
456 -               reg = 0;
457 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
458 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
459 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
460 +       switch (rt2x00dev->chip.rt) {
461 +       case RT6352:
462 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
463 +                       reg = 0;
464 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
465 +                                          word);
466 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
467 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
468  
469 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
470 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
471  
472 -               WAIT_FOR_RFCSR(rt2x00dev, &reg);
473 -       }
474 +                       WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
475 +               }
476 +
477 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
478 +               break;
479  
480 -       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
481 +       default:
482 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
483 +                       reg = 0;
484 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
485 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
486 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
487 +
488 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
489 +
490 +                       WAIT_FOR_RFCSR(rt2x00dev, &reg);
491 +               }
492 +
493 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
494 +               break;
495 +       }
496  
497         mutex_unlock(&rt2x00dev->csr_mutex);
498  }
499  
500 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
501 +                                  const unsigned int reg, u8 *value)
502 +{
503 +       rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
504 +}
505 +
506  static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
507                             const unsigned int word, const u32 value)
508  {
509 @@ -250,6 +316,7 @@ static const unsigned int rt2800_eeprom_
510         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
511         [EEPROM_TXPOWER_A1]             = 0x003c,
512         [EEPROM_TXPOWER_A2]             = 0x0053,
513 +       [EEPROM_TXPOWER_INIT]           = 0x0068,
514         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
515         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
516         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
517 @@ -524,6 +591,7 @@ void rt2800_get_txwi_rxwi_size(struct rt
518                 break;
519  
520         case RT5592:
521 +       case RT6352:
522                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
523                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
524                 break;
525 @@ -2810,7 +2878,8 @@ static void rt2800_config_channel_rf53xx
526                                 rt2800_rfcsr_write(rt2x00dev, 59,
527                                                    r59_nonbt_rev[idx]);
528                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
529 -                                  rt2x00_rt(rt2x00dev, RT5392)) {
530 +                                  rt2x00_rt(rt2x00dev, RT5392) ||
531 +                                  rt2x00_rt(rt2x00dev, RT6352)) {
532                                 static const char r59_non_bt[] = {0x8f, 0x8f,
533                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
534                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
535 @@ -3104,6 +3173,242 @@ static void rt2800_config_channel_rf55xx
536         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
537  }
538  
539 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
540 +                                        struct ieee80211_conf *conf,
541 +                                        struct rf_channel *rf,
542 +                                        struct channel_info *info)
543 +{
544 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
545 +       u8 rx_agc_fc, tx_agc_fc;
546 +       u8 rfcsr;
547 +
548 +       /* Frequeny plan setting */
549 +       /* Rdiv setting (set 0x03 if Xtal==20)
550 +        * R13[1:0]
551 +        */
552 +       rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
553 +       rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
554 +                         rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
555 +       rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
556 +
557 +       /* N setting
558 +        * R20[7:0] in rf->rf1
559 +        * R21[0] always 0
560 +        */
561 +       rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
562 +       rfcsr = (rf->rf1 & 0x00ff);
563 +       rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
564 +
565 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
566 +       rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
567 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
568 +
569 +       /* K setting (always 0)
570 +        * R16[3:0] (RF PLL freq selection)
571 +        */
572 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
573 +       rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
574 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
575 +
576 +       /* D setting (always 0)
577 +        * R22[2:0] (D=15, R22[2:0]=<111>)
578 +        */
579 +       rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
580 +       rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
581 +       rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
582 +
583 +       /* Ksd setting
584 +        * Ksd: R17<7:0> in rf->rf2
585 +        *      R18<7:0> in rf->rf3
586 +        *      R19<1:0> in rf->rf4
587 +        */
588 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
589 +       rfcsr = rf->rf2;
590 +       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
591 +
592 +       rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
593 +       rfcsr = rf->rf3;
594 +       rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
595 +
596 +       rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
597 +       rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
598 +       rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
599 +
600 +       /* Default: XO=20MHz , SDM mode */
601 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
602 +       rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
603 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
604 +
605 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
606 +       rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
607 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
608 +
609 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
610 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
611 +                         rt2x00dev->default_ant.tx_chain_num != 1);
612 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
613 +
614 +       rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
615 +       rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
616 +                         rt2x00dev->default_ant.tx_chain_num != 1);
617 +       rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
618 +                         rt2x00dev->default_ant.rx_chain_num != 1);
619 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
620 +
621 +       rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
622 +       rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
623 +                         rt2x00dev->default_ant.tx_chain_num != 1);
624 +       rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
625 +
626 +       /* RF for DC Cal BW */
627 +       if (conf_is_ht40(conf)) {
628 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
629 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
630 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
631 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
632 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
633 +       } else {
634 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
635 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
636 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
637 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
638 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
639 +       }
640 +
641 +       if (conf_is_ht40(conf)) {
642 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
643 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
644 +       } else {
645 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
646 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
647 +       }
648 +
649 +       rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
650 +       rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
651 +                         conf_is_ht40(conf) && (rf->channel == 11));
652 +       rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
653 +
654 +       if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
655 +               if (conf_is_ht40(conf)) {
656 +                       rx_agc_fc = drv_data->rx_calibration_bw40;
657 +                       tx_agc_fc = drv_data->tx_calibration_bw40;
658 +               } else {
659 +                       rx_agc_fc = drv_data->rx_calibration_bw20;
660 +                       tx_agc_fc = drv_data->tx_calibration_bw20;
661 +               }
662 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
663 +               rfcsr &= (~0x3F);
664 +               rfcsr |= rx_agc_fc;
665 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
666 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
667 +               rfcsr &= (~0x3F);
668 +               rfcsr |= rx_agc_fc;
669 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
670 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
671 +               rfcsr &= (~0x3F);
672 +               rfcsr |= rx_agc_fc;
673 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
674 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
675 +               rfcsr &= (~0x3F);
676 +               rfcsr |= rx_agc_fc;
677 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
678 +
679 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
680 +               rfcsr &= (~0x3F);
681 +               rfcsr |= tx_agc_fc;
682 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
683 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
684 +               rfcsr &= (~0x3F);
685 +               rfcsr |= tx_agc_fc;
686 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
687 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
688 +               rfcsr &= (~0x3F);
689 +               rfcsr |= tx_agc_fc;
690 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
691 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
692 +               rfcsr &= (~0x3F);
693 +               rfcsr |= tx_agc_fc;
694 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
695 +       }
696 +}
697 +
698 +static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
699 +                             struct ieee80211_channel *chan,
700 +                             int power_level) {
701 +       u16 eeprom, target_power, max_power;
702 +       u32 mac_sys_ctrl, mac_status;
703 +       u32 reg;
704 +       u8 bbp;
705 +       int i;
706 +
707 +       /* hardware unit is 0.5dBm, limited to 23.5dBm */
708 +       power_level *= 2;
709 +       if (power_level > 0x2f)
710 +               power_level = 0x2f;
711 +
712 +       max_power = chan->max_power * 2;
713 +       if (max_power > 0x2f)
714 +               max_power = 0x2f;
715 +
716 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
717 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
718 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
719 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
720 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
721 +
722 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
723 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
724 +               /* init base power by eeprom target power */
725 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
726 +                                  &target_power);
727 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
728 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
729 +       }
730 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
731 +
732 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
733 +       rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
734 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
735 +
736 +       /* Save MAC SYS CTRL registers */
737 +       rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
738 +       /* Disable Tx/Rx */
739 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
740 +       /* Check MAC Tx/Rx idle */
741 +       for (i = 0; i < 10000; i++) {
742 +               rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
743 +                                    &mac_status);
744 +               if (mac_status & 0x3)
745 +                       usleep_range(50, 200);
746 +               else
747 +                       break;
748 +       }
749 +
750 +       if (i == 10000)
751 +               rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
752 +
753 +       if (chan->center_freq > 2457) {
754 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
755 +               bbp = 0x40;
756 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
757 +               rt2800_rfcsr_write(rt2x00dev, 39, 0);
758 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
759 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
760 +               else
761 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
762 +       } else {
763 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
764 +               bbp = 0x1f;
765 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
766 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
767 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
768 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
769 +               else
770 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
771 +       }
772 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
773 +}
774 +
775  static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
776                                            const unsigned int word,
777                                            const u8 value)
778 @@ -3228,7 +3533,7 @@ static void rt2800_config_channel(struct
779                                   struct channel_info *info)
780  {
781         u32 reg;
782 -       unsigned int tx_pin;
783 +       u32 tx_pin;
784         u8 bbp, rfcsr;
785  
786         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
787 @@ -3273,6 +3578,9 @@ static void rt2800_config_channel(struct
788         case RF5592:
789                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
790                 break;
791 +       case RF7620:
792 +               rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
793 +               break;
794         default:
795                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
796         }
797 @@ -3347,7 +3655,8 @@ static void rt2800_config_channel(struct
798  
799         if (rf->channel <= 14) {
800                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
801 -                   !rt2x00_rt(rt2x00dev, RT5392)) {
802 +                   !rt2x00_rt(rt2x00dev, RT5392) &&
803 +                   !rt2x00_rt(rt2x00dev, RT6352)) {
804                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
805                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
806                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
807 @@ -3367,7 +3676,7 @@ static void rt2800_config_channel(struct
808                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
809                 else if (rt2x00_rt(rt2x00dev, RT3593))
810                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
811 -               else
812 +               else if (!rt2x00_rt(rt2x00dev, RT6352))
813                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
814  
815                 if (rt2x00_rt(rt2x00dev, RT3593))
816 @@ -3388,7 +3697,7 @@ static void rt2800_config_channel(struct
817         if (rt2x00_rt(rt2x00dev, RT3572))
818                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
819  
820 -       tx_pin = 0;
821 +       rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
822  
823         switch (rt2x00dev->default_ant.tx_chain_num) {
824         case 3:
825 @@ -3437,6 +3746,7 @@ static void rt2800_config_channel(struct
826  
827         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
828         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
829 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
830  
831         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
832  
833 @@ -3495,7 +3805,7 @@ static void rt2800_config_channel(struct
834                 usleep_range(1000, 1500);
835         }
836  
837 -       if (rt2x00_rt(rt2x00dev, RT5592)) {
838 +       if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
839                 rt2800_bbp_write(rt2x00dev, 195, 141);
840                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
841  
842 @@ -4182,6 +4492,128 @@ static void rt2800_config_txpower_rt3593
843                            (unsigned long) regs[i]);
844  }
845  
846 +static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
847 +                                        struct ieee80211_channel *chan,
848 +                                        int power_level)
849 +{
850 +       u32 reg, pwreg;
851 +       u16 eeprom;
852 +       u32 data, gdata;
853 +       u8 t, i;
854 +       enum nl80211_band band = chan->band;
855 +       int delta;
856 +
857 +       /* Warn user if bw_comp is set in EEPROM */
858 +       delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
859 +
860 +       if (delta)
861 +               rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
862 +                           delta);
863 +
864 +       /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
865 +        * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
866 +        * driver does as well, though it looks kinda wrong.
867 +        * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
868 +        * the hardware has a problem handling 0x20, and as the code initially
869 +        * used a fixed offset between HT20 and HT40 rates they had to work-
870 +        * around that issue and most likely just forgot about it later on.
871 +        * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
872 +        * however, the corresponding EEPROM value is not respected by the
873 +        * vendor driver, so maybe this is rather being taken care of the
874 +        * TXALC and the driver doesn't need to handle it...?
875 +        * Though this is all very awkward, just do as they did, as that's what
876 +        * board vendors expected when they populated the EEPROM...
877 +        */
878 +       for (i = 0; i < 5; i++) {
879 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
880 +                                             i * 2, &eeprom);
881 +
882 +               data = eeprom;
883 +
884 +               t = eeprom & 0x3f;
885 +               if (t == 32)
886 +                       t++;
887 +
888 +               gdata = t;
889 +
890 +               t = (eeprom & 0x3f00) >> 8;
891 +               if (t == 32)
892 +                       t++;
893 +
894 +               gdata |= (t << 8);
895 +
896 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
897 +                                             (i * 2) + 1, &eeprom);
898 +
899 +               t = eeprom & 0x3f;
900 +               if (t == 32)
901 +                       t++;
902 +
903 +               gdata |= (t << 16);
904 +
905 +               t = (eeprom & 0x3f00) >> 8;
906 +               if (t == 32)
907 +                       t++;
908 +
909 +               gdata |= (t << 24);
910 +               data |= (eeprom << 16);
911 +
912 +               if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
913 +                       /* HT20 */
914 +                       if (data != 0xffffffff)
915 +                               rt2800_register_write(rt2x00dev,
916 +                                                     TX_PWR_CFG_0 + (i * 4),
917 +                                                     data);
918 +               } else {
919 +                       /* HT40 */
920 +                       if (gdata != 0xffffffff)
921 +                               rt2800_register_write(rt2x00dev,
922 +                                                     TX_PWR_CFG_0 + (i * 4),
923 +                                                     gdata);
924 +               }
925 +       }
926 +
927 +       /* Aparently Ralink ran out of space in the BYRATE calibration section
928 +        * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
929 +        * registers. As recent 2T chips use 8-bit instead of 4-bit values for
930 +        * power-offsets more space would be needed. Ralink decided to keep the
931 +        * EEPROM layout untouched and rather have some shared values covering
932 +        * multiple bitrates.
933 +        * Populate the registers not covered by the EEPROM in the same way the
934 +        * vendor driver does.
935 +        */
936 +
937 +       /* For OFDM 54MBS use value from OFDM 48MBS */
938 +       pwreg = 0;
939 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
940 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
941 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
942 +
943 +       /* For MCS 7 use value from MCS 6 */
944 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
945 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
946 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
947 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
948 +
949 +       /* For MCS 15 use value from MCS 14 */
950 +       pwreg = 0;
951 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
952 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
953 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
954 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
955 +
956 +       /* For STBC MCS 7 use value from STBC MCS 6 */
957 +       pwreg = 0;
958 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
959 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
960 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
961 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
962 +
963 +       rt2800_config_alc(rt2x00dev, chan, power_level);
964 +
965 +       /* TODO: temperature compensation code! */
966 +}
967 +
968  /*
969   * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
970   * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
971 @@ -4378,6 +4810,8 @@ static void rt2800_config_txpower(struct
972  {
973         if (rt2x00_rt(rt2x00dev, RT3593))
974                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
975 +       else if (rt2x00_rt(rt2x00dev, RT6352))
976 +               rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
977         else
978                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
979  }
980 @@ -4393,6 +4827,7 @@ void rt2800_vco_calibration(struct rt2x0
981  {
982         u32     tx_pin;
983         u8      rfcsr;
984 +       unsigned long min_sleep = 0;
985  
986         /*
987          * A voltage-controlled oscillator(VCO) is an electronic oscillator
988 @@ -4431,6 +4866,15 @@ void rt2800_vco_calibration(struct rt2x0
989                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
990                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
991                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
992 +               min_sleep = 1000;
993 +               break;
994 +       case RF7620:
995 +               rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
996 +               rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
997 +               rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
998 +               rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
999 +               rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
1000 +               min_sleep = 2000;
1001                 break;
1002         default:
1003                 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
1004 @@ -4438,7 +4882,8 @@ void rt2800_vco_calibration(struct rt2x0
1005                 return;
1006         }
1007  
1008 -       usleep_range(1000, 1500);
1009 +       if (min_sleep > 0)
1010 +               usleep_range(min_sleep, min_sleep * 2);
1011  
1012         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
1013         if (rt2x00dev->rf_channel <= 14) {
1014 @@ -4470,6 +4915,42 @@ void rt2800_vco_calibration(struct rt2x0
1015         }
1016         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1017  
1018 +       if (rt2x00_rt(rt2x00dev, RT6352)) {
1019 +               if (rt2x00dev->default_ant.tx_chain_num == 1) {
1020 +                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
1021 +                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
1022 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
1023 +                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
1024 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
1025 +                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
1026 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
1027 +                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
1028 +               } else {
1029 +                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
1030 +                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
1031 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
1032 +                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
1033 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
1034 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
1035 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
1036 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
1037 +               }
1038 +
1039 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
1040 +                       rt2800_bbp_write(rt2x00dev, 75, 0x60);
1041 +                       rt2800_bbp_write(rt2x00dev, 76, 0x44);
1042 +                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
1043 +                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
1044 +                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
1045 +               }
1046 +
1047 +               /* On 11A, We should delay and wait RF/BBP to be stable
1048 +                * and the appropriate time should be 1000 micro seconds
1049 +                * 2005/06/05 - On 11G, we also need this delay time.
1050 +                * Otherwise it's difficult to pass the WHQL.
1051 +                */
1052 +               usleep_range(1000, 1500);
1053 +       }
1054  }
1055  EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
1056  
1057 @@ -4568,7 +5049,8 @@ static u8 rt2800_get_default_vgc(struct
1058                     rt2x00_rt(rt2x00dev, RT3593) ||
1059                     rt2x00_rt(rt2x00dev, RT5390) ||
1060                     rt2x00_rt(rt2x00dev, RT5392) ||
1061 -                   rt2x00_rt(rt2x00dev, RT5592))
1062 +                   rt2x00_rt(rt2x00dev, RT5592) ||
1063 +                   rt2x00_rt(rt2x00dev, RT6352))
1064                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
1065                 else
1066                         vgc = 0x2e + rt2x00dev->lna_gain;
1067 @@ -4795,7 +5277,8 @@ static int rt2800_init_registers(struct
1068                                               0x00000000);
1069                 }
1070         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
1071 -                  rt2x00_rt(rt2x00dev, RT5392)) {
1072 +                  rt2x00_rt(rt2x00dev, RT5392) ||
1073 +                  rt2x00_rt(rt2x00dev, RT6352)) {
1074                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
1075                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1076                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1077 @@ -4805,6 +5288,24 @@ static int rt2800_init_registers(struct
1078                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1079         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
1080                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
1081 +       } else if (rt2x00_rt(rt2x00dev, RT6352)) {
1082 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
1083 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
1084 +               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1085 +               rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
1086 +               rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
1087 +               rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
1088 +               rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
1089 +               rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
1090 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
1091 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
1092 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
1093 +                                     0x3630363A);
1094 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
1095 +                                     0x3630363A);
1096 +               rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
1097 +               rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
1098 +               rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
1099         } else {
1100                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1101                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1102 @@ -5786,6 +6287,231 @@ static void rt2800_init_bbp_5592(struct
1103                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1104  }
1105  
1106 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
1107 +                                 const u8 reg, const u8 value)
1108 +{
1109 +       rt2800_bbp_write(rt2x00dev, 195, reg);
1110 +       rt2800_bbp_write(rt2x00dev, 196, value);
1111 +}
1112 +
1113 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
1114 +                                 const u8 reg, const u8 value)
1115 +{
1116 +       rt2800_bbp_write(rt2x00dev, 158, reg);
1117 +       rt2800_bbp_write(rt2x00dev, 159, value);
1118 +}
1119 +
1120 +static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev,
1121 +                                const u8 reg, u8 *value)
1122 +{
1123 +       rt2800_bbp_write(rt2x00dev, 158, reg);
1124 +       rt2800_bbp_read(rt2x00dev, 159, value);
1125 +}
1126 +
1127 +static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
1128 +{
1129 +       u8 bbp;
1130 +
1131 +       /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
1132 +       rt2800_bbp_read(rt2x00dev, 105, &bbp);
1133 +       rt2x00_set_field8(&bbp, BBP105_MLD,
1134 +                         rt2x00dev->default_ant.rx_chain_num == 2);
1135 +       rt2800_bbp_write(rt2x00dev, 105, bbp);
1136 +
1137 +       /* Avoid data loss and CRC errors */
1138 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1139 +
1140 +       /* Fix I/Q swap issue */
1141 +       rt2800_bbp_read(rt2x00dev, 1, &bbp);
1142 +       bbp |= 0x04;
1143 +       rt2800_bbp_write(rt2x00dev, 1, bbp);
1144 +
1145 +       /* BBP for G band */
1146 +       rt2800_bbp_write(rt2x00dev, 3, 0x08);
1147 +       rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
1148 +       rt2800_bbp_write(rt2x00dev, 6, 0x08);
1149 +       rt2800_bbp_write(rt2x00dev, 14, 0x09);
1150 +       rt2800_bbp_write(rt2x00dev, 15, 0xFF);
1151 +       rt2800_bbp_write(rt2x00dev, 16, 0x01);
1152 +       rt2800_bbp_write(rt2x00dev, 20, 0x06);
1153 +       rt2800_bbp_write(rt2x00dev, 21, 0x00);
1154 +       rt2800_bbp_write(rt2x00dev, 22, 0x00);
1155 +       rt2800_bbp_write(rt2x00dev, 27, 0x00);
1156 +       rt2800_bbp_write(rt2x00dev, 28, 0x00);
1157 +       rt2800_bbp_write(rt2x00dev, 30, 0x00);
1158 +       rt2800_bbp_write(rt2x00dev, 31, 0x48);
1159 +       rt2800_bbp_write(rt2x00dev, 47, 0x40);
1160 +       rt2800_bbp_write(rt2x00dev, 62, 0x00);
1161 +       rt2800_bbp_write(rt2x00dev, 63, 0x00);
1162 +       rt2800_bbp_write(rt2x00dev, 64, 0x00);
1163 +       rt2800_bbp_write(rt2x00dev, 65, 0x2C);
1164 +       rt2800_bbp_write(rt2x00dev, 66, 0x1C);
1165 +       rt2800_bbp_write(rt2x00dev, 67, 0x20);
1166 +       rt2800_bbp_write(rt2x00dev, 68, 0xDD);
1167 +       rt2800_bbp_write(rt2x00dev, 69, 0x10);
1168 +       rt2800_bbp_write(rt2x00dev, 70, 0x05);
1169 +       rt2800_bbp_write(rt2x00dev, 73, 0x18);
1170 +       rt2800_bbp_write(rt2x00dev, 74, 0x0F);
1171 +       rt2800_bbp_write(rt2x00dev, 75, 0x60);
1172 +       rt2800_bbp_write(rt2x00dev, 76, 0x44);
1173 +       rt2800_bbp_write(rt2x00dev, 77, 0x59);
1174 +       rt2800_bbp_write(rt2x00dev, 78, 0x1E);
1175 +       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
1176 +       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
1177 +       rt2800_bbp_write(rt2x00dev, 81, 0x3A);
1178 +       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
1179 +       rt2800_bbp_write(rt2x00dev, 83, 0x9A);
1180 +       rt2800_bbp_write(rt2x00dev, 84, 0x9A);
1181 +       rt2800_bbp_write(rt2x00dev, 86, 0x38);
1182 +       rt2800_bbp_write(rt2x00dev, 88, 0x90);
1183 +       rt2800_bbp_write(rt2x00dev, 91, 0x04);
1184 +       rt2800_bbp_write(rt2x00dev, 92, 0x02);
1185 +       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
1186 +       rt2800_bbp_write(rt2x00dev, 96, 0x00);
1187 +       rt2800_bbp_write(rt2x00dev, 103, 0xC0);
1188 +       rt2800_bbp_write(rt2x00dev, 104, 0x92);
1189 +       /* FIXME BBP105 owerwrite */
1190 +       rt2800_bbp_write(rt2x00dev, 105, 0x3C);
1191 +       rt2800_bbp_write(rt2x00dev, 106, 0x12);
1192 +       rt2800_bbp_write(rt2x00dev, 109, 0x00);
1193 +       rt2800_bbp_write(rt2x00dev, 134, 0x10);
1194 +       rt2800_bbp_write(rt2x00dev, 135, 0xA6);
1195 +       rt2800_bbp_write(rt2x00dev, 137, 0x04);
1196 +       rt2800_bbp_write(rt2x00dev, 142, 0x30);
1197 +       rt2800_bbp_write(rt2x00dev, 143, 0xF7);
1198 +       rt2800_bbp_write(rt2x00dev, 160, 0xEC);
1199 +       rt2800_bbp_write(rt2x00dev, 161, 0xC4);
1200 +       rt2800_bbp_write(rt2x00dev, 162, 0x77);
1201 +       rt2800_bbp_write(rt2x00dev, 163, 0xF9);
1202 +       rt2800_bbp_write(rt2x00dev, 164, 0x00);
1203 +       rt2800_bbp_write(rt2x00dev, 165, 0x00);
1204 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1205 +       rt2800_bbp_write(rt2x00dev, 187, 0x00);
1206 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1207 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1208 +       rt2800_bbp_write(rt2x00dev, 187, 0x01);
1209 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1210 +       rt2800_bbp_write(rt2x00dev, 189, 0x00);
1211 +
1212 +       rt2800_bbp_write(rt2x00dev, 91, 0x06);
1213 +       rt2800_bbp_write(rt2x00dev, 92, 0x04);
1214 +       rt2800_bbp_write(rt2x00dev, 93, 0x54);
1215 +       rt2800_bbp_write(rt2x00dev, 99, 0x50);
1216 +       rt2800_bbp_write(rt2x00dev, 148, 0x84);
1217 +       rt2800_bbp_write(rt2x00dev, 167, 0x80);
1218 +       rt2800_bbp_write(rt2x00dev, 178, 0xFF);
1219 +       rt2800_bbp_write(rt2x00dev, 106, 0x13);
1220 +
1221 +       /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
1222 +       rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
1223 +       rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
1224 +       rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
1225 +       rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
1226 +       rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
1227 +       rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
1228 +       rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
1229 +       rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
1230 +       rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
1231 +       rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
1232 +       rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
1233 +       rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
1234 +       rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
1235 +       rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
1236 +       rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
1237 +       rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
1238 +       rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
1239 +       rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
1240 +       rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
1241 +       rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
1242 +       rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
1243 +       rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
1244 +       rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
1245 +       rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
1246 +       rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
1247 +       rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
1248 +       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
1249 +       rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
1250 +       rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
1251 +       rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
1252 +       rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
1253 +       rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
1254 +       rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
1255 +       rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
1256 +       rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
1257 +       rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
1258 +       rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
1259 +       rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
1260 +       rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
1261 +       rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
1262 +       rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
1263 +       rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
1264 +       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
1265 +       rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
1266 +       rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
1267 +       rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
1268 +       rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
1269 +       rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
1270 +       rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
1271 +       rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
1272 +       rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
1273 +       rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
1274 +       rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
1275 +       rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
1276 +       rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
1277 +       rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
1278 +       rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
1279 +       rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
1280 +       rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
1281 +       rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
1282 +       rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
1283 +       rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
1284 +       rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
1285 +       rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
1286 +       rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
1287 +       rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
1288 +       rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
1289 +       rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
1290 +       rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
1291 +       rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
1292 +       rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
1293 +       rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
1294 +       rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
1295 +       rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
1296 +       rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
1297 +       rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
1298 +       rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
1299 +       rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
1300 +       rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
1301 +       rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
1302 +       rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
1303 +       rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
1304 +       rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
1305 +
1306 +       /* BBP for G band DCOC function */
1307 +       rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
1308 +       rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
1309 +       rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
1310 +       rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
1311 +       rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
1312 +       rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
1313 +       rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
1314 +       rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
1315 +       rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
1316 +       rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
1317 +       rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
1318 +       rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
1319 +       rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
1320 +       rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
1321 +       rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
1322 +       rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
1323 +       rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
1324 +       rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
1325 +       rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
1326 +       rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
1327 +
1328 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1329 +}
1330 +
1331  static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1332  {
1333         unsigned int i;
1334 @@ -5830,6 +6556,9 @@ static void rt2800_init_bbp(struct rt2x0
1335         case RT5592:
1336                 rt2800_init_bbp_5592(rt2x00dev);
1337                 return;
1338 +       case RT6352:
1339 +               rt2800_init_bbp_6352(rt2x00dev);
1340 +               break;
1341         }
1342  
1343         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1344 @@ -6901,6 +7630,615 @@ static void rt2800_init_rfcsr_5592(struc
1345         rt2800_led_open_drain_enable(rt2x00dev);
1346  }
1347  
1348 +static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
1349 +                                      bool set_bw, bool is_ht40)
1350 +{
1351 +       u8 bbp_val;
1352 +
1353 +       rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
1354 +       bbp_val |= 0x1;
1355 +       rt2800_bbp_write(rt2x00dev, 21, bbp_val);
1356 +       usleep_range(100, 200);
1357 +
1358 +       if (set_bw) {
1359 +               rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
1360 +               rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
1361 +               rt2800_bbp_write(rt2x00dev, 4, bbp_val);
1362 +               usleep_range(100, 200);
1363 +       }
1364 +
1365 +       rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
1366 +       bbp_val &= (~0x1);
1367 +       rt2800_bbp_write(rt2x00dev, 21, bbp_val);
1368 +       usleep_range(100, 200);
1369 +}
1370 +
1371 +static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
1372 +{
1373 +       u8 rf_val;
1374 +
1375 +       if (btxcal)
1376 +               rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
1377 +       else
1378 +               rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
1379 +
1380 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
1381 +
1382 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &rf_val);
1383 +       rf_val |= 0x80;
1384 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
1385 +
1386 +       if (btxcal) {
1387 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
1388 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
1389 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
1390 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
1391 +               rf_val &= (~0x3F);
1392 +               rf_val |= 0x3F;
1393 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
1394 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
1395 +               rf_val &= (~0x3F);
1396 +               rf_val |= 0x3F;
1397 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
1398 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
1399 +       } else {
1400 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
1401 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
1402 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
1403 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
1404 +               rf_val &= (~0x3F);
1405 +               rf_val |= 0x34;
1406 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
1407 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
1408 +               rf_val &= (~0x3F);
1409 +               rf_val |= 0x34;
1410 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
1411 +       }
1412 +
1413 +       return 0;
1414 +}
1415 +
1416 +static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
1417 +{
1418 +       unsigned int cnt;
1419 +       u8 bbp_val;
1420 +       char cal_val;
1421 +
1422 +       rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
1423 +
1424 +       cnt = 0;
1425 +       do {
1426 +               usleep_range(500, 2000);
1427 +               rt2800_bbp_read(rt2x00dev, 159, &bbp_val);
1428 +               if (bbp_val == 0x02 || cnt == 20)
1429 +                       break;
1430 +
1431 +               cnt++;
1432 +       } while (cnt < 20);
1433 +
1434 +       rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val);
1435 +       cal_val = bbp_val & 0x7F;
1436 +       if (cal_val >= 0x40)
1437 +               cal_val -= 128;
1438 +
1439 +       return cal_val;
1440 +}
1441 +
1442 +static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
1443 +                                        bool btxcal)
1444 +{
1445 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1446 +       u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
1447 +       u8 filter_target;
1448 +       u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
1449 +       u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
1450 +       int loop = 0, is_ht40, cnt;
1451 +       u8 bbp_val, rf_val;
1452 +       char cal_r32_init, cal_r32_val, cal_diff;
1453 +       u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
1454 +       u8 saverfb5r06, saverfb5r07;
1455 +       u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
1456 +       u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
1457 +       u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
1458 +       u8 saverfb5r58, saverfb5r59;
1459 +       u8 savebbp159r0, savebbp159r2, savebbpr23;
1460 +       u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
1461 +
1462 +       /* Save MAC registers */
1463 +       rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0);
1464 +       rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0);
1465 +
1466 +       /* save BBP registers */
1467 +       rt2800_bbp_read(rt2x00dev, 23, &savebbpr23);
1468 +
1469 +       rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0);
1470 +       rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2);
1471 +
1472 +       /* Save RF registers */
1473 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &saverfb5r00);
1474 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &saverfb5r01);
1475 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &saverfb5r03);
1476 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &saverfb5r04);
1477 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 5, &saverfb5r05);
1478 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &saverfb5r06);
1479 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &saverfb5r07);
1480 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &saverfb5r08);
1481 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &saverfb5r17);
1482 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 18, &saverfb5r18);
1483 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 19, &saverfb5r19);
1484 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 20, &saverfb5r20);
1485 +
1486 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 37, &saverfb5r37);
1487 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 38, &saverfb5r38);
1488 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 39, &saverfb5r39);
1489 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 40, &saverfb5r40);
1490 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 41, &saverfb5r41);
1491 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 42, &saverfb5r42);
1492 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 43, &saverfb5r43);
1493 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 44, &saverfb5r44);
1494 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 45, &saverfb5r45);
1495 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 46, &saverfb5r46);
1496 +
1497 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &saverfb5r58);
1498 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &saverfb5r59);
1499 +
1500 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
1501 +       rf_val |= 0x3;
1502 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
1503 +
1504 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
1505 +       rf_val |= 0x1;
1506 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
1507 +
1508 +       cnt = 0;
1509 +       do {
1510 +               usleep_range(500, 2000);
1511 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
1512 +               if (((rf_val & 0x1) == 0x00) || (cnt == 40))
1513 +                       break;
1514 +               cnt++;
1515 +       } while (cnt < 40);
1516 +
1517 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
1518 +       rf_val &= (~0x3);
1519 +       rf_val |= 0x1;
1520 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
1521 +
1522 +       /* I-3 */
1523 +       rt2800_bbp_read(rt2x00dev, 23, &bbp_val);
1524 +       bbp_val &= (~0x1F);
1525 +       bbp_val |= 0x10;
1526 +       rt2800_bbp_write(rt2x00dev, 23, bbp_val);
1527 +
1528 +       do {
1529 +               /* I-4,5,6,7,8,9 */
1530 +               if (loop == 0) {
1531 +                       is_ht40 = false;
1532 +
1533 +                       if (btxcal)
1534 +                               filter_target = tx_filter_target_20m;
1535 +                       else
1536 +                               filter_target = rx_filter_target_20m;
1537 +               } else {
1538 +                       is_ht40 = true;
1539 +
1540 +                       if (btxcal)
1541 +                               filter_target = tx_filter_target_40m;
1542 +                       else
1543 +                               filter_target = rx_filter_target_40m;
1544 +               }
1545 +
1546 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &rf_val);
1547 +               rf_val &= (~0x04);
1548 +               if (loop == 1)
1549 +                       rf_val |= 0x4;
1550 +
1551 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
1552 +
1553 +               rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
1554 +
1555 +               rt2800_rf_lp_config(rt2x00dev, btxcal);
1556 +               if (btxcal) {
1557 +                       tx_agc_fc = 0;
1558 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
1559 +                       rf_val &= (~0x7F);
1560 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
1561 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
1562 +                       rf_val &= (~0x7F);
1563 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
1564 +               } else {
1565 +                       rx_agc_fc = 0;
1566 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
1567 +                       rf_val &= (~0x7F);
1568 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
1569 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
1570 +                       rf_val &= (~0x7F);
1571 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
1572 +               }
1573 +
1574 +               usleep_range(1000, 2000);
1575 +
1576 +               rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
1577 +               bbp_val &= (~0x6);
1578 +               rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
1579 +
1580 +               rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
1581 +
1582 +               cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
1583 +
1584 +               rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
1585 +               bbp_val |= 0x6;
1586 +               rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
1587 +do_cal:
1588 +               if (btxcal) {
1589 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
1590 +                       rf_val &= (~0x7F);
1591 +                       rf_val |= tx_agc_fc;
1592 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
1593 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
1594 +                       rf_val &= (~0x7F);
1595 +                       rf_val |= tx_agc_fc;
1596 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
1597 +               } else {
1598 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
1599 +                       rf_val &= (~0x7F);
1600 +                       rf_val |= rx_agc_fc;
1601 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
1602 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
1603 +                       rf_val &= (~0x7F);
1604 +                       rf_val |= rx_agc_fc;
1605 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
1606 +               }
1607 +
1608 +               usleep_range(500, 1000);
1609 +
1610 +               rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
1611 +
1612 +               cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
1613 +
1614 +               cal_diff = cal_r32_init - cal_r32_val;
1615 +
1616 +               if (btxcal)
1617 +                       cmm_agc_fc = tx_agc_fc;
1618 +               else
1619 +                       cmm_agc_fc = rx_agc_fc;
1620 +
1621 +               if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
1622 +                   ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
1623 +                       if (btxcal)
1624 +                               tx_agc_fc = 0;
1625 +                       else
1626 +                               rx_agc_fc = 0;
1627 +               } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
1628 +                       if (btxcal)
1629 +                               tx_agc_fc++;
1630 +                       else
1631 +                               rx_agc_fc++;
1632 +                       goto do_cal;
1633 +               }
1634 +
1635 +               if (btxcal) {
1636 +                       if (loop == 0)
1637 +                               drv_data->tx_calibration_bw20 = tx_agc_fc;
1638 +                       else
1639 +                               drv_data->tx_calibration_bw40 = tx_agc_fc;
1640 +               } else {
1641 +                       if (loop == 0)
1642 +                               drv_data->rx_calibration_bw20 = rx_agc_fc;
1643 +                       else
1644 +                               drv_data->rx_calibration_bw40 = rx_agc_fc;
1645 +               }
1646 +
1647 +               loop++;
1648 +       } while (loop <= 1);
1649 +
1650 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
1651 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
1652 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
1653 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
1654 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
1655 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
1656 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
1657 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
1658 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
1659 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
1660 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
1661 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
1662 +
1663 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
1664 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
1665 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
1666 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
1667 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
1668 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
1669 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
1670 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
1671 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
1672 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
1673 +
1674 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
1675 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
1676 +
1677 +       rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
1678 +
1679 +       rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
1680 +       rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
1681 +
1682 +       rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
1683 +       rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
1684 +                         2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
1685 +       rt2800_bbp_write(rt2x00dev, 4, bbp_val);
1686 +
1687 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
1688 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
1689 +}
1690 +
1691 +static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
1692 +{
1693 +       /* Initialize RF central register to default value */
1694 +       rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
1695 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
1696 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
1697 +       rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
1698 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
1699 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
1700 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
1701 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
1702 +       rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1703 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
1704 +       rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
1705 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1706 +       rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
1707 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1708 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
1709 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
1710 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
1711 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
1712 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
1713 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
1714 +       rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
1715 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
1716 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
1717 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
1718 +       rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
1719 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
1720 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
1721 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1722 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
1723 +       rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
1724 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1725 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1726 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
1727 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
1728 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
1729 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
1730 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
1731 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
1732 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
1733 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
1734 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
1735 +       rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
1736 +       rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
1737 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
1738 +
1739 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1740 +       if (rt2800_clk_is_20mhz(rt2x00dev))
1741 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
1742 +       else
1743 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1744 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
1745 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
1746 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
1747 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
1748 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
1749 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
1750 +       rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
1751 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1752 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
1753 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
1754 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
1755 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
1756 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1757 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
1758 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
1759 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
1760 +
1761 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
1762 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
1763 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
1764 +
1765 +       /* Initialize RF channel register to default value */
1766 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
1767 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
1768 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
1769 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
1770 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
1771 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
1772 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
1773 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
1774 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
1775 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
1776 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
1777 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1778 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
1779 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
1780 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1781 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
1782 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
1783 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
1784 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
1785 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1786 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
1787 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
1788 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
1789 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
1790 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
1791 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
1792 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
1793 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
1794 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
1795 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
1796 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
1797 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
1798 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
1799 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
1800 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
1801 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
1802 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
1803 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
1804 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
1805 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
1806 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
1807 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
1808 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
1809 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
1810 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
1811 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1812 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
1813 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
1814 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
1815 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
1816 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
1817 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
1818 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
1819 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
1820 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1821 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1822 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1823 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1824 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1825 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1826 +
1827 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1828 +
1829 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1830 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1831 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1832 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1833 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1834 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1835 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1836 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1837 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1838 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1839 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1840 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1841 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1842 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1843 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1844 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1845 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1846 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1847 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1848 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1849 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1850 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1851 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1852 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1853 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1854 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1855 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1856 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1857 +
1858 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1859 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1860 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1861 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1862 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1863 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1864 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1865 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1866 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1867 +
1868 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1869 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1870 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1871 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1872 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1873 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1874 +
1875 +       /* Initialize RF channel register for DRQFN */
1876 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1877 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1878 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1879 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1880 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1881 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1882 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1883 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1884 +
1885 +       /* Initialize RF DC calibration register to default value */
1886 +       rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1887 +       rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1888 +       rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1889 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1890 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1891 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1892 +       rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1893 +       rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1894 +       rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1895 +       rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1896 +       rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1897 +       rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1898 +       rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1899 +       rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1900 +       rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1901 +       rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1902 +       rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1903 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1904 +       rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1905 +       rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1906 +       rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1907 +       rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1908 +       rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1909 +       rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1910 +       rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1911 +       rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1912 +       rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1913 +       rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1914 +       rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1915 +       rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1916 +       rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1917 +       rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1918 +       rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1919 +       rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1920 +       rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1921 +       rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1922 +       rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1923 +       rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1924 +       rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1925 +       rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1926 +       rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1927 +       rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1928 +       rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1929 +       rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1930 +       rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1931 +       rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1932 +       rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1933 +       rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1934 +       rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1935 +       rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1936 +       rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1937 +       rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1938 +       rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1939 +       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1940 +       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1941 +       rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1942 +       rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1943 +       rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1944 +       rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1945 +
1946 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1947 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1948 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1949 +
1950 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1951 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1952 +
1953 +       rt2800_bw_filter_calibration(rt2x00dev, true);
1954 +       rt2800_bw_filter_calibration(rt2x00dev, false);
1955 +}
1956 +
1957  static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1958  {
1959         if (rt2800_is_305x_soc(rt2x00dev)) {
1960 @@ -6941,6 +8279,9 @@ static void rt2800_init_rfcsr(struct rt2
1961         case RT5592:
1962                 rt2800_init_rfcsr_5592(rt2x00dev);
1963                 break;
1964 +       case RT6352:
1965 +               rt2800_init_rfcsr_6352(rt2x00dev);
1966 +               break;
1967         }
1968  }
1969  
1970 @@ -7307,7 +8648,8 @@ static int rt2800_init_eeprom(struct rt2
1971          */
1972         if (rt2x00_rt(rt2x00dev, RT3290) ||
1973             rt2x00_rt(rt2x00dev, RT5390) ||
1974 -           rt2x00_rt(rt2x00dev, RT5392))
1975 +           rt2x00_rt(rt2x00dev, RT5392) ||
1976 +           rt2x00_rt(rt2x00dev, RT6352))
1977                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
1978         else if (rt2x00_rt(rt2x00dev, RT3352))
1979                 rf = RF3322;
1980 @@ -7339,6 +8681,7 @@ static int rt2800_init_eeprom(struct rt2
1981         case RF5390:
1982         case RF5392:
1983         case RF5592:
1984 +       case RF7620:
1985                 break;
1986         default:
1987                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1988 @@ -7746,6 +9089,23 @@ static const struct rf_channel rf_vals_5
1989         {196, 83, 0, 12, 1},
1990  };
1991  
1992 +static const struct rf_channel rf_vals_7620[] = {
1993 +       {1, 0x50, 0x99, 0x99, 1},
1994 +       {2, 0x50, 0x44, 0x44, 2},
1995 +       {3, 0x50, 0xEE, 0xEE, 2},
1996 +       {4, 0x50, 0x99, 0x99, 3},
1997 +       {5, 0x51, 0x44, 0x44, 0},
1998 +       {6, 0x51, 0xEE, 0xEE, 0},
1999 +       {7, 0x51, 0x99, 0x99, 1},
2000 +       {8, 0x51, 0x44, 0x44, 2},
2001 +       {9, 0x51, 0xEE, 0xEE, 2},
2002 +       {10, 0x51, 0x99, 0x99, 3},
2003 +       {11, 0x52, 0x44, 0x44, 0},
2004 +       {12, 0x52, 0xEE, 0xEE, 0},
2005 +       {13, 0x52, 0x99, 0x99, 1},
2006 +       {14, 0x52, 0x33, 0x33, 3},
2007 +};
2008 +
2009  static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2010  {
2011         struct hw_mode_spec *spec = &rt2x00dev->spec;
2012 @@ -7849,6 +9209,11 @@ static int rt2800_probe_hw_mode(struct r
2013                         spec->channels = rf_vals_3x;
2014                 break;
2015  
2016 +       case RF7620:
2017 +               spec->num_channels = ARRAY_SIZE(rf_vals_7620);
2018 +               spec->channels = rf_vals_7620;
2019 +               break;
2020 +
2021         case RF3052:
2022         case RF3053:
2023                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2024 @@ -7980,6 +9345,7 @@ static int rt2800_probe_hw_mode(struct r
2025         case RF5390:
2026         case RF5392:
2027         case RF5592:
2028 +       case RF7620:
2029                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
2030                 break;
2031         }
2032 @@ -8024,6 +9390,9 @@ static int rt2800_probe_rt(struct rt2x00
2033                 return -ENODEV;
2034         }
2035  
2036 +       if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
2037 +               rt = RT6352;
2038 +
2039         rt2x00_set_rt(rt2x00dev, rt, rev);
2040  
2041         return 0;
2042 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
2043 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
2044 @@ -33,6 +33,10 @@
2045  struct rt2800_drv_data {
2046         u8 calibration_bw20;
2047         u8 calibration_bw40;
2048 +       char rx_calibration_bw20;
2049 +       char rx_calibration_bw40;
2050 +       char tx_calibration_bw20;
2051 +       char tx_calibration_bw40;
2052         u8 bbp25;
2053         u8 bbp26;
2054         u8 txmixer_gain_24g;
2055 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
2056 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
2057 @@ -174,6 +174,7 @@ struct rt2x00_chip {
2058  #define RT5390         0x5390  /* 2.4GHz */
2059  #define RT5392         0x5392  /* 2.4GHz */
2060  #define RT5592         0x5592
2061 +#define RT6352         0x6352  /* WSOC 2.4GHz */
2062  
2063         u16 rf;
2064         u16 rev;