package/kernel/mac80211/patches/020-19-rt2x00-add-support-for-MT7620.patch

   1 From 41977e86c984fcdddb454a3d7887de5d47b5f530 Mon Sep 17 00:00:00 2001
   2 From: Roman Yeryomin <roman@advem.lv>
   3 Date: Tue, 21 Mar 2017 00:43:00 +0100
   4 Subject: [PATCH 19/19] rt2x00: add support for MT7620
   5
   6 Basic support for MT7620 built-in wireless radio was added to
   7 OpenWrt in r41441. It has seen some heavy cleaning and refactoring
   8 since in order to match the Kernel's code quality standards.
   9
  10 Signed-off-by: Roman Yeryomin <roman@advem.lv>
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
  13 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
  14 ---
  15  drivers/net/wireless/ralink/rt2x00/Kconfig     |    2 +-
  16  drivers/net/wireless/ralink/rt2x00/rt2800.h    |  177 +++
  17  drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 1421 +++++++++++++++++++++++-
  18  drivers/net/wireless/ralink/rt2x00/rt2800lib.h |    4 +
  19  drivers/net/wireless/ralink/rt2x00/rt2x00.h    |    1 +
  20  5 files changed, 1578 insertions(+), 27 deletions(-)
  21
  22 diff --git a/drivers/net/wireless/ralink/rt2x00/Kconfig b/drivers/net/wireless/ralink/rt2x00/Kconfig
  23 index de62f5dcb62f..a1d1cfe214d2 100644
  24 --- a/drivers/net/wireless/ralink/rt2x00/Kconfig
  25 +++ b/drivers/net/wireless/ralink/rt2x00/Kconfig
  26 @@ -210,7 +210,7 @@ endif
  27  config RT2800SOC
  28         tristate "Ralink WiSoC support"
  29         depends on m
  30 -       depends on SOC_RT288X || SOC_RT305X
  31 +       depends on SOC_RT288X || SOC_RT305X || SOC_MT7620
  32         select RT2X00_LIB_SOC
  33         select RT2X00_LIB_MMIO
  34         select RT2X00_LIB_CRYPTO
  35 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800.h b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  36 index fd1dbd956bad..6a8c93fb6a43 100644
  37 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  38 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  39 @@ -79,6 +79,7 @@
  40  #define RF5372                         0x5372
  41  #define RF5390                         0x5390
  42  #define RF5392                         0x5392
  43 +#define RF7620                         0x7620
  44
  45  /*
  46   * Chipset revisions.
  47 @@ -639,6 +640,24 @@
  48  #define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
  49
  50  /*
  51 + * MT7620 RF registers (reversed order)
  52 + */
  53 +#define RF_CSR_CFG_DATA_MT7620         FIELD32(0x0000ff00)
  54 +#define RF_CSR_CFG_REGNUM_MT7620       FIELD32(0x03ff0000)
  55 +#define RF_CSR_CFG_WRITE_MT7620                FIELD32(0x00000010)
  56 +#define RF_CSR_CFG_BUSY_MT7620         FIELD32(0x00000001)
  57 +
  58 +/* undocumented registers for calibration of new MAC */
  59 +#define RF_CONTROL0                    0x0518
  60 +#define RF_BYPASS0                     0x051c
  61 +#define RF_CONTROL1                    0x0520
  62 +#define RF_BYPASS1                     0x0524
  63 +#define RF_CONTROL2                    0x0528
  64 +#define RF_BYPASS2                     0x052c
  65 +#define RF_CONTROL3                    0x0530
  66 +#define RF_BYPASS3                     0x0534
  67 +
  68 +/*
  69   * EFUSE_CSR: RT30x0 EEPROM
  70   */
  71  #define EFUSE_CTRL                     0x0580
  72 @@ -1022,6 +1041,16 @@
  73  #define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
  74
  75  /*
  76 + * MIMO_PS_CFG: MIMO Power-save Configuration
  77 + */
  78 +#define MIMO_PS_CFG                    0x1210
  79 +#define MIMO_PS_CFG_MMPS_BB_EN         FIELD32(0x00000001)
  80 +#define MIMO_PS_CFG_MMPS_RX_ANT_NUM    FIELD32(0x00000006)
  81 +#define MIMO_PS_CFG_MMPS_RF_EN         FIELD32(0x00000008)
  82 +#define MIMO_PS_CFG_RX_STBY_POL                FIELD32(0x00000010)
  83 +#define MIMO_PS_CFG_RX_RX_STBY0                FIELD32(0x00000020)
  84 +
  85 +/*
  86   * EDCA_AC0_CFG:
  87   */
  88  #define EDCA_AC0_CFG                   0x1300
  89 @@ -1095,6 +1124,12 @@
  90  #define TX_PWR_CFG_0_OFDM6_CH1         FIELD32(0x00f00000)
  91  #define TX_PWR_CFG_0_OFDM12_CH0                FIELD32(0x0f000000)
  92  #define TX_PWR_CFG_0_OFDM12_CH1                FIELD32(0xf0000000)
  93 +/* bits for new 2T devices */
  94 +#define TX_PWR_CFG_0B_1MBS_2MBS                FIELD32(0x000000ff)
  95 +#define TX_PWR_CFG_0B_5MBS_11MBS               FIELD32(0x0000ff00)
  96 +#define TX_PWR_CFG_0B_6MBS_9MBS                FIELD32(0x00ff0000)
  97 +#define TX_PWR_CFG_0B_12MBS_18MBS      FIELD32(0xff000000)
  98 +
  99
 100  /*
 101   * TX_PWR_CFG_1:
 102 @@ -1117,6 +1152,11 @@
 103  #define TX_PWR_CFG_1_MCS0_CH1          FIELD32(0x00f00000)
 104  #define TX_PWR_CFG_1_MCS2_CH0          FIELD32(0x0f000000)
 105  #define TX_PWR_CFG_1_MCS2_CH1          FIELD32(0xf0000000)
 106 +/* bits for new 2T devices */
 107 +#define TX_PWR_CFG_1B_24MBS_36MBS      FIELD32(0x000000ff)
 108 +#define TX_PWR_CFG_1B_48MBS            FIELD32(0x0000ff00)
 109 +#define TX_PWR_CFG_1B_MCS0_MCS1                FIELD32(0x00ff0000)
 110 +#define TX_PWR_CFG_1B_MCS2_MCS3                FIELD32(0xff000000)
 111
 112  /*
 113   * TX_PWR_CFG_2:
 114 @@ -1139,6 +1179,11 @@
 115  #define TX_PWR_CFG_2_MCS8_CH1          FIELD32(0x00f00000)
 116  #define TX_PWR_CFG_2_MCS10_CH0         FIELD32(0x0f000000)
 117  #define TX_PWR_CFG_2_MCS10_CH1         FIELD32(0xf0000000)
 118 +/* bits for new 2T devices */
 119 +#define TX_PWR_CFG_2B_MCS4_MCS5                FIELD32(0x000000ff)
 120 +#define TX_PWR_CFG_2B_MCS6_MCS7                FIELD32(0x0000ff00)
 121 +#define TX_PWR_CFG_2B_MCS8_MCS9                FIELD32(0x00ff0000)
 122 +#define TX_PWR_CFG_2B_MCS10_MCS11      FIELD32(0xff000000)
 123
 124  /*
 125   * TX_PWR_CFG_3:
 126 @@ -1161,6 +1206,11 @@
 127  #define TX_PWR_CFG_3_STBC0_CH1         FIELD32(0x00f00000)
 128  #define TX_PWR_CFG_3_STBC2_CH0         FIELD32(0x0f000000)
 129  #define TX_PWR_CFG_3_STBC2_CH1         FIELD32(0xf0000000)
 130 +/* bits for new 2T devices */
 131 +#define TX_PWR_CFG_3B_MCS12_MCS13      FIELD32(0x000000ff)
 132 +#define TX_PWR_CFG_3B_MCS14            FIELD32(0x0000ff00)
 133 +#define TX_PWR_CFG_3B_STBC_MCS0_MCS1   FIELD32(0x00ff0000)
 134 +#define TX_PWR_CFG_3B_STBC_MCS2_MSC3   FIELD32(0xff000000)
 135
 136  /*
 137   * TX_PWR_CFG_4:
 138 @@ -1175,6 +1225,9 @@
 139  #define TX_PWR_CFG_4_STBC4_CH1         FIELD32(0x000000f0)
 140  #define TX_PWR_CFG_4_STBC6_CH0         FIELD32(0x00000f00)
 141  #define TX_PWR_CFG_4_STBC6_CH1         FIELD32(0x0000f000)
 142 +/* bits for new 2T devices */
 143 +#define TX_PWR_CFG_4B_STBC_MCS4_MCS5   FIELD32(0x000000ff)
 144 +#define TX_PWR_CFG_4B_STBC_MCS6                FIELD32(0x0000ff00)
 145
 146  /*
 147   * TX_PIN_CFG:
 148 @@ -1201,6 +1254,8 @@
 149  #define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
 150  #define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
 151  #define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
 152 +#define TX_PIN_CFG_RFRX_EN             FIELD32(0x00100000)
 153 +#define TX_PIN_CFG_RFRX_POL            FIELD32(0x00200000)
 154  #define TX_PIN_CFG_PA_PE_A2_EN         FIELD32(0x01000000)
 155  #define TX_PIN_CFG_PA_PE_G2_EN         FIELD32(0x02000000)
 156  #define TX_PIN_CFG_PA_PE_A2_POL                FIELD32(0x04000000)
 157 @@ -1547,6 +1602,95 @@
 158  #define TX_PWR_CFG_4_EXT_STBC4_CH2     FIELD32(0x0000000f)
 159  #define TX_PWR_CFG_4_EXT_STBC6_CH2     FIELD32(0x00000f00)
 160
 161 +/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
 162 + * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
 163 + */
 164 +#define TX0_RF_GAIN_CORRECT            0x13a0
 165 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
 166 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
 167 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
 168 +#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
 169 +
 170 +#define TX1_RF_GAIN_CORRECT            0x13a4
 171 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0        FIELD32(0x0000003f)
 172 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1        FIELD32(0x00003f00)
 173 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2        FIELD32(0x003f0000)
 174 +#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3        FIELD32(0x3f000000)
 175 +
 176 +/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
 177 + * Format: 7-bit, signed value
 178 + * Unit: 0.5 dB, Range: -20 dB to -5 dB
 179 + */
 180 +#define TX0_RF_GAIN_ATTEN              0x13a8
 181 +#define TX0_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
 182 +#define TX0_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
 183 +#define TX0_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
 184 +#define TX0_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
 185 +#define TX1_RF_GAIN_ATTEN              0x13ac
 186 +#define TX1_RF_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000007f)
 187 +#define TX1_RF_GAIN_ATTEN_LEVEL_1      FIELD32(0x00007f00)
 188 +#define TX1_RF_GAIN_ATTEN_LEVEL_2      FIELD32(0x007f0000)
 189 +#define TX1_RF_GAIN_ATTEN_LEVEL_3      FIELD32(0x7f000000)
 190 +
 191 +/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
 192 + * TX_ALC_LIMIT_n: TXn upper limit
 193 + * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
 194 + * Unit: 0.5 dB, Range: 0 to 23.5 dB
 195 + */
 196 +#define TX_ALC_CFG_0                   0x13b0
 197 +#define TX_ALC_CFG_0_CH_INIT_0         FIELD32(0x0000003f)
 198 +#define TX_ALC_CFG_0_CH_INIT_1         FIELD32(0x00003f00)
 199 +#define TX_ALC_CFG_0_LIMIT_0           FIELD32(0x003f0000)
 200 +#define TX_ALC_CFG_0_LIMIT_1           FIELD32(0x3f000000)
 201 +
 202 +/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
 203 + * TX_TEMP_COMP:      TX Power Temperature Compensation
 204 + *                    Unit: 0.5 dB, Range: -10 dB to 10 dB
 205 + * TXn_GAIN_FINE:     TXn Gain Fine Adjustment
 206 + *                    Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
 207 + * RF_TOS_DLY:        Sets the RF_TOS_EN assertion delay after
 208 + *                    deassertion of PA_PE.
 209 + *                    Unit: 0.25 usec
 210 + * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
 211 + * RF_TOS_TIMEOUT:    time-out value for RF_TOS_ENABLE
 212 + *                    deassertion if RF_TOS_DONE is missing.
 213 + *                    Unit: 0.25 usec
 214 + * RF_TOS_ENABLE:     TX offset calibration enable
 215 + * ROS_BUSY_EN:       RX offset calibration busy enable
 216 + */
 217 +#define TX_ALC_CFG_1                   0x13b4
 218 +#define TX_ALC_CFG_1_TX_TEMP_COMP      FIELD32(0x0000003f)
 219 +#define TX_ALC_CFG_1_TX0_GAIN_FINE     FIELD32(0x00000f00)
 220 +#define TX_ALC_CFG_1_TX1_GAIN_FINE     FIELD32(0x0000f000)
 221 +#define TX_ALC_CFG_1_RF_TOS_DLY                FIELD32(0x00070000)
 222 +#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
 223 +#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
 224 +#define TX_ALC_CFG_1_RF_TOS_TIMEOUT    FIELD32(0x3f000000)
 225 +#define TX_ALC_CFG_1_RF_TOS_ENABLE     FIELD32(0x40000000)
 226 +#define TX_ALC_CFG_1_ROS_BUSY_EN       FIELD32(0x80000000)
 227 +
 228 +/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
 229 + * Format: 5-bit signed values
 230 + * Unit: 0.5 dB, Range: -8 dB to 7 dB
 231 + */
 232 +#define TX0_BB_GAIN_ATTEN              0x13c0
 233 +#define TX0_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
 234 +#define TX0_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
 235 +#define TX0_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
 236 +#define TX0_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
 237 +#define TX1_BB_GAIN_ATTEN              0x13c4
 238 +#define TX1_BB_GAIN_ATTEN_LEVEL_0      FIELD32(0x0000001f)
 239 +#define TX1_BB_GAIN_ATTEN_LEVEL_1      FIELD32(0x00001f00)
 240 +#define TX1_BB_GAIN_ATTEN_LEVEL_2      FIELD32(0x001f0000)
 241 +#define TX1_BB_GAIN_ATTEN_LEVEL_3      FIELD32(0x1f000000)
 242 +
 243 +/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
 244 +#define TX_ALC_VGA3                    0x13c8
 245 +#define TX_ALC_VGA3_TX0_ALC_VGA3       FIELD32(0x0000001f)
 246 +#define TX_ALC_VGA3_TX1_ALC_VGA3       FIELD32(0x00001f00)
 247 +#define TX_ALC_VGA3_TX0_ALC_VGA2       FIELD32(0x001f0000)
 248 +#define TX_ALC_VGA3_TX1_ALC_VGA2       FIELD32(0x1f000000)
 249 +
 250  /* TX_PWR_CFG_7 */
 251  #define TX_PWR_CFG_7                   0x13d4
 252  #define TX_PWR_CFG_7_OFDM54_CH0                FIELD32(0x0000000f)
 253 @@ -1555,6 +1699,10 @@
 254  #define TX_PWR_CFG_7_MCS7_CH0          FIELD32(0x000f0000)
 255  #define TX_PWR_CFG_7_MCS7_CH1          FIELD32(0x00f00000)
 256  #define TX_PWR_CFG_7_MCS7_CH2          FIELD32(0x0f000000)
 257 +/* bits for new 2T devices */
 258 +#define TX_PWR_CFG_7B_54MBS            FIELD32(0x000000ff)
 259 +#define TX_PWR_CFG_7B_MCS7             FIELD32(0x00ff0000)
 260 +
 261
 262  /* TX_PWR_CFG_8 */
 263  #define TX_PWR_CFG_8                   0x13d8
 264 @@ -1564,12 +1712,17 @@
 265  #define TX_PWR_CFG_8_MCS23_CH0         FIELD32(0x000f0000)
 266  #define TX_PWR_CFG_8_MCS23_CH1         FIELD32(0x00f00000)
 267  #define TX_PWR_CFG_8_MCS23_CH2         FIELD32(0x0f000000)
 268 +/* bits for new 2T devices */
 269 +#define TX_PWR_CFG_8B_MCS15            FIELD32(0x000000ff)
 270 +
 271
 272  /* TX_PWR_CFG_9 */
 273  #define TX_PWR_CFG_9                   0x13dc
 274  #define TX_PWR_CFG_9_STBC7_CH0         FIELD32(0x0000000f)
 275  #define TX_PWR_CFG_9_STBC7_CH1         FIELD32(0x000000f0)
 276  #define TX_PWR_CFG_9_STBC7_CH2         FIELD32(0x00000f00)
 277 +/* bits for new 2T devices */
 278 +#define TX_PWR_CFG_9B_STBC_MCS7                FIELD32(0x000000ff)
 279
 280  /*
 281   * RX_FILTER_CFG: RX configuration register.
 282 @@ -2137,11 +2290,14 @@ struct mac_iveiv_entry {
 283  #define RFCSR1_TX1_PD                  FIELD8(0x20)
 284  #define RFCSR1_RX2_PD                  FIELD8(0x40)
 285  #define RFCSR1_TX2_PD                  FIELD8(0x80)
 286 +#define RFCSR1_TX2_EN_MT7620           FIELD8(0x02)
 287
 288  /*
 289   * RFCSR 2:
 290   */
 291  #define RFCSR2_RESCAL_EN               FIELD8(0x80)
 292 +#define RFCSR2_RX2_EN_MT7620           FIELD8(0x02)
 293 +#define RFCSR2_TX2_EN_MT7620           FIELD8(0x20)
 294
 295  /*
 296   * RFCSR 3:
 297 @@ -2160,6 +2316,12 @@ struct mac_iveiv_entry {
 298  #define RFCSR3_BIT5                    FIELD8(0x20)
 299
 300  /*
 301 + * RFCSR 4:
 302 + * VCOCAL_EN used by MT7620
 303 + */
 304 +#define RFCSR4_VCOCAL_EN               FIELD8(0x80)
 305 +
 306 +/*
 307   * FRCSR 5:
 308   */
 309  #define RFCSR5_R1                      FIELD8(0x0c)
 310 @@ -2214,6 +2376,7 @@ struct mac_iveiv_entry {
 311   */
 312  #define RFCSR13_TX_POWER               FIELD8(0x1f)
 313  #define RFCSR13_DR0                    FIELD8(0xe0)
 314 +#define RFCSR13_RDIV_MT7620            FIELD8(0x03)
 315
 316  /*
 317   * RFCSR 15:
 318 @@ -2224,6 +2387,8 @@ struct mac_iveiv_entry {
 319   * RFCSR 16:
 320   */
 321  #define RFCSR16_TXMIXER_GAIN           FIELD8(0x07)
 322 +#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
 323 +#define RFCSR16_SDM_MODE_MT7620                FIELD8(0xE0)
 324
 325  /*
 326   * RFCSR 17:
 327 @@ -2236,6 +2401,8 @@ struct mac_iveiv_entry {
 328  /* RFCSR 18 */
 329  #define RFCSR18_XO_TUNE_BYPASS         FIELD8(0x40)
 330
 331 +/* RFCSR 19 */
 332 +#define RFCSR19_K                      FIELD8(0x03)
 333
 334  /*
 335   * RFCSR 20:
 336 @@ -2246,11 +2413,14 @@ struct mac_iveiv_entry {
 337   * RFCSR 21:
 338   */
 339  #define RFCSR21_RX_LO2_EN              FIELD8(0x08)
 340 +#define RFCSR21_BIT1                   FIELD8(0x01)
 341 +#define RFCSR21_BIT8                   FIELD8(0x80)
 342
 343  /*
 344   * RFCSR 22:
 345   */
 346  #define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
 347 +#define RFCSR22_FREQPLAN_D_MT7620      FIELD8(0x07)
 348
 349  /*
 350   * RFCSR 23:
 351 @@ -2273,6 +2443,11 @@ struct mac_iveiv_entry {
 352  #define RFCSR27_R4                     FIELD8(0x40)
 353
 354  /*
 355 + * RFCSR 28:
 356 + */
 357 +#define RFCSR28_CH11_HT40              FIELD8(0x04)
 358 +
 359 +/*
 360   * RFCSR 29:
 361   */
 362  #define RFCSR29_ADC6_TEST              FIELD8(0x01)
 363 @@ -2333,6 +2508,7 @@ struct mac_iveiv_entry {
 364   */
 365  #define RFCSR42_BIT1                   FIELD8(0x01)
 366  #define RFCSR42_BIT4                   FIELD8(0x08)
 367 +#define RFCSR42_TX2_EN_MT7620          FIELD8(0x40)
 368
 369  /*
 370   * RFCSR 49:
 371 @@ -2435,6 +2611,7 @@ enum rt2800_eeprom_word {
 372         EEPROM_TSSI_BOUND_BG5,
 373         EEPROM_TXPOWER_A1,
 374         EEPROM_TXPOWER_A2,
 375 +       EEPROM_TXPOWER_INIT,
 376         EEPROM_TSSI_BOUND_A1,
 377         EEPROM_TSSI_BOUND_A2,
 378         EEPROM_TSSI_BOUND_A3,
 379 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
 380 index 8d00c599e47a..201b12ed90c6 100644
 381 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
 382 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
 383 @@ -59,6 +59,9 @@
 384         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
 385  #define WAIT_FOR_RFCSR(__dev, __reg) \
 386         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
 387 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
 388 +       rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
 389 +                           (__reg))
 390  #define WAIT_FOR_RF(__dev, __reg) \
 391         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 392  #define WAIT_FOR_MCU(__dev, __reg) \
 393 @@ -150,19 +153,56 @@ static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 394          * Wait until the RFCSR becomes available, afterwards we
 395          * can safely write the new data into the register.
 396          */
 397 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 398 -               reg = 0;
 399 -               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 400 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 401 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 402 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 403 +       switch (rt2x00dev->chip.rt) {
 404 +       case RT6352:
 405 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 406 +                       reg = 0;
 407 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 408 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 409 +                                          word);
 410 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 411 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 412 +
 413 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 414 +               }
 415 +               break;
 416
 417 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 418 +       default:
 419 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 420 +                       reg = 0;
 421 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 422 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 423 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 424 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 425 +
 426 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 427 +               }
 428 +               break;
 429         }
 430
 431         mutex_unlock(&rt2x00dev->csr_mutex);
 432  }
 433
 434 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 435 +                                   const unsigned int reg, const u8 value)
 436 +{
 437 +       rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 438 +}
 439 +
 440 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 441 +                                      const unsigned int reg, const u8 value)
 442 +{
 443 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 444 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 445 +}
 446 +
 447 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 448 +                                    const unsigned int reg, const u8 value)
 449 +{
 450 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 451 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 452 +}
 453 +
 454  static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 455                               const unsigned int word, u8 *value)
 456  {
 457 @@ -178,22 +218,48 @@ static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 458          * doesn't become available in time, reg will be 0xffffffff
 459          * which means we return 0xff to the caller.
 460          */
 461 -       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 462 -               reg = 0;
 463 -               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 464 -               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 465 -               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 466 +       switch (rt2x00dev->chip.rt) {
 467 +       case RT6352:
 468 +               if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 469 +                       reg = 0;
 470 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 471 +                                          word);
 472 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 473 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 474
 475 -               rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 476 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 477
 478 -               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 479 -       }
 480 +                       WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 481 +               }
 482
 483 -       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 484 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 485 +               break;
 486 +
 487 +       default:
 488 +               if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 489 +                       reg = 0;
 490 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 491 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 492 +                       rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 493 +
 494 +                       rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 495 +
 496 +                       WAIT_FOR_RFCSR(rt2x00dev, &reg);
 497 +               }
 498 +
 499 +               *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 500 +               break;
 501 +       }
 502
 503         mutex_unlock(&rt2x00dev->csr_mutex);
 504  }
 505
 506 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 507 +                                  const unsigned int reg, u8 *value)
 508 +{
 509 +       rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
 510 +}
 511 +
 512  static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 513                             const unsigned int word, const u32 value)
 514  {
 515 @@ -250,6 +316,7 @@ static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 516         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 517         [EEPROM_TXPOWER_A1]             = 0x003c,
 518         [EEPROM_TXPOWER_A2]             = 0x0053,
 519 +       [EEPROM_TXPOWER_INIT]           = 0x0068,
 520         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 521         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 522         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 523 @@ -524,6 +591,7 @@ void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 524                 break;
 525
 526         case RT5592:
 527 +       case RT6352:
 528                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 529                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 530                 break;
 531 @@ -2810,7 +2878,8 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
 532                                 rt2800_rfcsr_write(rt2x00dev, 59,
 533                                                    r59_nonbt_rev[idx]);
 534                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
 535 -                                  rt2x00_rt(rt2x00dev, RT5392)) {
 536 +                                  rt2x00_rt(rt2x00dev, RT5392) ||
 537 +                                  rt2x00_rt(rt2x00dev, RT6352)) {
 538                                 static const char r59_non_bt[] = {0x8f, 0x8f,
 539                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
 540                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
 541 @@ -3104,6 +3173,242 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
 542         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
 543  }
 544
 545 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
 546 +                                        struct ieee80211_conf *conf,
 547 +                                        struct rf_channel *rf,
 548 +                                        struct channel_info *info)
 549 +{
 550 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 551 +       u8 rx_agc_fc, tx_agc_fc;
 552 +       u8 rfcsr;
 553 +
 554 +       /* Frequeny plan setting */
 555 +       /* Rdiv setting (set 0x03 if Xtal==20)
 556 +        * R13[1:0]
 557 +        */
 558 +       rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
 559 +       rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
 560 +                         rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
 561 +       rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 562 +
 563 +       /* N setting
 564 +        * R20[7:0] in rf->rf1
 565 +        * R21[0] always 0
 566 +        */
 567 +       rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
 568 +       rfcsr = (rf->rf1 & 0x00ff);
 569 +       rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
 570 +
 571 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 572 +       rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
 573 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 574 +
 575 +       /* K setting (always 0)
 576 +        * R16[3:0] (RF PLL freq selection)
 577 +        */
 578 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 579 +       rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
 580 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 581 +
 582 +       /* D setting (always 0)
 583 +        * R22[2:0] (D=15, R22[2:0]=<111>)
 584 +        */
 585 +       rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
 586 +       rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
 587 +       rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 588 +
 589 +       /* Ksd setting
 590 +        * Ksd: R17<7:0> in rf->rf2
 591 +        *      R18<7:0> in rf->rf3
 592 +        *      R19<1:0> in rf->rf4
 593 +        */
 594 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
 595 +       rfcsr = rf->rf2;
 596 +       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 597 +
 598 +       rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
 599 +       rfcsr = rf->rf3;
 600 +       rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
 601 +
 602 +       rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
 603 +       rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
 604 +       rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
 605 +
 606 +       /* Default: XO=20MHz , SDM mode */
 607 +       rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
 608 +       rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
 609 +       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
 610 +
 611 +       rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
 612 +       rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
 613 +       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
 614 +
 615 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
 616 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
 617 +                         rt2x00dev->default_ant.tx_chain_num != 1);
 618 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 619 +
 620 +       rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
 621 +       rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
 622 +                         rt2x00dev->default_ant.tx_chain_num != 1);
 623 +       rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
 624 +                         rt2x00dev->default_ant.rx_chain_num != 1);
 625 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 626 +
 627 +       rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
 628 +       rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
 629 +                         rt2x00dev->default_ant.tx_chain_num != 1);
 630 +       rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
 631 +
 632 +       /* RF for DC Cal BW */
 633 +       if (conf_is_ht40(conf)) {
 634 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
 635 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
 636 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
 637 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
 638 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
 639 +       } else {
 640 +               rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
 641 +               rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
 642 +               rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
 643 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
 644 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
 645 +       }
 646 +
 647 +       if (conf_is_ht40(conf)) {
 648 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
 649 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
 650 +       } else {
 651 +               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
 652 +               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
 653 +       }
 654 +
 655 +       rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
 656 +       rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
 657 +                         conf_is_ht40(conf) && (rf->channel == 11));
 658 +       rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
 659 +
 660 +       if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
 661 +               if (conf_is_ht40(conf)) {
 662 +                       rx_agc_fc = drv_data->rx_calibration_bw40;
 663 +                       tx_agc_fc = drv_data->tx_calibration_bw40;
 664 +               } else {
 665 +                       rx_agc_fc = drv_data->rx_calibration_bw20;
 666 +                       tx_agc_fc = drv_data->tx_calibration_bw20;
 667 +               }
 668 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
 669 +               rfcsr &= (~0x3F);
 670 +               rfcsr |= rx_agc_fc;
 671 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
 672 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
 673 +               rfcsr &= (~0x3F);
 674 +               rfcsr |= rx_agc_fc;
 675 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
 676 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
 677 +               rfcsr &= (~0x3F);
 678 +               rfcsr |= rx_agc_fc;
 679 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
 680 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
 681 +               rfcsr &= (~0x3F);
 682 +               rfcsr |= rx_agc_fc;
 683 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
 684 +
 685 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
 686 +               rfcsr &= (~0x3F);
 687 +               rfcsr |= tx_agc_fc;
 688 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
 689 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
 690 +               rfcsr &= (~0x3F);
 691 +               rfcsr |= tx_agc_fc;
 692 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
 693 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
 694 +               rfcsr &= (~0x3F);
 695 +               rfcsr |= tx_agc_fc;
 696 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
 697 +               rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
 698 +               rfcsr &= (~0x3F);
 699 +               rfcsr |= tx_agc_fc;
 700 +               rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
 701 +       }
 702 +}
 703 +
 704 +static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
 705 +                             struct ieee80211_channel *chan,
 706 +                             int power_level) {
 707 +       u16 eeprom, target_power, max_power;
 708 +       u32 mac_sys_ctrl, mac_status;
 709 +       u32 reg;
 710 +       u8 bbp;
 711 +       int i;
 712 +
 713 +       /* hardware unit is 0.5dBm, limited to 23.5dBm */
 714 +       power_level *= 2;
 715 +       if (power_level > 0x2f)
 716 +               power_level = 0x2f;
 717 +
 718 +       max_power = chan->max_power * 2;
 719 +       if (max_power > 0x2f)
 720 +               max_power = 0x2f;
 721 +
 722 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
 723 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
 724 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
 725 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
 726 +       rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
 727 +
 728 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
 729 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
 730 +               /* init base power by eeprom target power */
 731 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
 732 +                                  &target_power);
 733 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
 734 +               rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
 735 +       }
 736 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
 737 +
 738 +       rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
 739 +       rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
 740 +       rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 741 +
 742 +       /* Save MAC SYS CTRL registers */
 743 +       rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
 744 +       /* Disable Tx/Rx */
 745 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 746 +       /* Check MAC Tx/Rx idle */
 747 +       for (i = 0; i < 10000; i++) {
 748 +               rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
 749 +                                    &mac_status);
 750 +               if (mac_status & 0x3)
 751 +                       usleep_range(50, 200);
 752 +               else
 753 +                       break;
 754 +       }
 755 +
 756 +       if (i == 10000)
 757 +               rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
 758 +
 759 +       if (chan->center_freq > 2457) {
 760 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 761 +               bbp = 0x40;
 762 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 763 +               rt2800_rfcsr_write(rt2x00dev, 39, 0);
 764 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 765 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
 766 +               else
 767 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
 768 +       } else {
 769 +               rt2800_bbp_read(rt2x00dev, 30, &bbp);
 770 +               bbp = 0x1f;
 771 +               rt2800_bbp_write(rt2x00dev, 30, bbp);
 772 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 773 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 774 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
 775 +               else
 776 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 777 +       }
 778 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
 779 +}
 780 +
 781  static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
 782                                            const unsigned int word,
 783                                            const u8 value)
 784 @@ -3228,7 +3533,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 785                                   struct channel_info *info)
 786  {
 787         u32 reg;
 788 -       unsigned int tx_pin;
 789 +       u32 tx_pin;
 790         u8 bbp, rfcsr;
 791
 792         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
 793 @@ -3273,6 +3578,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 794         case RF5592:
 795                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
 796                 break;
 797 +       case RF7620:
 798 +               rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
 799 +               break;
 800         default:
 801                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 802         }
 803 @@ -3347,7 +3655,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 804
 805         if (rf->channel <= 14) {
 806                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
 807 -                   !rt2x00_rt(rt2x00dev, RT5392)) {
 808 +                   !rt2x00_rt(rt2x00dev, RT5392) &&
 809 +                   !rt2x00_rt(rt2x00dev, RT6352)) {
 810                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 811                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
 812                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
 813 @@ -3367,7 +3676,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 814                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
 815                 else if (rt2x00_rt(rt2x00dev, RT3593))
 816                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
 817 -               else
 818 +               else if (!rt2x00_rt(rt2x00dev, RT6352))
 819                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 820
 821                 if (rt2x00_rt(rt2x00dev, RT3593))
 822 @@ -3388,7 +3697,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 823         if (rt2x00_rt(rt2x00dev, RT3572))
 824                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
 825
 826 -       tx_pin = 0;
 827 +       rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
 828
 829         switch (rt2x00dev->default_ant.tx_chain_num) {
 830         case 3:
 831 @@ -3437,6 +3746,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 832
 833         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 834         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 835 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
 836
 837         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 838
 839 @@ -3495,7 +3805,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 840                 usleep_range(1000, 1500);
 841         }
 842
 843 -       if (rt2x00_rt(rt2x00dev, RT5592)) {
 844 +       if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
 845                 rt2800_bbp_write(rt2x00dev, 195, 141);
 846                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
 847
 848 @@ -4182,6 +4492,128 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
 849                            (unsigned long) regs[i]);
 850  }
 851
 852 +static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
 853 +                                        struct ieee80211_channel *chan,
 854 +                                        int power_level)
 855 +{
 856 +       u32 reg, pwreg;
 857 +       u16 eeprom;
 858 +       u32 data, gdata;
 859 +       u8 t, i;
 860 +       enum nl80211_band band = chan->band;
 861 +       int delta;
 862 +
 863 +       /* Warn user if bw_comp is set in EEPROM */
 864 +       delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
 865 +
 866 +       if (delta)
 867 +               rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
 868 +                           delta);
 869 +
 870 +       /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
 871 +        * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
 872 +        * driver does as well, though it looks kinda wrong.
 873 +        * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
 874 +        * the hardware has a problem handling 0x20, and as the code initially
 875 +        * used a fixed offset between HT20 and HT40 rates they had to work-
 876 +        * around that issue and most likely just forgot about it later on.
 877 +        * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
 878 +        * however, the corresponding EEPROM value is not respected by the
 879 +        * vendor driver, so maybe this is rather being taken care of the
 880 +        * TXALC and the driver doesn't need to handle it...?
 881 +        * Though this is all very awkward, just do as they did, as that's what
 882 +        * board vendors expected when they populated the EEPROM...
 883 +        */
 884 +       for (i = 0; i < 5; i++) {
 885 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 886 +                                             i * 2, &eeprom);
 887 +
 888 +               data = eeprom;
 889 +
 890 +               t = eeprom & 0x3f;
 891 +               if (t == 32)
 892 +                       t++;
 893 +
 894 +               gdata = t;
 895 +
 896 +               t = (eeprom & 0x3f00) >> 8;
 897 +               if (t == 32)
 898 +                       t++;
 899 +
 900 +               gdata |= (t << 8);
 901 +
 902 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
 903 +                                             (i * 2) + 1, &eeprom);
 904 +
 905 +               t = eeprom & 0x3f;
 906 +               if (t == 32)
 907 +                       t++;
 908 +
 909 +               gdata |= (t << 16);
 910 +
 911 +               t = (eeprom & 0x3f00) >> 8;
 912 +               if (t == 32)
 913 +                       t++;
 914 +
 915 +               gdata |= (t << 24);
 916 +               data |= (eeprom << 16);
 917 +
 918 +               if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
 919 +                       /* HT20 */
 920 +                       if (data != 0xffffffff)
 921 +                               rt2800_register_write(rt2x00dev,
 922 +                                                     TX_PWR_CFG_0 + (i * 4),
 923 +                                                     data);
 924 +               } else {
 925 +                       /* HT40 */
 926 +                       if (gdata != 0xffffffff)
 927 +                               rt2800_register_write(rt2x00dev,
 928 +                                                     TX_PWR_CFG_0 + (i * 4),
 929 +                                                     gdata);
 930 +               }
 931 +       }
 932 +
 933 +       /* Aparently Ralink ran out of space in the BYRATE calibration section
 934 +        * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
 935 +        * registers. As recent 2T chips use 8-bit instead of 4-bit values for
 936 +        * power-offsets more space would be needed. Ralink decided to keep the
 937 +        * EEPROM layout untouched and rather have some shared values covering
 938 +        * multiple bitrates.
 939 +        * Populate the registers not covered by the EEPROM in the same way the
 940 +        * vendor driver does.
 941 +        */
 942 +
 943 +       /* For OFDM 54MBS use value from OFDM 48MBS */
 944 +       pwreg = 0;
 945 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 946 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
 947 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
 948 +
 949 +       /* For MCS 7 use value from MCS 6 */
 950 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 951 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
 952 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
 953 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
 954 +
 955 +       /* For MCS 15 use value from MCS 14 */
 956 +       pwreg = 0;
 957 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 958 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
 959 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
 960 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
 961 +
 962 +       /* For STBC MCS 7 use value from STBC MCS 6 */
 963 +       pwreg = 0;
 964 +       rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 965 +       t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
 966 +       rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
 967 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
 968 +
 969 +       rt2800_config_alc(rt2x00dev, chan, power_level);
 970 +
 971 +       /* TODO: temperature compensation code! */
 972 +}
 973 +
 974  /*
 975   * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
 976   * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
 977 @@ -4378,6 +4810,8 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 978  {
 979         if (rt2x00_rt(rt2x00dev, RT3593))
 980                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
 981 +       else if (rt2x00_rt(rt2x00dev, RT6352))
 982 +               rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
 983         else
 984                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
 985  }
 986 @@ -4393,6 +4827,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
 987  {
 988         u32     tx_pin;
 989         u8      rfcsr;
 990 +       unsigned long min_sleep = 0;
 991
 992         /*
 993          * A voltage-controlled oscillator(VCO) is an electronic oscillator
 994 @@ -4431,6 +4866,15 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
 995                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
 996                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
 997                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 998 +               min_sleep = 1000;
 999 +               break;
1000 +       case RF7620:
1001 +               rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
1002 +               rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
1003 +               rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
1004 +               rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
1005 +               rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
1006 +               min_sleep = 2000;
1007                 break;
1008         default:
1009                 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
1010 @@ -4438,7 +4882,8 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
1011                 return;
1012         }
1013
1014 -       usleep_range(1000, 1500);
1015 +       if (min_sleep > 0)
1016 +               usleep_range(min_sleep, min_sleep * 2);
1017
1018         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
1019         if (rt2x00dev->rf_channel <= 14) {
1020 @@ -4470,6 +4915,42 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
1021         }
1022         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1023
1024 +       if (rt2x00_rt(rt2x00dev, RT6352)) {
1025 +               if (rt2x00dev->default_ant.tx_chain_num == 1) {
1026 +                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
1027 +                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
1028 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
1029 +                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
1030 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
1031 +                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
1032 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
1033 +                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
1034 +               } else {
1035 +                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
1036 +                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
1037 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
1038 +                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
1039 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
1040 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
1041 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
1042 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
1043 +               }
1044 +
1045 +               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
1046 +                       rt2800_bbp_write(rt2x00dev, 75, 0x60);
1047 +                       rt2800_bbp_write(rt2x00dev, 76, 0x44);
1048 +                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
1049 +                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
1050 +                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
1051 +               }
1052 +
1053 +               /* On 11A, We should delay and wait RF/BBP to be stable
1054 +                * and the appropriate time should be 1000 micro seconds
1055 +                * 2005/06/05 - On 11G, we also need this delay time.
1056 +                * Otherwise it's difficult to pass the WHQL.
1057 +                */
1058 +               usleep_range(1000, 1500);
1059 +       }
1060  }
1061  EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
1062
1063 @@ -4568,7 +5049,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1064                     rt2x00_rt(rt2x00dev, RT3593) ||
1065                     rt2x00_rt(rt2x00dev, RT5390) ||
1066                     rt2x00_rt(rt2x00dev, RT5392) ||
1067 -                   rt2x00_rt(rt2x00dev, RT5592))
1068 +                   rt2x00_rt(rt2x00dev, RT5592) ||
1069 +                   rt2x00_rt(rt2x00dev, RT6352))
1070                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
1071                 else
1072                         vgc = 0x2e + rt2x00dev->lna_gain;
1073 @@ -4795,7 +5277,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1074                                               0x00000000);
1075                 }
1076         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
1077 -                  rt2x00_rt(rt2x00dev, RT5392)) {
1078 +                  rt2x00_rt(rt2x00dev, RT5392) ||
1079 +                  rt2x00_rt(rt2x00dev, RT6352)) {
1080                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
1081                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1082                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1083 @@ -4805,6 +5288,24 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1084                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1085         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
1086                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
1087 +       } else if (rt2x00_rt(rt2x00dev, RT6352)) {
1088 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
1089 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
1090 +               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1091 +               rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
1092 +               rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
1093 +               rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
1094 +               rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
1095 +               rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
1096 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
1097 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
1098 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
1099 +                                     0x3630363A);
1100 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
1101 +                                     0x3630363A);
1102 +               rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
1103 +               rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
1104 +               rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
1105         } else {
1106                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1107                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1108 @@ -5786,6 +6287,231 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
1109                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1110  }
1111
1112 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
1113 +                                 const u8 reg, const u8 value)
1114 +{
1115 +       rt2800_bbp_write(rt2x00dev, 195, reg);
1116 +       rt2800_bbp_write(rt2x00dev, 196, value);
1117 +}
1118 +
1119 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
1120 +                                 const u8 reg, const u8 value)
1121 +{
1122 +       rt2800_bbp_write(rt2x00dev, 158, reg);
1123 +       rt2800_bbp_write(rt2x00dev, 159, value);
1124 +}
1125 +
1126 +static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev,
1127 +                                const u8 reg, u8 *value)
1128 +{
1129 +       rt2800_bbp_write(rt2x00dev, 158, reg);
1130 +       rt2800_bbp_read(rt2x00dev, 159, value);
1131 +}
1132 +
1133 +static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
1134 +{
1135 +       u8 bbp;
1136 +
1137 +       /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
1138 +       rt2800_bbp_read(rt2x00dev, 105, &bbp);
1139 +       rt2x00_set_field8(&bbp, BBP105_MLD,
1140 +                         rt2x00dev->default_ant.rx_chain_num == 2);
1141 +       rt2800_bbp_write(rt2x00dev, 105, bbp);
1142 +
1143 +       /* Avoid data loss and CRC errors */
1144 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1145 +
1146 +       /* Fix I/Q swap issue */
1147 +       rt2800_bbp_read(rt2x00dev, 1, &bbp);
1148 +       bbp |= 0x04;
1149 +       rt2800_bbp_write(rt2x00dev, 1, bbp);
1150 +
1151 +       /* BBP for G band */
1152 +       rt2800_bbp_write(rt2x00dev, 3, 0x08);
1153 +       rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
1154 +       rt2800_bbp_write(rt2x00dev, 6, 0x08);
1155 +       rt2800_bbp_write(rt2x00dev, 14, 0x09);
1156 +       rt2800_bbp_write(rt2x00dev, 15, 0xFF);
1157 +       rt2800_bbp_write(rt2x00dev, 16, 0x01);
1158 +       rt2800_bbp_write(rt2x00dev, 20, 0x06);
1159 +       rt2800_bbp_write(rt2x00dev, 21, 0x00);
1160 +       rt2800_bbp_write(rt2x00dev, 22, 0x00);
1161 +       rt2800_bbp_write(rt2x00dev, 27, 0x00);
1162 +       rt2800_bbp_write(rt2x00dev, 28, 0x00);
1163 +       rt2800_bbp_write(rt2x00dev, 30, 0x00);
1164 +       rt2800_bbp_write(rt2x00dev, 31, 0x48);
1165 +       rt2800_bbp_write(rt2x00dev, 47, 0x40);
1166 +       rt2800_bbp_write(rt2x00dev, 62, 0x00);
1167 +       rt2800_bbp_write(rt2x00dev, 63, 0x00);
1168 +       rt2800_bbp_write(rt2x00dev, 64, 0x00);
1169 +       rt2800_bbp_write(rt2x00dev, 65, 0x2C);
1170 +       rt2800_bbp_write(rt2x00dev, 66, 0x1C);
1171 +       rt2800_bbp_write(rt2x00dev, 67, 0x20);
1172 +       rt2800_bbp_write(rt2x00dev, 68, 0xDD);
1173 +       rt2800_bbp_write(rt2x00dev, 69, 0x10);
1174 +       rt2800_bbp_write(rt2x00dev, 70, 0x05);
1175 +       rt2800_bbp_write(rt2x00dev, 73, 0x18);
1176 +       rt2800_bbp_write(rt2x00dev, 74, 0x0F);
1177 +       rt2800_bbp_write(rt2x00dev, 75, 0x60);
1178 +       rt2800_bbp_write(rt2x00dev, 76, 0x44);
1179 +       rt2800_bbp_write(rt2x00dev, 77, 0x59);
1180 +       rt2800_bbp_write(rt2x00dev, 78, 0x1E);
1181 +       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
1182 +       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
1183 +       rt2800_bbp_write(rt2x00dev, 81, 0x3A);
1184 +       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
1185 +       rt2800_bbp_write(rt2x00dev, 83, 0x9A);
1186 +       rt2800_bbp_write(rt2x00dev, 84, 0x9A);
1187 +       rt2800_bbp_write(rt2x00dev, 86, 0x38);
1188 +       rt2800_bbp_write(rt2x00dev, 88, 0x90);
1189 +       rt2800_bbp_write(rt2x00dev, 91, 0x04);
1190 +       rt2800_bbp_write(rt2x00dev, 92, 0x02);
1191 +       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
1192 +       rt2800_bbp_write(rt2x00dev, 96, 0x00);
1193 +       rt2800_bbp_write(rt2x00dev, 103, 0xC0);
1194 +       rt2800_bbp_write(rt2x00dev, 104, 0x92);
1195 +       /* FIXME BBP105 owerwrite */
1196 +       rt2800_bbp_write(rt2x00dev, 105, 0x3C);
1197 +       rt2800_bbp_write(rt2x00dev, 106, 0x12);
1198 +       rt2800_bbp_write(rt2x00dev, 109, 0x00);
1199 +       rt2800_bbp_write(rt2x00dev, 134, 0x10);
1200 +       rt2800_bbp_write(rt2x00dev, 135, 0xA6);
1201 +       rt2800_bbp_write(rt2x00dev, 137, 0x04);
1202 +       rt2800_bbp_write(rt2x00dev, 142, 0x30);
1203 +       rt2800_bbp_write(rt2x00dev, 143, 0xF7);
1204 +       rt2800_bbp_write(rt2x00dev, 160, 0xEC);
1205 +       rt2800_bbp_write(rt2x00dev, 161, 0xC4);
1206 +       rt2800_bbp_write(rt2x00dev, 162, 0x77);
1207 +       rt2800_bbp_write(rt2x00dev, 163, 0xF9);
1208 +       rt2800_bbp_write(rt2x00dev, 164, 0x00);
1209 +       rt2800_bbp_write(rt2x00dev, 165, 0x00);
1210 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1211 +       rt2800_bbp_write(rt2x00dev, 187, 0x00);
1212 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1213 +       rt2800_bbp_write(rt2x00dev, 186, 0x00);
1214 +       rt2800_bbp_write(rt2x00dev, 187, 0x01);
1215 +       rt2800_bbp_write(rt2x00dev, 188, 0x00);
1216 +       rt2800_bbp_write(rt2x00dev, 189, 0x00);
1217 +
1218 +       rt2800_bbp_write(rt2x00dev, 91, 0x06);
1219 +       rt2800_bbp_write(rt2x00dev, 92, 0x04);
1220 +       rt2800_bbp_write(rt2x00dev, 93, 0x54);
1221 +       rt2800_bbp_write(rt2x00dev, 99, 0x50);
1222 +       rt2800_bbp_write(rt2x00dev, 148, 0x84);
1223 +       rt2800_bbp_write(rt2x00dev, 167, 0x80);
1224 +       rt2800_bbp_write(rt2x00dev, 178, 0xFF);
1225 +       rt2800_bbp_write(rt2x00dev, 106, 0x13);
1226 +
1227 +       /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
1228 +       rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
1229 +       rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
1230 +       rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
1231 +       rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
1232 +       rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
1233 +       rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
1234 +       rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
1235 +       rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
1236 +       rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
1237 +       rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
1238 +       rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
1239 +       rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
1240 +       rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
1241 +       rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
1242 +       rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
1243 +       rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
1244 +       rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
1245 +       rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
1246 +       rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
1247 +       rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
1248 +       rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
1249 +       rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
1250 +       rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
1251 +       rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
1252 +       rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
1253 +       rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
1254 +       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
1255 +       rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
1256 +       rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
1257 +       rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
1258 +       rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
1259 +       rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
1260 +       rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
1261 +       rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
1262 +       rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
1263 +       rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
1264 +       rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
1265 +       rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
1266 +       rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
1267 +       rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
1268 +       rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
1269 +       rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
1270 +       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
1271 +       rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
1272 +       rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
1273 +       rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
1274 +       rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
1275 +       rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
1276 +       rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
1277 +       rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
1278 +       rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
1279 +       rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
1280 +       rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
1281 +       rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
1282 +       rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
1283 +       rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
1284 +       rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
1285 +       rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
1286 +       rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
1287 +       rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
1288 +       rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
1289 +       rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
1290 +       rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
1291 +       rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
1292 +       rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
1293 +       rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
1294 +       rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
1295 +       rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
1296 +       rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
1297 +       rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
1298 +       rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
1299 +       rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
1300 +       rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
1301 +       rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
1302 +       rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
1303 +       rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
1304 +       rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
1305 +       rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
1306 +       rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
1307 +       rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
1308 +       rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
1309 +       rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
1310 +       rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
1311 +
1312 +       /* BBP for G band DCOC function */
1313 +       rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
1314 +       rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
1315 +       rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
1316 +       rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
1317 +       rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
1318 +       rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
1319 +       rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
1320 +       rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
1321 +       rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
1322 +       rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
1323 +       rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
1324 +       rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
1325 +       rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
1326 +       rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
1327 +       rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
1328 +       rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
1329 +       rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
1330 +       rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
1331 +       rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
1332 +       rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
1333 +
1334 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
1335 +}
1336 +
1337  static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1338  {
1339         unsigned int i;
1340 @@ -5830,6 +6556,9 @@ static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1341         case RT5592:
1342                 rt2800_init_bbp_5592(rt2x00dev);
1343                 return;
1344 +       case RT6352:
1345 +               rt2800_init_bbp_6352(rt2x00dev);
1346 +               break;
1347         }
1348
1349         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1350 @@ -6901,6 +7630,615 @@ static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
1351         rt2800_led_open_drain_enable(rt2x00dev);
1352  }
1353
1354 +static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
1355 +                                      bool set_bw, bool is_ht40)
1356 +{
1357 +       u8 bbp_val;
1358 +
1359 +       rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
1360 +       bbp_val |= 0x1;
1361 +       rt2800_bbp_write(rt2x00dev, 21, bbp_val);
1362 +       usleep_range(100, 200);
1363 +
1364 +       if (set_bw) {
1365 +               rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
1366 +               rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
1367 +               rt2800_bbp_write(rt2x00dev, 4, bbp_val);
1368 +               usleep_range(100, 200);
1369 +       }
1370 +
1371 +       rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
1372 +       bbp_val &= (~0x1);
1373 +       rt2800_bbp_write(rt2x00dev, 21, bbp_val);
1374 +       usleep_range(100, 200);
1375 +}
1376 +
1377 +static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
1378 +{
1379 +       u8 rf_val;
1380 +
1381 +       if (btxcal)
1382 +               rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
1383 +       else
1384 +               rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
1385 +
1386 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
1387 +
1388 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &rf_val);
1389 +       rf_val |= 0x80;
1390 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
1391 +
1392 +       if (btxcal) {
1393 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
1394 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
1395 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
1396 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
1397 +               rf_val &= (~0x3F);
1398 +               rf_val |= 0x3F;
1399 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
1400 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
1401 +               rf_val &= (~0x3F);
1402 +               rf_val |= 0x3F;
1403 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
1404 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
1405 +       } else {
1406 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
1407 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
1408 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
1409 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val);
1410 +               rf_val &= (~0x3F);
1411 +               rf_val |= 0x34;
1412 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
1413 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val);
1414 +               rf_val &= (~0x3F);
1415 +               rf_val |= 0x34;
1416 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
1417 +       }
1418 +
1419 +       return 0;
1420 +}
1421 +
1422 +static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
1423 +{
1424 +       unsigned int cnt;
1425 +       u8 bbp_val;
1426 +       char cal_val;
1427 +
1428 +       rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
1429 +
1430 +       cnt = 0;
1431 +       do {
1432 +               usleep_range(500, 2000);
1433 +               rt2800_bbp_read(rt2x00dev, 159, &bbp_val);
1434 +               if (bbp_val == 0x02 || cnt == 20)
1435 +                       break;
1436 +
1437 +               cnt++;
1438 +       } while (cnt < 20);
1439 +
1440 +       rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val);
1441 +       cal_val = bbp_val & 0x7F;
1442 +       if (cal_val >= 0x40)
1443 +               cal_val -= 128;
1444 +
1445 +       return cal_val;
1446 +}
1447 +
1448 +static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
1449 +                                        bool btxcal)
1450 +{
1451 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1452 +       u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
1453 +       u8 filter_target;
1454 +       u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
1455 +       u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
1456 +       int loop = 0, is_ht40, cnt;
1457 +       u8 bbp_val, rf_val;
1458 +       char cal_r32_init, cal_r32_val, cal_diff;
1459 +       u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
1460 +       u8 saverfb5r06, saverfb5r07;
1461 +       u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
1462 +       u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
1463 +       u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
1464 +       u8 saverfb5r58, saverfb5r59;
1465 +       u8 savebbp159r0, savebbp159r2, savebbpr23;
1466 +       u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
1467 +
1468 +       /* Save MAC registers */
1469 +       rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0);
1470 +       rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0);
1471 +
1472 +       /* save BBP registers */
1473 +       rt2800_bbp_read(rt2x00dev, 23, &savebbpr23);
1474 +
1475 +       rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0);
1476 +       rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2);
1477 +
1478 +       /* Save RF registers */
1479 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &saverfb5r00);
1480 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &saverfb5r01);
1481 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &saverfb5r03);
1482 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &saverfb5r04);
1483 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 5, &saverfb5r05);
1484 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &saverfb5r06);
1485 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &saverfb5r07);
1486 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &saverfb5r08);
1487 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &saverfb5r17);
1488 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 18, &saverfb5r18);
1489 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 19, &saverfb5r19);
1490 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 20, &saverfb5r20);
1491 +
1492 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 37, &saverfb5r37);
1493 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 38, &saverfb5r38);
1494 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 39, &saverfb5r39);
1495 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 40, &saverfb5r40);
1496 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 41, &saverfb5r41);
1497 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 42, &saverfb5r42);
1498 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 43, &saverfb5r43);
1499 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 44, &saverfb5r44);
1500 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 45, &saverfb5r45);
1501 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 46, &saverfb5r46);
1502 +
1503 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &saverfb5r58);
1504 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &saverfb5r59);
1505 +
1506 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
1507 +       rf_val |= 0x3;
1508 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
1509 +
1510 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
1511 +       rf_val |= 0x1;
1512 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
1513 +
1514 +       cnt = 0;
1515 +       do {
1516 +               usleep_range(500, 2000);
1517 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val);
1518 +               if (((rf_val & 0x1) == 0x00) || (cnt == 40))
1519 +                       break;
1520 +               cnt++;
1521 +       } while (cnt < 40);
1522 +
1523 +       rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val);
1524 +       rf_val &= (~0x3);
1525 +       rf_val |= 0x1;
1526 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
1527 +
1528 +       /* I-3 */
1529 +       rt2800_bbp_read(rt2x00dev, 23, &bbp_val);
1530 +       bbp_val &= (~0x1F);
1531 +       bbp_val |= 0x10;
1532 +       rt2800_bbp_write(rt2x00dev, 23, bbp_val);
1533 +
1534 +       do {
1535 +               /* I-4,5,6,7,8,9 */
1536 +               if (loop == 0) {
1537 +                       is_ht40 = false;
1538 +
1539 +                       if (btxcal)
1540 +                               filter_target = tx_filter_target_20m;
1541 +                       else
1542 +                               filter_target = rx_filter_target_20m;
1543 +               } else {
1544 +                       is_ht40 = true;
1545 +
1546 +                       if (btxcal)
1547 +                               filter_target = tx_filter_target_40m;
1548 +                       else
1549 +                               filter_target = rx_filter_target_40m;
1550 +               }
1551 +
1552 +               rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &rf_val);
1553 +               rf_val &= (~0x04);
1554 +               if (loop == 1)
1555 +                       rf_val |= 0x4;
1556 +
1557 +               rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
1558 +
1559 +               rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
1560 +
1561 +               rt2800_rf_lp_config(rt2x00dev, btxcal);
1562 +               if (btxcal) {
1563 +                       tx_agc_fc = 0;
1564 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
1565 +                       rf_val &= (~0x7F);
1566 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
1567 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
1568 +                       rf_val &= (~0x7F);
1569 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
1570 +               } else {
1571 +                       rx_agc_fc = 0;
1572 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
1573 +                       rf_val &= (~0x7F);
1574 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
1575 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
1576 +                       rf_val &= (~0x7F);
1577 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
1578 +               }
1579 +
1580 +               usleep_range(1000, 2000);
1581 +
1582 +               rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
1583 +               bbp_val &= (~0x6);
1584 +               rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
1585 +
1586 +               rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
1587 +
1588 +               cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
1589 +
1590 +               rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
1591 +               bbp_val |= 0x6;
1592 +               rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
1593 +do_cal:
1594 +               if (btxcal) {
1595 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val);
1596 +                       rf_val &= (~0x7F);
1597 +                       rf_val |= tx_agc_fc;
1598 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
1599 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val);
1600 +                       rf_val &= (~0x7F);
1601 +                       rf_val |= tx_agc_fc;
1602 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
1603 +               } else {
1604 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val);
1605 +                       rf_val &= (~0x7F);
1606 +                       rf_val |= rx_agc_fc;
1607 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
1608 +                       rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val);
1609 +                       rf_val &= (~0x7F);
1610 +                       rf_val |= rx_agc_fc;
1611 +                       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
1612 +               }
1613 +
1614 +               usleep_range(500, 1000);
1615 +
1616 +               rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
1617 +
1618 +               cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
1619 +
1620 +               cal_diff = cal_r32_init - cal_r32_val;
1621 +
1622 +               if (btxcal)
1623 +                       cmm_agc_fc = tx_agc_fc;
1624 +               else
1625 +                       cmm_agc_fc = rx_agc_fc;
1626 +
1627 +               if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
1628 +                   ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
1629 +                       if (btxcal)
1630 +                               tx_agc_fc = 0;
1631 +                       else
1632 +                               rx_agc_fc = 0;
1633 +               } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
1634 +                       if (btxcal)
1635 +                               tx_agc_fc++;
1636 +                       else
1637 +                               rx_agc_fc++;
1638 +                       goto do_cal;
1639 +               }
1640 +
1641 +               if (btxcal) {
1642 +                       if (loop == 0)
1643 +                               drv_data->tx_calibration_bw20 = tx_agc_fc;
1644 +                       else
1645 +                               drv_data->tx_calibration_bw40 = tx_agc_fc;
1646 +               } else {
1647 +                       if (loop == 0)
1648 +                               drv_data->rx_calibration_bw20 = rx_agc_fc;
1649 +                       else
1650 +                               drv_data->rx_calibration_bw40 = rx_agc_fc;
1651 +               }
1652 +
1653 +               loop++;
1654 +       } while (loop <= 1);
1655 +
1656 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
1657 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
1658 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
1659 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
1660 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
1661 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
1662 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
1663 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
1664 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
1665 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
1666 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
1667 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
1668 +
1669 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
1670 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
1671 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
1672 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
1673 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
1674 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
1675 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
1676 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
1677 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
1678 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
1679 +
1680 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
1681 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
1682 +
1683 +       rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
1684 +
1685 +       rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
1686 +       rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
1687 +
1688 +       rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
1689 +       rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
1690 +                         2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
1691 +       rt2800_bbp_write(rt2x00dev, 4, bbp_val);
1692 +
1693 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
1694 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
1695 +}
1696 +
1697 +static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
1698 +{
1699 +       /* Initialize RF central register to default value */
1700 +       rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
1701 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
1702 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
1703 +       rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
1704 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
1705 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
1706 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
1707 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
1708 +       rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1709 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
1710 +       rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
1711 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1712 +       rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
1713 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1714 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
1715 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
1716 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
1717 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
1718 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
1719 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
1720 +       rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
1721 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
1722 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
1723 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
1724 +       rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
1725 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
1726 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
1727 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1728 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
1729 +       rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
1730 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1731 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1732 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
1733 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
1734 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
1735 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
1736 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
1737 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
1738 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
1739 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
1740 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
1741 +       rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
1742 +       rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
1743 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
1744 +
1745 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1746 +       if (rt2800_clk_is_20mhz(rt2x00dev))
1747 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
1748 +       else
1749 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
1750 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
1751 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
1752 +       rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
1753 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
1754 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
1755 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
1756 +       rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
1757 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1758 +       rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
1759 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
1760 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
1761 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
1762 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1763 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
1764 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
1765 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
1766 +
1767 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
1768 +       rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
1769 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
1770 +
1771 +       /* Initialize RF channel register to default value */
1772 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
1773 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
1774 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
1775 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
1776 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
1777 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
1778 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
1779 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
1780 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
1781 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
1782 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
1783 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1784 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
1785 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
1786 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1787 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
1788 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
1789 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
1790 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
1791 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1792 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
1793 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
1794 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
1795 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
1796 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
1797 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
1798 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
1799 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
1800 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
1801 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
1802 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
1803 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
1804 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
1805 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
1806 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
1807 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
1808 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
1809 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
1810 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
1811 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
1812 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
1813 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
1814 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
1815 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
1816 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
1817 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1818 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
1819 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
1820 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
1821 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
1822 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
1823 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
1824 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
1825 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
1826 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1827 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1828 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1829 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1830 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1831 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1832 +
1833 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1834 +
1835 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1836 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1837 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1838 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1839 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1840 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1841 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1842 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1843 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1844 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1845 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1846 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1847 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1848 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1849 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1850 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1851 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1852 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1853 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1854 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1855 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1856 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1857 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1858 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1859 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1860 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1861 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1862 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1863 +
1864 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1865 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1866 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1867 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1868 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1869 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1870 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1871 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1872 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1873 +
1874 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1875 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1876 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1877 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1878 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1879 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1880 +
1881 +       /* Initialize RF channel register for DRQFN */
1882 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1883 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1884 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1885 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1886 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1887 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1888 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1889 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1890 +
1891 +       /* Initialize RF DC calibration register to default value */
1892 +       rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1893 +       rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1894 +       rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1895 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1896 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1897 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1898 +       rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1899 +       rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1900 +       rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1901 +       rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1902 +       rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1903 +       rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1904 +       rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1905 +       rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1906 +       rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1907 +       rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1908 +       rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1909 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1910 +       rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1911 +       rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1912 +       rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1913 +       rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1914 +       rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1915 +       rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1916 +       rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1917 +       rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1918 +       rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1919 +       rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1920 +       rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1921 +       rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1922 +       rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1923 +       rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1924 +       rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1925 +       rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1926 +       rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1927 +       rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1928 +       rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1929 +       rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1930 +       rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1931 +       rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1932 +       rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1933 +       rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1934 +       rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1935 +       rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1936 +       rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1937 +       rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1938 +       rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1939 +       rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1940 +       rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1941 +       rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1942 +       rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1943 +       rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1944 +       rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1945 +       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1946 +       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1947 +       rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1948 +       rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1949 +       rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1950 +       rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1951 +
1952 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1953 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1954 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1955 +
1956 +       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1957 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1958 +
1959 +       rt2800_bw_filter_calibration(rt2x00dev, true);
1960 +       rt2800_bw_filter_calibration(rt2x00dev, false);
1961 +}
1962 +
1963  static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1964  {
1965         if (rt2800_is_305x_soc(rt2x00dev)) {
1966 @@ -6941,6 +8279,9 @@ static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1967         case RT5592:
1968                 rt2800_init_rfcsr_5592(rt2x00dev);
1969                 break;
1970 +       case RT6352:
1971 +               rt2800_init_rfcsr_6352(rt2x00dev);
1972 +               break;
1973         }
1974  }
1975
1976 @@ -7307,7 +8648,8 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1977          */
1978         if (rt2x00_rt(rt2x00dev, RT3290) ||
1979             rt2x00_rt(rt2x00dev, RT5390) ||
1980 -           rt2x00_rt(rt2x00dev, RT5392))
1981 +           rt2x00_rt(rt2x00dev, RT5392) ||
1982 +           rt2x00_rt(rt2x00dev, RT6352))
1983                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
1984         else if (rt2x00_rt(rt2x00dev, RT3352))
1985                 rf = RF3322;
1986 @@ -7339,6 +8681,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1987         case RF5390:
1988         case RF5392:
1989         case RF5592:
1990 +       case RF7620:
1991                 break;
1992         default:
1993                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1994 @@ -7746,6 +9089,23 @@ static const struct rf_channel rf_vals_5592_xtal40[] = {
1995         {196, 83, 0, 12, 1},
1996  };
1997
1998 +static const struct rf_channel rf_vals_7620[] = {
1999 +       {1, 0x50, 0x99, 0x99, 1},
2000 +       {2, 0x50, 0x44, 0x44, 2},
2001 +       {3, 0x50, 0xEE, 0xEE, 2},
2002 +       {4, 0x50, 0x99, 0x99, 3},
2003 +       {5, 0x51, 0x44, 0x44, 0},
2004 +       {6, 0x51, 0xEE, 0xEE, 0},
2005 +       {7, 0x51, 0x99, 0x99, 1},
2006 +       {8, 0x51, 0x44, 0x44, 2},
2007 +       {9, 0x51, 0xEE, 0xEE, 2},
2008 +       {10, 0x51, 0x99, 0x99, 3},
2009 +       {11, 0x52, 0x44, 0x44, 0},
2010 +       {12, 0x52, 0xEE, 0xEE, 0},
2011 +       {13, 0x52, 0x99, 0x99, 1},
2012 +       {14, 0x52, 0x33, 0x33, 3},
2013 +};
2014 +
2015  static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2016  {
2017         struct hw_mode_spec *spec = &rt2x00dev->spec;
2018 @@ -7849,6 +9209,11 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2019                         spec->channels = rf_vals_3x;
2020                 break;
2021
2022 +       case RF7620:
2023 +               spec->num_channels = ARRAY_SIZE(rf_vals_7620);
2024 +               spec->channels = rf_vals_7620;
2025 +               break;
2026 +
2027         case RF3052:
2028         case RF3053:
2029                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2030 @@ -7980,6 +9345,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2031         case RF5390:
2032         case RF5392:
2033         case RF5592:
2034 +       case RF7620:
2035                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
2036                 break;
2037         }
2038 @@ -8024,6 +9390,9 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
2039                 return -ENODEV;
2040         }
2041
2042 +       if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
2043 +               rt = RT6352;
2044 +
2045         rt2x00_set_rt(rt2x00dev, rt, rev);
2046
2047         return 0;
2048 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
2049 index d9ef260d542a..f357531d9488 100644
2050 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
2051 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
2052 @@ -33,6 +33,10 @@
2053  struct rt2800_drv_data {
2054         u8 calibration_bw20;
2055         u8 calibration_bw40;
2056 +       char rx_calibration_bw20;
2057 +       char rx_calibration_bw40;
2058 +       char tx_calibration_bw20;
2059 +       char tx_calibration_bw40;
2060         u8 bbp25;
2061         u8 bbp26;
2062         u8 txmixer_gain_24g;
2063 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00.h b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
2064 index ce340bfd71a0..8fdd2f9726ee 100644
2065 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
2066 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
2067 @@ -174,6 +174,7 @@ struct rt2x00_chip {
2068  #define RT5390         0x5390  /* 2.4GHz */
2069  #define RT5392         0x5392  /* 2.4GHz */
2070  #define RT5592         0x5592
2071 +#define RT6352         0x6352  /* WSOC 2.4GHz */
2072
2073         u16 rf;
2074         u16 rev;
2075 --
2076 2.12.1
2077