1 --- a/src/mps/drv_mps_vmmc_ar9.c
2 +++ b/src/mps/drv_mps_vmmc_ar9.c
4 #include "ifxos_interrupt.h"
6 /* board specific headers */
7 +#if !defined CONFIG_LANTIQ
8 #include <asm/ifx/ifx_regs.h>
9 #include <asm/ifx_vpe.h>
10 #include <asm/ifx/ifx_gpio.h>
13 +#include <lantiq_soc.h>
16 /* device specific headers */
17 #include "drv_mps_vmmc.h"
18 #include "drv_mps_vmmc_dbg.h"
19 #include "drv_mps_vmmc_device.h"
21 +const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;
23 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
25 /* ============================= */
26 /* Local Macros & Definitions */
27 /* ============================= */
28 @@ -98,6 +107,7 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui
30 IFX_int32_t ifx_mps_fw_wdog_start_ar9()
32 + return IFX_SUCCESS; /* FIXME - Disable start wdog... */
33 /* vpe1_wdog_ctr should be set up in u-boot as
34 "vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing
36 @@ -292,6 +302,18 @@ IFX_int32_t ifx_mps_download_firmware (m
37 decryption. Subtract sizeof(u32) from length to avoid decryption
38 of data beyond the FW image code */
39 pFWDwnld->length -= sizeof(IFX_uint32_t);
40 + switch(ltq_soc_type()) {
42 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;
45 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;
47 + case SOC_TYPE_VR9_2:
48 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;
51 + if (ifx_bsp_basic_mps_decrypt)
52 ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);
55 @@ -306,7 +328,7 @@ IFX_int32_t ifx_mps_download_firmware (m
56 TRACE (MPS, DBG_LEVEL_HIGH,
57 ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
58 pFW_img_data->crc32, cksum));
60 + /* return IFX_ERROR; -- FIXME */
64 @@ -454,62 +476,62 @@ IFX_int32_t ifx_mps_wdog_callback (IFX_u
68 - IFXOS_LOCKINT (flags);
69 - if (ifx_gpio_pin_reserve
70 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
72 - TRACE (MPS, DBG_LEVEL_HIGH,
73 - (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
74 - __FILE__, __func__, __LINE__));
76 +// IFXOS_LOCKINT (flags);
77 +// if (ifx_gpio_pin_reserve
78 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
80 +// TRACE (MPS, DBG_LEVEL_HIGH,
81 +// (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
82 +// __FILE__, __func__, __LINE__));
84 /* P1_ALTSEL0.15 = 0 */
85 - if (ifx_gpio_altsel0_clear
86 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
88 - TRACE (MPS, DBG_LEVEL_HIGH,
89 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
90 - __func__, __LINE__));
92 +// if (ifx_gpio_altsel0_clear
93 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
95 +// TRACE (MPS, DBG_LEVEL_HIGH,
96 +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
97 +// __func__, __LINE__));
99 /* P1_ALTSEL1.15 = 0 */
100 - if (ifx_gpio_altsel1_clear
101 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
103 - TRACE (MPS, DBG_LEVEL_HIGH,
104 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
105 - __func__, __LINE__));
107 +// if (ifx_gpio_altsel1_clear
108 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
110 +// TRACE (MPS, DBG_LEVEL_HIGH,
111 +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
112 +// __func__, __LINE__));
115 - if (ifx_gpio_dir_out_set
116 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
118 - TRACE (MPS, DBG_LEVEL_HIGH,
119 - (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
120 - __func__, __LINE__));
122 +// if (ifx_gpio_dir_out_set
123 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
125 +// TRACE (MPS, DBG_LEVEL_HIGH,
126 +// (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
127 +// __func__, __LINE__));
130 - if (ifx_gpio_open_drain_set
131 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
133 - TRACE (MPS, DBG_LEVEL_HIGH,
134 - (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
135 - __func__, __LINE__));
137 +// if (ifx_gpio_open_drain_set
138 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
140 +// TRACE (MPS, DBG_LEVEL_HIGH,
141 +// (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
142 +// __func__, __LINE__));
145 - if (ifx_gpio_output_clear
146 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
148 - TRACE (MPS, DBG_LEVEL_HIGH,
149 - (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
150 - __func__, __LINE__));
152 - if (ifx_gpio_pin_free
153 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
155 - TRACE (MPS, DBG_LEVEL_HIGH,
156 - (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
157 - __func__, __LINE__));
159 - IFXOS_UNLOCKINT (flags);
160 +// if (ifx_gpio_output_clear
161 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
163 +// TRACE (MPS, DBG_LEVEL_HIGH,
164 +// (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
165 +// __func__, __LINE__));
167 +// if (ifx_gpio_pin_free
168 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
170 +// TRACE (MPS, DBG_LEVEL_HIGH,
171 +// (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
172 +// __func__, __LINE__));
174 +// IFXOS_UNLOCKINT (flags);
176 /* recalculate and compare the firmware checksum */
177 ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
178 --- a/src/drv_vmmc_amazon_s.h
179 +++ b/src/drv_vmmc_amazon_s.h
183 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
184 -#include <asm/ifx/ifx_gpio.h>
185 +//#include <asm/ifx/ifx_gpio.h>
187 #error no system selected
191 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
193 - ret = VMMC_statusOk; \
194 - /* Reserve P0.0 as TDM/FSC */ \
195 - if (!GPIOreserved) \
196 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
197 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
198 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
199 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
201 - /* Reserve P1.9 as TDM/DO */ \
202 - if (!GPIOreserved) \
203 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
204 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
205 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
206 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
207 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
209 - /* Reserve P2.9 as TDM/DI */ \
210 - if (!GPIOreserved) \
211 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
212 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
213 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\
214 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
216 - /* Reserve P2.8 as TDM/DCL */ \
217 - if (!GPIOreserved) \
218 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
219 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
220 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
221 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
224 - /* TDM/FSC+DCL Master */ \
225 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
226 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
228 - /* TDM/FSC+DCL Slave */ \
229 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
230 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
235 @@ -73,11 +34,6 @@ do { \
237 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
239 - ret = VMMC_statusOk; \
240 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
241 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
242 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
243 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
246 #endif /* _DRV_VMMC_AMAZON_S_H */